Second round of core additions for the Allwinner SoCs
Fixes to select missing configuration options, and update of the maintainer file. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJSzIe4AAoJEBx+YmzsjxAgIVkQAI93/8h3n5lU1QWja7MTzQf1 x2A633WMy5v1gnlgwFGGPA6HexTmXlchWOK1GfpSMmMi+WZ606NX/eJwfIA/uR1p 8kXdFfCimQWisIm0qeutm0rRjRabwom2UgiMqw9RSistynloLopJrfDvRWM7ht9x lMv4sL0ZEb4ZyznM2BwlenO/J41pIGIKJLVCnN4ZrHTL3isW0stJ59j1RAPTA4Md EUr2uo5YJLkHJ5ecQ6Z9rUO5i9q1dN5oddQSvKIRhHLqVwl+pgRQJ60036VHgGLG nYC6QDAiQqIMooEjFAKPGfxcQxqrzYTg2OeWTGnD+U9U6j1BnxpMXMuA97bjpaJp LffLm8rCp0hlcUPPe19ctzqpvJtTuR+0h/zWFr9HoYGktR70CahmsIeDco9VUKan SB5xvsK2D7wXO/CXogc5bNm4utldN/VKsuiQdr8mIkkb2cThA4psPhq81PG4gTWd OggV3FNv38o0IH/yXcSgl6cOTeYQBL08R7m7FF77oQGqmwNQpLQhSBLS1htNgqU4 tMKF3isHXW85bOvaoqipwcsIUpIX6YBEurcVe4ObDkEqf3URQrCRXOOP/aHmmgf/ 7Dric/C38mX2kHLFdBeeq+ZbbHHF63UTbmWY4k5U0W4dzawdtmz3dJX3kAHvdtx0 upr+EThlakg9EMpp2rUw =TOqs -----END PGP SIGNATURE----- Merge tag 'sunxi-core-for-3.14-2' of https://github.com/mripard/linux into next/soc From Maxime Ripard: Second round of core additions for the Allwinner SoCs Fixes to select missing configuration options, and update of the maintainer file. * tag 'sunxi-core-for-3.14-2' of https://github.com/mripard/linux: ARM: sunxi: select ARM_PSCI MAINTAINERS: Update Allwinner sunXi maintainer files ARM: sunxi: Select RESET_CONTROLLER ARM: sun6i: Add SMP support for the Allwinner A31 dt-bindings: fix example of allwinner interrupt controller ARM: sunxi: Register the A31 reset IP in init_time ARM: sunxi: Select ARCH_HAS_RESET_CONTROLLER reset: Add Allwinner SoCs Reset Controller Driver Signed-off-by: Kevin Hilman <khilman@linaro.org>wifi-calibration
Kevin Hilman
commit
3e0a79695c
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@ -14,5 +14,5 @@ intc: interrupt-controller {
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compatible = "allwinner,sun4i-ic";
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reg = <0x01c20400 0x400>;
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interrupt-controller;
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#interrupt-cells = <2>;
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#interrupt-cells = <1>;
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};
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@ -766,7 +766,12 @@ ARM/Allwinner A1X SoC support
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M: Maxime Ripard <maxime.ripard@free-electrons.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: arch/arm/mach-sunxi/
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N: sun[x4567]i
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ARM/Allwinner SoC Clock Support
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M: Emilio López <emilio@elopez.com.ar>
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S: Maintained
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F: drivers/clk/sunxi/
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ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES
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M: Andrew Victor <linux@maxim.org.za>
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@ -1,7 +1,9 @@
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config ARCH_SUNXI
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bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
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select ARCH_HAS_RESET_CONTROLLER
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select ARCH_REQUIRE_GPIOLIB
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select ARM_GIC
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select ARM_PSCI
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select CLKSRC_MMIO
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select CLKSRC_OF
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select COMMON_CLK
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@ -10,5 +12,6 @@ config ARCH_SUNXI
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select HAVE_SMP
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select PINCTRL
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select PINCTRL_SUNXI
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select RESET_CONTROLLER
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select SPARSE_IRQ
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select SUN4I_TIMER
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@ -1 +1,2 @@
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obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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@ -0,0 +1,19 @@
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/*
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* Core functions for Allwinner SoCs
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*
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* Copyright (C) 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ARCH_SUNXI_COMMON_H_
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#define __ARCH_SUNXI_COMMON_H_
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void sun6i_secondary_startup(void);
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extern struct smp_operations sun6i_smp_ops;
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#endif /* __ARCH_SUNXI_COMMON_H_ */
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@ -0,0 +1,9 @@
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#include <linux/linkage.h>
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#include <linux/init.h>
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.section ".text.head", "ax"
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ENTRY(sun6i_secondary_startup)
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msr cpsr_fsxc, #0xd3
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b secondary_startup
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ENDPROC(sun6i_secondary_startup)
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@ -0,0 +1,124 @@
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/*
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* SMP support for Allwinner SoCs
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*
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* Copyright (C) 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* Based on code
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* Copyright (C) 2012-2013 Allwinner Ltd.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/memory.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/smp.h>
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#include "common.h"
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#define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu) ((cpu) * 0x40 + 0x64)
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#define CPUCFG_CPU_RST_CTRL_REG(cpu) (((cpu) + 1) * 0x40)
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#define CPUCFG_CPU_CTRL_REG(cpu) (((cpu) + 1) * 0x40 + 0x04)
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#define CPUCFG_CPU_STATUS_REG(cpu) (((cpu) + 1) * 0x40 + 0x08)
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#define CPUCFG_GEN_CTRL_REG 0x184
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#define CPUCFG_PRIVATE0_REG 0x1a4
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#define CPUCFG_PRIVATE1_REG 0x1a8
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#define CPUCFG_DBG_CTL0_REG 0x1e0
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#define CPUCFG_DBG_CTL1_REG 0x1e4
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#define PRCM_CPU_PWROFF_REG 0x100
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#define PRCM_CPU_PWR_CLAMP_REG(cpu) (((cpu) * 4) + 0x140)
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static void __iomem *cpucfg_membase;
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static void __iomem *prcm_membase;
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static DEFINE_SPINLOCK(cpu_lock);
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static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *node;
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node = of_find_compatible_node(NULL, NULL, "allwinner,sun6i-a31-prcm");
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if (!node) {
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pr_err("Missing A31 PRCM node in the device tree\n");
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return;
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}
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prcm_membase = of_iomap(node, 0);
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if (!prcm_membase) {
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pr_err("Couldn't map A31 PRCM registers\n");
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return;
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}
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node = of_find_compatible_node(NULL, NULL,
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"allwinner,sun6i-a31-cpuconfig");
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if (!node) {
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pr_err("Missing A31 CPU config node in the device tree\n");
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return;
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}
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cpucfg_membase = of_iomap(node, 0);
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if (!cpucfg_membase)
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pr_err("Couldn't map A31 CPU config registers\n");
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}
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static int sun6i_smp_boot_secondary(unsigned int cpu,
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struct task_struct *idle)
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{
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u32 reg;
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int i;
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if (!(prcm_membase && cpucfg_membase))
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return -EFAULT;
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spin_lock(&cpu_lock);
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/* Set CPU boot address */
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writel(virt_to_phys(sun6i_secondary_startup),
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cpucfg_membase + CPUCFG_PRIVATE0_REG);
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/* Assert the CPU core in reset */
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writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
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/* Assert the L1 cache in reset */
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reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
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writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);
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/* Disable external debug access */
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reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
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writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
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/* Power up the CPU */
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for (i = 0; i <= 8; i++)
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writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu));
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mdelay(10);
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/* Clear CPU power-off gating */
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reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG);
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writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG);
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mdelay(1);
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/* Deassert the CPU core reset */
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writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
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/* Enable back the external debug accesses */
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reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
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writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
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spin_unlock(&cpu_lock);
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return 0;
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}
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struct smp_operations sun6i_smp_ops __initdata = {
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.smp_prepare_cpus = sun6i_smp_prepare_cpus,
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.smp_boot_secondary = sun6i_smp_boot_secondary,
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};
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@ -10,6 +10,8 @@
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clocksource.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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@ -23,6 +25,8 @@
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#include <asm/mach/map.h>
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#include <asm/system_misc.h>
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#include "common.h"
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#define SUN4I_WATCHDOG_CTRL_REG 0x00
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#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
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#define SUN4I_WATCHDOG_MODE_REG 0x04
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@ -132,10 +136,20 @@ static const char * const sun6i_board_dt_compat[] = {
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NULL,
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};
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extern void __init sun6i_reset_init(void);
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static void __init sun6i_timer_init(void)
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{
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of_clk_init(NULL);
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sun6i_reset_init();
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clocksource_of_init();
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}
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DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family")
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.init_machine = sunxi_dt_init,
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.init_time = sun6i_timer_init,
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.dt_compat = sun6i_board_dt_compat,
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.restart = sun6i_restart,
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.smp = smp_ops(sun6i_smp_ops),
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MACHINE_END
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static const char * const sun7i_board_dt_compat[] = {
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@ -1 +1,2 @@
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obj-$(CONFIG_RESET_CONTROLLER) += core.o
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obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
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@ -0,0 +1,175 @@
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/*
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* Allwinner SoCs Reset Controller driver
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*
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* Copyright 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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||||
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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struct sunxi_reset_data {
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spinlock_t lock;
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void __iomem *membase;
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struct reset_controller_dev rcdev;
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};
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static int sunxi_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct sunxi_reset_data *data = container_of(rcdev,
|
||||
struct sunxi_reset_data,
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rcdev);
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int bank = id / BITS_PER_LONG;
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int offset = id % BITS_PER_LONG;
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||||
unsigned long flags;
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||||
u32 reg;
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||||
spin_lock_irqsave(&data->lock, flags);
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||||
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reg = readl(data->membase + (bank * 4));
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writel(reg & ~BIT(offset), data->membase + (bank * 4));
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||||
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||||
spin_unlock_irqrestore(&data->lock, flags);
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||||
|
||||
return 0;
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||||
}
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||||
|
||||
static int sunxi_reset_deassert(struct reset_controller_dev *rcdev,
|
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unsigned long id)
|
||||
{
|
||||
struct sunxi_reset_data *data = container_of(rcdev,
|
||||
struct sunxi_reset_data,
|
||||
rcdev);
|
||||
int bank = id / BITS_PER_LONG;
|
||||
int offset = id % BITS_PER_LONG;
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
spin_lock_irqsave(&data->lock, flags);
|
||||
|
||||
reg = readl(data->membase + (bank * 4));
|
||||
writel(reg | BIT(offset), data->membase + (bank * 4));
|
||||
|
||||
spin_unlock_irqrestore(&data->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct reset_control_ops sunxi_reset_ops = {
|
||||
.assert = sunxi_reset_assert,
|
||||
.deassert = sunxi_reset_deassert,
|
||||
};
|
||||
|
||||
static int sunxi_reset_init(struct device_node *np)
|
||||
{
|
||||
struct sunxi_reset_data *data;
|
||||
struct resource res;
|
||||
resource_size_t size;
|
||||
int ret;
|
||||
|
||||
data = kzalloc(sizeof(*data), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = of_address_to_resource(np, 0, &res);
|
||||
if (ret)
|
||||
goto err_alloc;
|
||||
|
||||
size = resource_size(&res);
|
||||
if (!request_mem_region(res.start, size, np->name)) {
|
||||
ret = -EBUSY;
|
||||
goto err_alloc;
|
||||
}
|
||||
|
||||
data->membase = ioremap(res.start, size);
|
||||
if (!data->membase) {
|
||||
ret = -ENOMEM;
|
||||
goto err_alloc;
|
||||
}
|
||||
|
||||
data->rcdev.owner = THIS_MODULE;
|
||||
data->rcdev.nr_resets = size * 32;
|
||||
data->rcdev.ops = &sunxi_reset_ops;
|
||||
data->rcdev.of_node = np;
|
||||
reset_controller_register(&data->rcdev);
|
||||
|
||||
return 0;
|
||||
|
||||
err_alloc:
|
||||
kfree(data);
|
||||
return ret;
|
||||
};
|
||||
|
||||
/*
|
||||
* These are the reset controller we need to initialize early on in
|
||||
* our system, before we can even think of using a regular device
|
||||
* driver for it.
|
||||
*/
|
||||
static const struct of_device_id sunxi_early_reset_dt_ids[] __initdata = {
|
||||
{ .compatible = "allwinner,sun6i-a31-ahb1-reset", },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
void __init sun6i_reset_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
for_each_matching_node(np, sunxi_early_reset_dt_ids)
|
||||
sunxi_reset_init(np);
|
||||
}
|
||||
|
||||
/*
|
||||
* And these are the controllers we can register through the regular
|
||||
* device model.
|
||||
*/
|
||||
static const struct of_device_id sunxi_reset_dt_ids[] = {
|
||||
{ .compatible = "allwinner,sun6i-a31-clock-reset", },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sunxi_reset_dt_ids);
|
||||
|
||||
static int sunxi_reset_probe(struct platform_device *pdev)
|
||||
{
|
||||
return sunxi_reset_init(pdev->dev.of_node);
|
||||
}
|
||||
|
||||
static int sunxi_reset_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sunxi_reset_data *data = platform_get_drvdata(pdev);
|
||||
|
||||
reset_controller_unregister(&data->rcdev);
|
||||
iounmap(data->membase);
|
||||
kfree(data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver sunxi_reset_driver = {
|
||||
.probe = sunxi_reset_probe,
|
||||
.remove = sunxi_reset_remove,
|
||||
.driver = {
|
||||
.name = "sunxi-reset",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = sunxi_reset_dt_ids,
|
||||
},
|
||||
};
|
||||
module_platform_driver(sunxi_reset_driver);
|
||||
|
||||
MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
|
||||
MODULE_DESCRIPTION("Allwinner SoCs Reset Controller Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue