[PATCH] powerpc: Fix building of power3 config on ppc32
The spinlock_types.h merge renamed the structure for raw_spinlock_t to match ppc64. In doing so some of the spinlock macros/functions needed to be updated to match. Apparently, this seems to only be caught when building power3. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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@ -9,7 +9,7 @@
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* (the type definitions are in asm/raw_spinlock_types.h)
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*/
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#define __raw_spin_is_locked(x) ((x)->lock != 0)
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#define __raw_spin_is_locked(x) ((x)->slock != 0)
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#define __raw_spin_unlock_wait(lock) \
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do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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@ -31,17 +31,17 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
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bne- 2b\n\
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isync"
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: "=&r"(tmp)
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: "r"(&lock->lock), "r"(1)
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: "r"(&lock->slock), "r"(1)
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: "cr0", "memory");
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}
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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__asm__ __volatile__("eieio # __raw_spin_unlock": : :"memory");
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lock->lock = 0;
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lock->slock = 0;
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}
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#define __raw_spin_trylock(l) (!test_and_set_bit(0,&(l)->lock))
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#define __raw_spin_trylock(l) (!test_and_set_bit(0,(volatile unsigned long *)(&(l)->slock)))
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/*
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* Read-write spinlocks, allowing multiple readers
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