Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/cooloney/blackfin-2.6
* 'master' of master.kernel.org:/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: Blackfin arch: add proper const volatile to addr argument to the read functions Blackfin arch: Add definition of dma_mapping_error Blackfin arch: move cond_syscall() behind __KERNEL__ like all other architectures Blackfin arch: match kernel startup messaage with new linker script Blackfin arch: add missing braces around array bfin serial init Blackfin arch: update printk to use KERN_EMERG and reformat crash output Blackfin arch: update ANOMALY handling
This commit is contained in:
commit
3f2c6d0f4f
|
@ -329,9 +329,10 @@ void __init setup_arch(char **cmdline_p)
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printk(KERN_INFO "Memory map:\n"
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KERN_INFO " text = 0x%p-0x%p\n"
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KERN_INFO " init = 0x%p-0x%p\n"
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KERN_INFO " rodata = 0x%p-0x%p\n"
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KERN_INFO " data = 0x%p-0x%p\n"
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KERN_INFO " stack = 0x%p-0x%p\n"
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KERN_INFO " stack = 0x%p-0x%p\n"
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KERN_INFO " init = 0x%p-0x%p\n"
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KERN_INFO " bss = 0x%p-0x%p\n"
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KERN_INFO " available = 0x%p-0x%p\n"
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#ifdef CONFIG_MTD_UCLINUX
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@ -341,9 +342,10 @@ void __init setup_arch(char **cmdline_p)
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KERN_INFO " DMA Zone = 0x%p-0x%p\n"
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#endif
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, _stext, _etext,
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__init_begin, __init_end,
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__start_rodata, __end_rodata,
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_sdata, _edata,
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(void*)&init_thread_union, (void*)((int)(&init_thread_union) + 0x2000),
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__init_begin, __init_end,
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__bss_start, __bss_stop,
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(void*)_ramstart, (void*)memory_end
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#ifdef CONFIG_MTD_UCLINUX
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@ -148,8 +148,15 @@ asmlinkage void trap_c(struct pt_regs *fp)
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unsigned long trapnr = fp->seqstat & SEQSTAT_EXCAUSE;
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#ifdef CONFIG_KGDB
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# define CHK_DEBUGGER_TRAP() do { CHK_DEBUGGER(trapnr, sig, info.si_code, fp,); } while (0)
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# define CHK_DEBUGGER_TRAP_MAYBE() do { if (kgdb_connected) CHK_DEBUGGER_TRAP(); } while (0)
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# define CHK_DEBUGGER_TRAP() \
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do { \
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CHK_DEBUGGER(trapnr, sig, info.si_code, fp); \
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} while (0)
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# define CHK_DEBUGGER_TRAP_MAYBE() \
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do { \
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if (kgdb_connected) \
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CHK_DEBUGGER_TRAP(); \
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} while (0)
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#else
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# define CHK_DEBUGGER_TRAP() do { } while (0)
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# define CHK_DEBUGGER_TRAP_MAYBE() do { } while (0)
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@ -297,7 +304,8 @@ asmlinkage void trap_c(struct pt_regs *fp)
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info.si_code = ILL_CPLB_MULHIT;
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#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
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sig = SIGSEGV;
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printk(KERN_EMERG "\n\nNULL pointer access (probably)\n");
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printk(KERN_EMERG "\n"
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KERN_EMERG "NULL pointer access (probably)\n");
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#else
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sig = SIGILL;
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printk(KERN_EMERG EXC_0x27);
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@ -418,7 +426,9 @@ asmlinkage void trap_c(struct pt_regs *fp)
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if (current->mm) {
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fp->pc = current->mm->start_code;
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} else {
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printk(KERN_EMERG "I can't return to memory that doesn't exist - bad things happen\n");
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printk(KERN_EMERG
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"I can't return to memory that doesn't exist"
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" - bad things happen\n");
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panic("Help - I've fallen and can't get up\n");
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}
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}
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@ -522,15 +532,19 @@ EXPORT_SYMBOL(dump_stack);
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void dump_bfin_regs(struct pt_regs *fp, void *retaddr)
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{
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if (current->pid) {
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printk("\nCURRENT PROCESS:\n\n");
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printk("COMM=%s PID=%d\n", current->comm, current->pid);
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printk(KERN_EMERG "\n" KERN_EMERG "CURRENT PROCESS:\n"
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KERN_EMERG "\n");
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printk(KERN_EMERG "COMM=%s PID=%d\n",
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current->comm, current->pid);
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} else {
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printk
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("\nNo Valid pid - Either things are really messed up, or you are in the kernel\n");
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(KERN_EMERG "\n" KERN_EMERG
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"No Valid pid - Either things are really messed up,"
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" or you are in the kernel\n");
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}
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if (current->mm) {
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printk("TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n"
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printk(KERN_EMERG "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n"
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"BSS = 0x%p-0x%p USER-STACK = 0x%p\n\n",
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(void*)current->mm->start_code,
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(void*)current->mm->end_code,
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@ -541,7 +555,7 @@ void dump_bfin_regs(struct pt_regs *fp, void *retaddr)
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(void*)current->mm->start_stack);
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}
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printk("return address: 0x%p; contents of [PC-16...PC+8]:\n", retaddr);
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printk(KERN_EMERG "return address: [0x%p]; contents of:", retaddr);
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if (retaddr != 0 && retaddr <= (void*)physical_mem_end
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#if L1_CODE_LENGTH != 0
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/* FIXME: Copy the code out of L1 Instruction SRAM through dma
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@ -550,10 +564,15 @@ void dump_bfin_regs(struct pt_regs *fp, void *retaddr)
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&& retaddr < (void*)(L1_CODE_START + L1_CODE_LENGTH))
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#endif
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) {
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int i = 0;
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int i = ((unsigned int)retaddr & 0xFFFFFFF0) - 32;
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unsigned short x = 0;
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for (i = -16; i < 8; i++) {
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if (get_user(x, (unsigned short *)retaddr + i))
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for (; i < ((unsigned int)retaddr & 0xFFFFFFF0 ) + 32 ;
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i += 2) {
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if ( !(i & 0xF) )
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printk(KERN_EMERG "\n" KERN_EMERG
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"0x%08x: ", i);
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if (get_user(x, (unsigned short *)i))
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break;
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#ifndef CONFIG_DEBUG_HWERR
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/* If one of the last few instructions was a STI
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@ -561,53 +580,65 @@ void dump_bfin_regs(struct pt_regs *fp, void *retaddr)
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* and we just noticed
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*/
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if (x >= 0x0040 && x <= 0x0047 && i <= 0)
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panic("\n\nWARNING : You should reconfigure the kernel to turn on\n"
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" 'Hardware error interrupt debugging'\n"
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" The rest of this error is meanless\n");
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panic("\n\nWARNING : You should reconfigure"
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" the kernel to turn on\n"
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" 'Hardware error interrupt"
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" debugging'\n"
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" The rest of this error"
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" is meanless\n");
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#endif
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if (i == -8)
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printk("\n");
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if (i == 0)
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printk("X\n");
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printk("%04x ", x);
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if ( i == (unsigned int)retaddr )
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printk("[%04x]", x);
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else
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printk(" %04x ", x);
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}
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printk("\n" KERN_EMERG "\n");
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} else
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printk("Cannot look at the [PC] for it is in unreadable L1 SRAM - sorry\n");
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printk(KERN_EMERG
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"Cannot look at the [PC] for it is"
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"in unreadable L1 SRAM - sorry\n");
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printk("\n\n");
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printk("RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n",
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fp->rete, fp->retn, fp->retx, fp->rets);
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printk("IPEND: %04lx SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
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printk("SEQSTAT: %08lx SP: %08lx\n", (long)fp->seqstat, (long)fp);
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printk("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n",
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fp->r0, fp->r1, fp->r2, fp->r3);
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printk("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n",
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fp->r4, fp->r5, fp->r6, fp->r7);
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printk("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n",
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fp->p0, fp->p1, fp->p2, fp->p3);
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printk("P4: %08lx P5: %08lx FP: %08lx\n", fp->p4, fp->p5, fp->fp);
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printk("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
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fp->a0w, fp->a0x, fp->a1w, fp->a1x);
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printk(KERN_EMERG
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"RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n",
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fp->rete, fp->retn, fp->retx, fp->rets);
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printk(KERN_EMERG "IPEND: %04lx SYSCFG: %04lx\n",
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fp->ipend, fp->syscfg);
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printk(KERN_EMERG "SEQSTAT: %08lx SP: %08lx\n",
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(long)fp->seqstat, (long)fp);
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printk(KERN_EMERG "R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n",
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fp->r0, fp->r1, fp->r2, fp->r3);
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printk(KERN_EMERG "R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n",
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fp->r4, fp->r5, fp->r6, fp->r7);
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printk(KERN_EMERG "P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n",
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fp->p0, fp->p1, fp->p2, fp->p3);
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printk(KERN_EMERG
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"P4: %08lx P5: %08lx FP: %08lx\n",
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fp->p4, fp->p5, fp->fp);
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printk(KERN_EMERG
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"A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
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fp->a0w, fp->a0x, fp->a1w, fp->a1x);
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printk("LB0: %08lx LT0: %08lx LC0: %08lx\n", fp->lb0, fp->lt0,
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fp->lc0);
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printk("LB1: %08lx LT1: %08lx LC1: %08lx\n", fp->lb1, fp->lt1,
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fp->lc1);
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printk("B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n", fp->b0, fp->l0,
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fp->m0, fp->i0);
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printk("B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n", fp->b1, fp->l1,
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fp->m1, fp->i1);
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printk("B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n", fp->b2, fp->l2,
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fp->m2, fp->i2);
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printk("B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n", fp->b3, fp->l3,
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fp->m3, fp->i3);
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printk(KERN_EMERG "LB0: %08lx LT0: %08lx LC0: %08lx\n",
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fp->lb0, fp->lt0, fp->lc0);
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printk(KERN_EMERG "LB1: %08lx LT1: %08lx LC1: %08lx\n",
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fp->lb1, fp->lt1, fp->lc1);
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printk(KERN_EMERG "B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n",
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fp->b0, fp->l0, fp->m0, fp->i0);
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printk(KERN_EMERG "B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n",
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fp->b1, fp->l1, fp->m1, fp->i1);
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printk(KERN_EMERG "B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n",
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fp->b2, fp->l2, fp->m2, fp->i2);
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printk(KERN_EMERG "B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n",
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fp->b3, fp->l3, fp->m3, fp->i3);
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|
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printk("\nUSP: %08lx ASTAT: %08lx\n", rdusp(), fp->astat);
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printk(KERN_EMERG "\n" KERN_EMERG "USP: %08lx ASTAT: %08lx\n",
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rdusp(), fp->astat);
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if ((long)fp->seqstat & SEQSTAT_EXCAUSE) {
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printk(KERN_EMERG "DCPLB_FAULT_ADDR=%p\n", (void*)bfin_read_DCPLB_FAULT_ADDR());
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printk(KERN_EMERG "ICPLB_FAULT_ADDR=%p\n", (void*)bfin_read_ICPLB_FAULT_ADDR());
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printk(KERN_EMERG "DCPLB_FAULT_ADDR=%p\n",
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(void *)bfin_read_DCPLB_FAULT_ADDR());
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printk(KERN_EMERG "ICPLB_FAULT_ADDR=%p\n",
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(void *)bfin_read_ICPLB_FAULT_ADDR());
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}
|
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|
||||
printk("\n\n");
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||||
|
|
|
@ -61,7 +61,12 @@ ENTRY(_memcmp)
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|||
|
||||
LSETUP (.Lquad_loop_s, .Lquad_loop_e) LC0=P1;
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||||
.Lquad_loop_s:
|
||||
#ifdef ANOMALY_05000202
|
||||
R0 = [P0++];
|
||||
R1 = [I0++];
|
||||
#else
|
||||
MNOP || R0 = [P0++] || R1 = [I0++];
|
||||
#endif
|
||||
CC = R0 == R1;
|
||||
IF !CC JUMP .Lquad_different;
|
||||
.Lquad_loop_e:
|
||||
|
|
|
@ -94,13 +94,20 @@ ENTRY(_memcpy)
|
|||
.Lmore_than_seven:
|
||||
/* There's at least eight bytes to copy. */
|
||||
P2 += -1; /* because we unroll one iteration */
|
||||
LSETUP(.Lword_loop, .Lword_loop) LC0=P2;
|
||||
LSETUP(.Lword_loops, .Lword_loope) LC0=P2;
|
||||
R0 = R1;
|
||||
I1 = P1;
|
||||
R3 = [I1++];
|
||||
.Lword_loop:
|
||||
#ifdef ANOMALY_05000202
|
||||
.Lword_loops:
|
||||
[P0++] = R3;
|
||||
.Lword_loope:
|
||||
R3 = [I1++];
|
||||
#else
|
||||
.Lword_loops:
|
||||
.Lword_loope:
|
||||
MNOP || [P0++] = R3 || R3 = [I1++];
|
||||
|
||||
#endif
|
||||
[P0++] = R3;
|
||||
/* Any remaining bytes to copy? */
|
||||
R3 = 0x3;
|
||||
|
|
|
@ -69,8 +69,17 @@ ENTRY(_memmove)
|
|||
P2 = R2; /* set remainder */
|
||||
R1 = [I0++];
|
||||
|
||||
LSETUP (.Lquad_loop, .Lquad_loop) LC0=P1;
|
||||
.Lquad_loop: MNOP || [P0++] = R1 || R1 = [I0++];
|
||||
LSETUP (.Lquad_loops, .Lquad_loope) LC0=P1;
|
||||
#ifdef ANOMALY_05000202
|
||||
.Lquad_loops:
|
||||
[P0++] = R1;
|
||||
.Lquad_loope:
|
||||
R1 = [I0++];
|
||||
#else
|
||||
.Lquad_loops:
|
||||
.Lquad_loope:
|
||||
MNOP || [P0++] = R1 || R1 = [I0++];
|
||||
#endif
|
||||
[P0++] = R1;
|
||||
|
||||
CC = P2 == 0; /* any remaining bytes? */
|
||||
|
@ -93,6 +102,10 @@ ENTRY(_memmove)
|
|||
R1 = B[P3--] (Z);
|
||||
CC = P2 == 0;
|
||||
IF CC JUMP .Lno_loop;
|
||||
#ifdef ANOMALY_05000245
|
||||
NOP;
|
||||
NOP;
|
||||
#endif
|
||||
LSETUP (.Lol_s, .Lol_e) LC0 = P2;
|
||||
.Lol_s: B[P0--] = R1;
|
||||
.Lol_e: R1 = B[P3--] (Z);
|
||||
|
|
|
@ -123,14 +123,14 @@ ENTRY(_blackfin_icache_flush_range)
|
|||
R2 = R0 & R2;
|
||||
P0 = R2;
|
||||
P1 = R1;
|
||||
CSYNC;
|
||||
CSYNC(R3);
|
||||
IFLUSH [P0];
|
||||
1:
|
||||
IFLUSH [P0++];
|
||||
CC = P0 < P1 (iu);
|
||||
IF CC JUMP 1b (bp);
|
||||
IFLUSH [P0];
|
||||
SSYNC;
|
||||
SSYNC(R3);
|
||||
RTS;
|
||||
ENDPROC(_blackfin_icache_flush_range)
|
||||
|
||||
|
@ -148,7 +148,7 @@ ENTRY(_blackfin_icache_dcache_flush_range)
|
|||
R2 = R0 & R2;
|
||||
P0 = R2;
|
||||
P1 = R1;
|
||||
CSYNC;
|
||||
CSYNC(R3);
|
||||
IFLUSH [P0];
|
||||
1:
|
||||
FLUSH [P0];
|
||||
|
@ -157,7 +157,7 @@ ENTRY(_blackfin_icache_dcache_flush_range)
|
|||
IF CC JUMP 1b (bp);
|
||||
IFLUSH [P0];
|
||||
FLUSH [P0];
|
||||
SSYNC;
|
||||
SSYNC(R3);
|
||||
RTS;
|
||||
ENDPROC(_blackfin_icache_dcache_flush_range)
|
||||
|
||||
|
@ -174,7 +174,7 @@ ENTRY(_blackfin_dcache_invalidate_range)
|
|||
R2 = R0 & R2;
|
||||
P0 = R2;
|
||||
P1 = R1;
|
||||
CSYNC;
|
||||
CSYNC(R3);
|
||||
FLUSHINV[P0];
|
||||
1:
|
||||
FLUSHINV[P0++];
|
||||
|
@ -186,7 +186,7 @@ ENTRY(_blackfin_dcache_invalidate_range)
|
|||
* so do one more.
|
||||
*/
|
||||
FLUSHINV[P0];
|
||||
SSYNC;
|
||||
SSYNC(R3);
|
||||
RTS;
|
||||
ENDPROC(_blackfin_dcache_invalidate_range)
|
||||
|
||||
|
@ -235,7 +235,7 @@ ENTRY(_blackfin_dcache_flush_range)
|
|||
R2 = R0 & R2;
|
||||
P0 = R2;
|
||||
P1 = R1;
|
||||
CSYNC;
|
||||
CSYNC(R3);
|
||||
FLUSH[P0];
|
||||
1:
|
||||
FLUSH[P0++];
|
||||
|
@ -247,17 +247,17 @@ ENTRY(_blackfin_dcache_flush_range)
|
|||
* one more.
|
||||
*/
|
||||
FLUSH[P0];
|
||||
SSYNC;
|
||||
SSYNC(R3);
|
||||
RTS;
|
||||
ENDPROC(_blackfin_dcache_flush_range)
|
||||
|
||||
ENTRY(_blackfin_dflush_page)
|
||||
P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT);
|
||||
P0 = R0;
|
||||
CSYNC;
|
||||
CSYNC(R3);
|
||||
FLUSH[P0];
|
||||
LSETUP (.Lfl1, .Lfl1) LC0 = P1;
|
||||
.Lfl1: FLUSH [P0++];
|
||||
SSYNC;
|
||||
SSYNC(R3);
|
||||
RTS;
|
||||
ENDPROC(_blackfin_dflush_page)
|
||||
|
|
|
@ -139,7 +139,7 @@ __common_int_entry:
|
|||
fp = 0;
|
||||
#endif
|
||||
|
||||
#ifdef ANOMALY_05000283
|
||||
#if defined (ANOMALY_05000283) || defined (ANOMALY_05000315)
|
||||
cc = r7 == r7;
|
||||
p5.h = 0xffc0;
|
||||
p5.l = 0x0014;
|
||||
|
|
|
@ -39,7 +39,9 @@ static inline void SSYNC (void)
|
|||
#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
|
||||
static inline void SSYNC (void)
|
||||
{
|
||||
__builtin_bfin_ssync();
|
||||
__asm__ __volatile__ ("nop; nop; nop;\n\t"
|
||||
"ssync;\n\t"
|
||||
::);
|
||||
}
|
||||
#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
|
||||
static inline void SSYNC (void)
|
||||
|
@ -71,7 +73,9 @@ static inline void CSYNC (void)
|
|||
#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
|
||||
static inline void CSYNC (void)
|
||||
{
|
||||
__builtin_bfin_csync();
|
||||
__asm__ __volatile__ ("nop; nop; nop;\n\t"
|
||||
"ssync;\n\t"
|
||||
::);
|
||||
}
|
||||
#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
|
||||
static inline void CSYNC (void)
|
||||
|
@ -80,6 +84,31 @@ static inline void CSYNC (void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#else /* __ASSEMBLY__ */
|
||||
|
||||
/* SSYNC & CSYNC implementations for assembly files */
|
||||
|
||||
#define ssync(x) SSYNC(x)
|
||||
#define csync(x) CSYNC(x)
|
||||
|
||||
#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
|
||||
#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
|
||||
#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
|
||||
|
||||
#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
|
||||
#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
|
||||
#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
|
||||
|
||||
#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
|
||||
#define SSYNC(scratch) nop; nop; nop; SSYNC;
|
||||
#define CSYNC(scratch) nop; nop; nop; CSYNC;
|
||||
|
||||
#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
|
||||
#define SSYNC(scratch) SSYNC;
|
||||
#define CSYNC(scratch) CSYNC;
|
||||
|
||||
#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _BLACKFIN_H_ */
|
||||
|
|
|
@ -15,6 +15,8 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
|
|||
#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
|
||||
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
|
||||
|
||||
#define dma_mapping_error
|
||||
|
||||
/*
|
||||
* Map a single buffer of the indicated size for DMA in streaming mode.
|
||||
* The 32-bit bus address to use is returned.
|
||||
|
|
|
@ -20,7 +20,7 @@
|
|||
*/
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
static inline unsigned char readb(void __iomem *addr)
|
||||
static inline unsigned char readb(const volatile void __iomem *addr)
|
||||
{
|
||||
unsigned int val;
|
||||
int tmp;
|
||||
|
@ -35,7 +35,7 @@ static inline unsigned char readb(void __iomem *addr)
|
|||
return (unsigned char) val;
|
||||
}
|
||||
|
||||
static inline unsigned short readw(void __iomem *addr)
|
||||
static inline unsigned short readw(const volatile void __iomem *addr)
|
||||
{
|
||||
unsigned int val;
|
||||
int tmp;
|
||||
|
@ -50,7 +50,7 @@ static inline unsigned short readw(void __iomem *addr)
|
|||
return (unsigned short) val;
|
||||
}
|
||||
|
||||
static inline unsigned int readl(void __iomem *addr)
|
||||
static inline unsigned int readl(const volatile void __iomem *addr)
|
||||
{
|
||||
unsigned int val;
|
||||
int tmp;
|
||||
|
|
|
@ -43,7 +43,8 @@
|
|||
#endif
|
||||
|
||||
/* Issues that are common to 0.5, 0.4, and 0.3 silicon */
|
||||
#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
|
||||
#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) \
|
||||
|| defined(CONFIG_BF_REV_0_3))
|
||||
#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
|
||||
slot1 and store of a P register in slot 2 is not
|
||||
supported */
|
||||
|
@ -76,11 +77,16 @@
|
|||
control */
|
||||
#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
|
||||
killed in a particular stage*/
|
||||
#define ANOMALY_05000311 /* Erroneous flag pin operations under specific
|
||||
sequences */
|
||||
#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
|
||||
registers are interrupted */
|
||||
#define ANOMALY_05000311 /* Erroneous flag pin operations under specific sequences*/
|
||||
|
||||
#endif
|
||||
#define ANOMALY_05000313 /* PPI Is Level-Sensitive on First Transfer */
|
||||
#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously On
|
||||
* Next System MMR Access */
|
||||
#define ANOMALY_05000319 /* Internal Voltage Regulator Values of 1.05V, 1.10V
|
||||
* and 1.15V Not Allowed for LQFP Packages */
|
||||
#endif /* Issues that are common to 0.5, 0.4, and 0.3 silicon */
|
||||
|
||||
/* These issues only occur on 0.3 or 0.4 BF533 */
|
||||
#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
|
||||
|
@ -134,14 +140,14 @@
|
|||
internal voltage regulator (VDDint) to increase. */
|
||||
#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
|
||||
internal voltage regulator (VDDint) to decrease */
|
||||
#endif
|
||||
#endif /* issues only occur on 0.3 or 0.4 BF533 */
|
||||
|
||||
/* These issues are only on 0.4 silicon */
|
||||
#if (defined(CONFIG_BF_REV_0_4))
|
||||
#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
|
||||
#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
|
||||
(TDM) */
|
||||
#endif
|
||||
#endif /* issues are only on 0.4 silicon */
|
||||
|
||||
/* These issues are only on 0.3 silicon */
|
||||
#if defined(CONFIG_BF_REV_0_3)
|
||||
|
@ -170,6 +176,72 @@
|
|||
#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
|
||||
Sync Transmit Mode */
|
||||
#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
|
||||
#endif /* only on 0.3 silicon */
|
||||
|
||||
#if defined(CONFIG_BF_REV_0_2)
|
||||
#define ANOMALY_05000067 /* Watchpoints (Hardware Breakpoints) are not
|
||||
* supported */
|
||||
#define ANOMALY_05000109 /* Reserved bits in SYSCFG register not set at
|
||||
* power on */
|
||||
#define ANOMALY_05000116 /* Trace Buffers may record discontinuities into
|
||||
* emulation mode and/or exception, NMI, reset
|
||||
* handlers */
|
||||
#define ANOMALY_05000123 /* DTEST_COMMAND initiated memory access may be
|
||||
* incorrect if data cache or DMA is active */
|
||||
#define ANOMALY_05000124 /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1,
|
||||
* or 1:1 */
|
||||
#define ANOMALY_05000125 /* Erroneous exception when enabling cache */
|
||||
#define ANOMALY_05000126 /* SPI clock polarity and phase bits incorrect
|
||||
* during booting */
|
||||
#define ANOMALY_05000137 /* DMEM_CONTROL is not set on Reset */
|
||||
#define ANOMALY_05000138 /* SPI boot will not complete if there is a zero fill
|
||||
* block in the loader file */
|
||||
#define ANOMALY_05000140 /* Allowing the SPORT RX FIFO to fill will cause an
|
||||
* overflow */
|
||||
#define ANOMALY_05000141 /* An Infinite Stall occurs with a particular sequence
|
||||
* of consecutive dual dag events */
|
||||
#define ANOMALY_05000142 /* Interrupts may be lost when a programmable input
|
||||
* flag is configured to be edge sensitive */
|
||||
#define ANOMALY_05000143 /* A read from external memory may return a wrong
|
||||
* value with data cache enabled */
|
||||
#define ANOMALY_05000144 /* DMA and TESTSET conflict when both are accessing
|
||||
* external memory */
|
||||
#define ANOMALY_05000145 /* In PWM_OUT mode, you must enable the PPI block to
|
||||
* generate a waveform from PPI_CLK */
|
||||
#define ANOMALY_05000146 /* MDMA may lose the first few words of a descriptor
|
||||
* chain */
|
||||
#define ANOMALY_05000147 /* The source MDMA descriptor may stop with a DMA
|
||||
* Error */
|
||||
#define ANOMALY_05000148 /* When booting from a 16-bit asynchronous memory
|
||||
* device, the upper 8-bits of each word must be
|
||||
* 0x00 */
|
||||
#define ANOMALY_05000153 /* Frame Delay in SPORT Multichannel Mode */
|
||||
#define ANOMALY_05000154 /* SPORT TFS signal is active in Multi-channel mode
|
||||
* outside of valid channels */
|
||||
#define ANOMALY_05000155 /* Timer1 can not be used for PWMOUT mode when a
|
||||
* certain PPI mode is in use */
|
||||
#define ANOMALY_05000157 /* A killed 32-bit System MMR write will lead to
|
||||
* the next system MMR access thinking it should be
|
||||
* 32-bit. */
|
||||
#define ANOMALY_05000163 /* SPORT transmit data is not gated by external frame
|
||||
* sync in certain conditions */
|
||||
#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */
|
||||
#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost
|
||||
* write-through cache data writes */
|
||||
#define ANOMALY_05000173 /* DMA vs Core accesses to external memory */
|
||||
#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */
|
||||
#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */
|
||||
#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an
|
||||
* accumulator saturation */
|
||||
#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration
|
||||
* registers */
|
||||
#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */
|
||||
#define ANOMALY_05000191 /* PPI does not invert the Driving PPICLK edge in
|
||||
* Transmit Modes */
|
||||
#define ANOMALY_05000192 /* In PPI Transmit Modes with External Frame Syncs
|
||||
* POLC */
|
||||
#define ANOMALY_05000206 /* Internal Voltage Regulator may not start up */
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* _MACH_ANOMALY_H_ */
|
||||
|
|
|
@ -78,6 +78,7 @@ struct bfin_serial_res {
|
|||
};
|
||||
|
||||
struct bfin_serial_res bfin_serial_resource[] = {
|
||||
{
|
||||
0xFFC00400,
|
||||
IRQ_UART_RX,
|
||||
#ifdef CONFIG_SERIAL_BFIN_DMA
|
||||
|
@ -88,6 +89,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
|
|||
CONFIG_UART0_CTS_PIN,
|
||||
CONFIG_UART0_RTS_PIN,
|
||||
#endif
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
|
|
|
@ -73,8 +73,13 @@
|
|||
control */
|
||||
#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
|
||||
killed in a particular stage*/
|
||||
#define ANOMALY_05000310 /* False hardware errors caused by fetches at the
|
||||
* boundary of reserved memory */
|
||||
#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
|
||||
registers are interrupted */
|
||||
#define ANOMALY_05000313 /* PPI is level sensitive on first transfer */
|
||||
#define ANOMALY_05000322 /* EMAC RMII mode at 10-Base-T speed: RX frames not
|
||||
* received properly */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BF_REV_0_2)
|
||||
|
@ -114,7 +119,21 @@
|
|||
DMA system instability */
|
||||
#define ANOMALY_05000280 /* SPI Master boot mode does not work well with
|
||||
Atmel Dataflash devices */
|
||||
|
||||
#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context
|
||||
* is not restored */
|
||||
#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
|
||||
* control */
|
||||
#define ANOMALY_05000283 /* System MMR Write Is Stalled Indefinitely When
|
||||
* Killed in a Particular Stage */
|
||||
#define ANOMALY_05000285 /* New Feature: EMAC TX DMA Word Alignment
|
||||
* (Not Available On Older Silicon) */
|
||||
#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */
|
||||
#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously
|
||||
* On Next System MMR Access */
|
||||
#define ANOMALY_05000316 /* EMAC RMII mode: collisions occur in Full Duplex
|
||||
* mode */
|
||||
#define ANOMALY_05000321 /* EMAC RMII mode: TX frames in half duplex fail with
|
||||
* status No Carrier */
|
||||
#endif /* CONFIG_BF_REV_0_2 */
|
||||
|
||||
#endif /* _MACH_ANOMALY_H_ */
|
||||
|
|
|
@ -78,6 +78,7 @@ struct bfin_serial_res {
|
|||
};
|
||||
|
||||
struct bfin_serial_res bfin_serial_resource[] = {
|
||||
{
|
||||
0xFFC00400,
|
||||
IRQ_UART_RX,
|
||||
#ifdef CONFIG_SERIAL_BFIN_DMA
|
||||
|
@ -88,6 +89,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
|
|||
CONFIG_UART0_CTS_PIN,
|
||||
CONFIG_UART0_RTS_PIN,
|
||||
#endif
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
|
|
|
@ -39,7 +39,20 @@
|
|||
#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS)
|
||||
#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
|
||||
#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
|
||||
#ifdef ANOMALY_05000125
|
||||
static __inline__ void bfin_write_DMEM_CONTROL(unsigned int val)
|
||||
{
|
||||
unsigned long flags, iwr;
|
||||
|
||||
local_irq_save(flags);
|
||||
__asm__(".align 8\n");
|
||||
bfin_write32(IMEM_CONTROL, val);
|
||||
__builtin_bfin_ssync();
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
#else
|
||||
#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
|
||||
#endif
|
||||
#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
|
||||
#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val)
|
||||
#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR)
|
||||
|
@ -125,7 +138,21 @@
|
|||
#define DTEST_DATA3 0xFFE0040C
|
||||
*/
|
||||
#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
|
||||
#ifdef ANOMALY_05000125
|
||||
static __inline__ void bfin_write_IMEM_CONTROL(unsigned int val)
|
||||
{
|
||||
unsigned long flags, iwr;
|
||||
|
||||
local_irq_save(flags);
|
||||
__asm__(".align 8\n");
|
||||
bfin_write32(IMEM_CONTROL, val);
|
||||
__builtin_bfin_ssync();
|
||||
local_irq_restore(flags);
|
||||
|
||||
}
|
||||
#else
|
||||
#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val)
|
||||
#endif
|
||||
#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
|
||||
#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val)
|
||||
#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)
|
||||
|
|
|
@ -369,7 +369,6 @@
|
|||
#define __ARCH_WANT_SYS_NICE
|
||||
#define __ARCH_WANT_SYS_RT_SIGACTION
|
||||
#define __ARCH_WANT_SYS_RT_SIGSUSPEND
|
||||
#endif
|
||||
|
||||
/*
|
||||
* "Conditional" syscalls
|
||||
|
@ -379,4 +378,6 @@
|
|||
*/
|
||||
#define cond_syscall(x) asm(".weak\t_" #x "\n\t.set\t_" #x ",_sys_ni_syscall");
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* __ASM_BFIN_UNISTD_H */
|
||||
|
|
Loading…
Reference in a new issue