clk: samsung: exynos7: Correct CMU_PERIC0 clocks names
This patch renames CMU_PERIC0 clocks names to match with user manual. And also adds missing gate clock for aclk_peric0_66. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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@ -224,6 +224,7 @@ CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
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#define DIV_TOP0_PERIC1 0x0634
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#define DIV_TOP0_PERIC2 0x0638
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#define DIV_TOP0_PERIC3 0x063C
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#define ENABLE_ACLK_TOP03 0x080C
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#define ENABLE_SCLK_TOP0_PERIC0 0x0A30
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#define ENABLE_SCLK_TOP0_PERIC1 0x0A34
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#define ENABLE_SCLK_TOP0_PERIC2 0x0A38
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@ -338,6 +339,9 @@ static struct samsung_div_clock top0_div_clks[] __initdata = {
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};
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static struct samsung_gate_clock top0_gate_clks[] __initdata = {
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GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66",
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ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif",
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ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1",
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@ -590,8 +594,8 @@ CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
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#define ENABLE_SCLK_PERIC0 0x0A00
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/* List of parent clocks for Muxes in CMU_PERIC0 */
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PNAME(mout_aclk_peric0_66_p) = { "fin_pll", "dout_aclk_peric0_66" };
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PNAME(mout_sclk_uart0_p) = { "fin_pll", "sclk_uart0" };
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PNAME(mout_aclk_peric0_66_user_p) = { "fin_pll", "aclk_peric0_66" };
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PNAME(mout_sclk_uart0_user_p) = { "fin_pll", "sclk_uart0" };
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static unsigned long peric0_clk_regs[] __initdata = {
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MUX_SEL_PERIC0,
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@ -600,9 +604,9 @@ static unsigned long peric0_clk_regs[] __initdata = {
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};
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static struct samsung_mux_clock peric0_mux_clks[] __initdata = {
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MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p,
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MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p,
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MUX_SEL_PERIC0, 0, 1),
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MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p,
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MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p,
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MUX_SEL_PERIC0, 16, 1),
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};
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@ -49,7 +49,8 @@
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#define CLK_SCLK_SPDIF 12
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#define CLK_SCLK_PCM1 13
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#define CLK_SCLK_I2S1 14
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#define TOP0_NR_CLK 15
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#define CLK_ACLK_PERIC0_66 15
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#define TOP0_NR_CLK 16
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/* TOP1 */
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#define DOUT_ACLK_FSYS1_200 1
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