sh: CMT clockevent platform driver
SuperH CMT clockevent driver. Both 16-bit and 32-bit CMT versions are supported, but only 32-bit is tested. This driver contains support for both clockevents and clocksources, but no unregistration is supported at this point. Works fine as clock source and/or event in periodic or oneshot mode. Tested on sh7722 and sh7723, but should work with any cpu/architecture. This version is lacking clocksource and early platform driver support for now - this to minimize the amount of dependencies. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
parent
07821d3310
commit
3fb1b6ad06
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@ -397,6 +397,14 @@ source "arch/sh/boards/Kconfig"
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menu "Timer and clock configuration"
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config SH_TIMER_CMT
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def_bool n
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prompt "CMT support"
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select GENERIC_TIME
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select GENERIC_CLOCKEVENTS
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help
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This enables build of the CMT system timer driver.
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config SH_TMU
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def_bool y
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prompt "TMU timer support"
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@ -2,3 +2,4 @@ obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
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obj-$(CONFIG_X86_CYCLONE_TIMER) += cyclone.o
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obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
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obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
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obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o
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615
drivers/clocksource/sh_cmt.c
Normal file
615
drivers/clocksource/sh_cmt.c
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@ -0,0 +1,615 @@
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/*
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* SuperH Timer Support - CMT
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*
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* Copyright (C) 2008 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/irq.h>
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#include <linux/err.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/sh_cmt.h>
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struct sh_cmt_priv {
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void __iomem *mapbase;
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struct clk *clk;
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unsigned long width; /* 16 or 32 bit version of hardware block */
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unsigned long overflow_bit;
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unsigned long clear_bits;
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struct irqaction irqaction;
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struct platform_device *pdev;
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unsigned long flags;
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unsigned long match_value;
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unsigned long next_match_value;
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unsigned long max_match_value;
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unsigned long rate;
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spinlock_t lock;
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struct clock_event_device ced;
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unsigned long total_cycles;
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};
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static DEFINE_SPINLOCK(sh_cmt_lock);
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#define CMSTR -1 /* shared register */
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#define CMCSR 0 /* channel register */
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#define CMCNT 1 /* channel register */
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#define CMCOR 2 /* channel register */
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static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
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{
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struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
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void __iomem *base = p->mapbase;
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unsigned long offs;
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if (reg_nr == CMSTR) {
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offs = 0;
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base -= cfg->channel_offset;
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} else
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offs = reg_nr;
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if (p->width == 16)
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offs <<= 1;
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else {
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offs <<= 2;
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if ((reg_nr == CMCNT) || (reg_nr == CMCOR))
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return ioread32(base + offs);
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}
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return ioread16(base + offs);
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}
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static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr,
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unsigned long value)
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{
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struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
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void __iomem *base = p->mapbase;
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unsigned long offs;
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if (reg_nr == CMSTR) {
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offs = 0;
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base -= cfg->channel_offset;
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} else
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offs = reg_nr;
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if (p->width == 16)
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offs <<= 1;
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else {
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offs <<= 2;
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if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) {
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iowrite32(value, base + offs);
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return;
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}
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}
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iowrite16(value, base + offs);
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}
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static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
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int *has_wrapped)
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{
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unsigned long v1, v2, v3;
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/* Make sure the timer value is stable. Stolen from acpi_pm.c */
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do {
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v1 = sh_cmt_read(p, CMCNT);
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v2 = sh_cmt_read(p, CMCNT);
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v3 = sh_cmt_read(p, CMCNT);
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} while (unlikely((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1)
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|| (v3 > v1 && v3 < v2)));
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*has_wrapped = sh_cmt_read(p, CMCSR) & p->overflow_bit;
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return v2;
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}
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static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
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{
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struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
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unsigned long flags, value;
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/* start stop register shared by multiple timer channels */
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spin_lock_irqsave(&sh_cmt_lock, flags);
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value = sh_cmt_read(p, CMSTR);
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if (start)
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value |= 1 << cfg->timer_bit;
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else
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value &= ~(1 << cfg->timer_bit);
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sh_cmt_write(p, CMSTR, value);
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spin_unlock_irqrestore(&sh_cmt_lock, flags);
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}
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static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
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{
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struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
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int ret;
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/* enable clock */
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ret = clk_enable(p->clk);
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if (ret) {
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pr_err("sh_cmt: cannot enable clock \"%s\"\n", cfg->clk);
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return ret;
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}
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*rate = clk_get_rate(p->clk) / 8;
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/* make sure channel is disabled */
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sh_cmt_start_stop_ch(p, 0);
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/* configure channel, periodic mode and maximum timeout */
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if (p->width == 16)
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sh_cmt_write(p, CMCSR, 0);
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else
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sh_cmt_write(p, CMCSR, 0x01a4);
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sh_cmt_write(p, CMCOR, 0xffffffff);
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sh_cmt_write(p, CMCNT, 0);
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/* enable channel */
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sh_cmt_start_stop_ch(p, 1);
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return 0;
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}
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static void sh_cmt_disable(struct sh_cmt_priv *p)
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{
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/* disable channel */
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sh_cmt_start_stop_ch(p, 0);
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/* stop clock */
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clk_disable(p->clk);
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}
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/* private flags */
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#define FLAG_CLOCKEVENT (1 << 0)
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#define FLAG_CLOCKSOURCE (1 << 1)
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#define FLAG_REPROGRAM (1 << 2)
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#define FLAG_SKIPEVENT (1 << 3)
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#define FLAG_IRQCONTEXT (1 << 4)
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static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p,
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int absolute)
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{
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unsigned long new_match;
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unsigned long value = p->next_match_value;
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unsigned long delay = 0;
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unsigned long now = 0;
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int has_wrapped;
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now = sh_cmt_get_counter(p, &has_wrapped);
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p->flags |= FLAG_REPROGRAM; /* force reprogram */
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if (has_wrapped) {
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/* we're competing with the interrupt handler.
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* -> let the interrupt handler reprogram the timer.
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* -> interrupt number two handles the event.
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*/
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p->flags |= FLAG_SKIPEVENT;
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return;
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}
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if (absolute)
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now = 0;
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do {
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/* reprogram the timer hardware,
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* but don't save the new match value yet.
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*/
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new_match = now + value + delay;
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if (new_match > p->max_match_value)
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new_match = p->max_match_value;
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sh_cmt_write(p, CMCOR, new_match);
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now = sh_cmt_get_counter(p, &has_wrapped);
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if (has_wrapped && (new_match > p->match_value)) {
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/* we are changing to a greater match value,
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* so this wrap must be caused by the counter
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* matching the old value.
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* -> first interrupt reprograms the timer.
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* -> interrupt number two handles the event.
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*/
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p->flags |= FLAG_SKIPEVENT;
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break;
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}
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if (has_wrapped) {
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/* we are changing to a smaller match value,
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* so the wrap must be caused by the counter
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* matching the new value.
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* -> save programmed match value.
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* -> let isr handle the event.
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*/
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p->match_value = new_match;
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break;
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}
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/* be safe: verify hardware settings */
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if (now < new_match) {
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/* timer value is below match value, all good.
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* this makes sure we won't miss any match events.
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* -> save programmed match value.
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* -> let isr handle the event.
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*/
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p->match_value = new_match;
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break;
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}
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/* the counter has reached a value greater
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* than our new match value. and since the
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* has_wrapped flag isn't set we must have
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* programmed a too close event.
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* -> increase delay and retry.
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*/
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if (delay)
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delay <<= 1;
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else
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delay = 1;
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if (!delay)
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pr_warning("sh_cmt: too long delay\n");
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} while (delay);
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}
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static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
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{
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unsigned long flags;
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if (delta > p->max_match_value)
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pr_warning("sh_cmt: delta out of range\n");
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spin_lock_irqsave(&p->lock, flags);
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p->next_match_value = delta;
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sh_cmt_clock_event_program_verify(p, 0);
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spin_unlock_irqrestore(&p->lock, flags);
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}
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static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
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{
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struct sh_cmt_priv *p = dev_id;
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/* clear flags */
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sh_cmt_write(p, CMCSR, sh_cmt_read(p, CMCSR) & p->clear_bits);
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/* update clock source counter to begin with if enabled
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* the wrap flag should be cleared by the timer specific
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* isr before we end up here.
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*/
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if (p->flags & FLAG_CLOCKSOURCE)
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p->total_cycles += p->match_value;
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if (!(p->flags & FLAG_REPROGRAM))
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p->next_match_value = p->max_match_value;
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p->flags |= FLAG_IRQCONTEXT;
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if (p->flags & FLAG_CLOCKEVENT) {
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if (!(p->flags & FLAG_SKIPEVENT)) {
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if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) {
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p->next_match_value = p->max_match_value;
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p->flags |= FLAG_REPROGRAM;
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}
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p->ced.event_handler(&p->ced);
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}
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}
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p->flags &= ~FLAG_SKIPEVENT;
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if (p->flags & FLAG_REPROGRAM) {
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p->flags &= ~FLAG_REPROGRAM;
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sh_cmt_clock_event_program_verify(p, 1);
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if (p->flags & FLAG_CLOCKEVENT)
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if ((p->ced.mode == CLOCK_EVT_MODE_SHUTDOWN)
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|| (p->match_value == p->next_match_value))
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p->flags &= ~FLAG_REPROGRAM;
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}
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p->flags &= ~FLAG_IRQCONTEXT;
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return IRQ_HANDLED;
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}
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static int sh_cmt_start(struct sh_cmt_priv *p, unsigned long flag)
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{
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int ret = 0;
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unsigned long flags;
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spin_lock_irqsave(&p->lock, flags);
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if (!(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
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ret = sh_cmt_enable(p, &p->rate);
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if (ret)
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goto out;
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p->flags |= flag;
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/* setup timeout if no clockevent */
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if ((flag == FLAG_CLOCKSOURCE) && (!(p->flags & FLAG_CLOCKEVENT)))
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sh_cmt_set_next(p, p->max_match_value);
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out:
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spin_unlock_irqrestore(&p->lock, flags);
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return ret;
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}
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static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag)
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{
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unsigned long flags;
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unsigned long f;
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spin_lock_irqsave(&p->lock, flags);
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f = p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
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p->flags &= ~flag;
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if (f && !(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
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sh_cmt_disable(p);
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/* adjust the timeout to maximum if only clocksource left */
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if ((flag == FLAG_CLOCKEVENT) && (p->flags & FLAG_CLOCKSOURCE))
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sh_cmt_set_next(p, p->max_match_value);
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spin_unlock_irqrestore(&p->lock, flags);
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}
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static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced)
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{
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return container_of(ced, struct sh_cmt_priv, ced);
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}
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static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic)
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{
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struct clock_event_device *ced = &p->ced;
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sh_cmt_start(p, FLAG_CLOCKEVENT);
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/* TODO: calculate good shift from rate and counter bit width */
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ced->shift = 32;
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ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
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ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced);
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ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
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if (periodic)
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sh_cmt_set_next(p, (p->rate + HZ/2) / HZ);
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else
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sh_cmt_set_next(p, p->max_match_value);
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}
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static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
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struct clock_event_device *ced)
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{
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struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
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/* deal with old setting first */
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switch (ced->mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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case CLOCK_EVT_MODE_ONESHOT:
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sh_cmt_stop(p, FLAG_CLOCKEVENT);
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break;
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default:
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break;
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}
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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pr_info("sh_cmt: %s used for periodic clock events\n",
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ced->name);
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sh_cmt_clock_event_start(p, 1);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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pr_info("sh_cmt: %s used for oneshot clock events\n",
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ced->name);
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sh_cmt_clock_event_start(p, 0);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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sh_cmt_stop(p, FLAG_CLOCKEVENT);
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break;
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default:
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break;
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}
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}
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static int sh_cmt_clock_event_next(unsigned long delta,
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struct clock_event_device *ced)
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{
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struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
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BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
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if (likely(p->flags & FLAG_IRQCONTEXT))
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p->next_match_value = delta;
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else
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sh_cmt_set_next(p, delta);
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return 0;
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}
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static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
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char *name, unsigned long rating)
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{
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struct clock_event_device *ced = &p->ced;
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memset(ced, 0, sizeof(*ced));
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ced->name = name;
|
||||
ced->features = CLOCK_EVT_FEAT_PERIODIC;
|
||||
ced->features |= CLOCK_EVT_FEAT_ONESHOT;
|
||||
ced->rating = rating;
|
||||
ced->cpumask = cpumask_of(0);
|
||||
ced->set_next_event = sh_cmt_clock_event_next;
|
||||
ced->set_mode = sh_cmt_clock_event_mode;
|
||||
|
||||
pr_info("sh_cmt: %s used for clock events\n", ced->name);
|
||||
ced->mult = 1; /* work around misplaced WARN_ON() in clockevents.c */
|
||||
clockevents_register_device(ced);
|
||||
}
|
||||
|
||||
int sh_cmt_register(struct sh_cmt_priv *p, char *name,
|
||||
unsigned long clockevent_rating,
|
||||
unsigned long clocksource_rating)
|
||||
{
|
||||
if (p->width == (sizeof(p->max_match_value) * 8))
|
||||
p->max_match_value = ~0;
|
||||
else
|
||||
p->max_match_value = (1 << p->width) - 1;
|
||||
|
||||
p->match_value = p->max_match_value;
|
||||
spin_lock_init(&p->lock);
|
||||
|
||||
if (clockevent_rating)
|
||||
sh_cmt_register_clockevent(p, name, clockevent_rating);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
|
||||
{
|
||||
struct sh_cmt_config *cfg = pdev->dev.platform_data;
|
||||
struct resource *res;
|
||||
int irq, ret;
|
||||
ret = -ENXIO;
|
||||
|
||||
memset(p, 0, sizeof(*p));
|
||||
p->pdev = pdev;
|
||||
|
||||
if (!cfg) {
|
||||
dev_err(&p->pdev->dev, "missing platform data\n");
|
||||
goto err0;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, p);
|
||||
|
||||
res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(&p->pdev->dev, "failed to get I/O memory\n");
|
||||
goto err0;
|
||||
}
|
||||
|
||||
irq = platform_get_irq(p->pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(&p->pdev->dev, "failed to get irq\n");
|
||||
goto err0;
|
||||
}
|
||||
|
||||
/* map memory, let mapbase point to our channel */
|
||||
p->mapbase = ioremap_nocache(res->start, resource_size(res));
|
||||
if (p->mapbase == NULL) {
|
||||
pr_err("sh_cmt: failed to remap I/O memory\n");
|
||||
goto err0;
|
||||
}
|
||||
|
||||
/* request irq using setup_irq() (too early for request_irq()) */
|
||||
p->irqaction.name = cfg->name;
|
||||
p->irqaction.handler = sh_cmt_interrupt;
|
||||
p->irqaction.dev_id = p;
|
||||
p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
|
||||
p->irqaction.mask = CPU_MASK_NONE;
|
||||
ret = setup_irq(irq, &p->irqaction);
|
||||
if (ret) {
|
||||
pr_err("sh_cmt: failed to request irq %d\n", irq);
|
||||
goto err1;
|
||||
}
|
||||
|
||||
/* get hold of clock */
|
||||
p->clk = clk_get(&p->pdev->dev, cfg->clk);
|
||||
if (IS_ERR(p->clk)) {
|
||||
pr_err("sh_cmt: cannot get clock \"%s\"\n", cfg->clk);
|
||||
ret = PTR_ERR(p->clk);
|
||||
goto err2;
|
||||
}
|
||||
|
||||
if (resource_size(res) == 6) {
|
||||
p->width = 16;
|
||||
p->overflow_bit = 0x80;
|
||||
p->clear_bits = ~0xc0;
|
||||
} else {
|
||||
p->width = 32;
|
||||
p->overflow_bit = 0x8000;
|
||||
p->clear_bits = ~0xc000;
|
||||
}
|
||||
|
||||
return sh_cmt_register(p, cfg->name,
|
||||
cfg->clockevent_rating,
|
||||
cfg->clocksource_rating);
|
||||
err2:
|
||||
free_irq(irq, p);
|
||||
err1:
|
||||
iounmap(p->mapbase);
|
||||
err0:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __devinit sh_cmt_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct sh_cmt_priv *p = platform_get_drvdata(pdev);
|
||||
int ret;
|
||||
|
||||
p = kmalloc(sizeof(*p), GFP_KERNEL);
|
||||
if (p == NULL) {
|
||||
dev_err(&pdev->dev, "failed to allocate driver data\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ret = sh_cmt_setup(p, pdev);
|
||||
if (ret) {
|
||||
kfree(p);
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __devexit sh_cmt_remove(struct platform_device *pdev)
|
||||
{
|
||||
return -EBUSY; /* cannot unregister clockevent and clocksource */
|
||||
}
|
||||
|
||||
static struct platform_driver sh_cmt_device_driver = {
|
||||
.probe = sh_cmt_probe,
|
||||
.remove = __devexit_p(sh_cmt_remove),
|
||||
.driver = {
|
||||
.name = "sh_cmt",
|
||||
}
|
||||
};
|
||||
|
||||
static int __init sh_cmt_init(void)
|
||||
{
|
||||
return platform_driver_register(&sh_cmt_device_driver);
|
||||
}
|
||||
|
||||
static void __exit sh_cmt_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&sh_cmt_device_driver);
|
||||
}
|
||||
|
||||
module_init(sh_cmt_init);
|
||||
module_exit(sh_cmt_exit);
|
||||
|
||||
MODULE_AUTHOR("Magnus Damm");
|
||||
MODULE_DESCRIPTION("SuperH CMT Timer Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
13
include/linux/sh_cmt.h
Normal file
13
include/linux/sh_cmt.h
Normal file
|
@ -0,0 +1,13 @@
|
|||
#ifndef __SH_CMT_H__
|
||||
#define __SH_CMT_H__
|
||||
|
||||
struct sh_cmt_config {
|
||||
char *name;
|
||||
unsigned long channel_offset;
|
||||
int timer_bit;
|
||||
char *clk;
|
||||
unsigned long clockevent_rating;
|
||||
unsigned long clocksource_rating;
|
||||
};
|
||||
|
||||
#endif /* __SH_CMT_H__ */
|
Loading…
Reference in a new issue