Merge tag 'qcom-dt-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into for-next
Merge "Qualcomm ARM Based Device Tree Updates for v3.16" from Kumar Gala: * Added device tree nodes for pinctrl and SDHC for msm8974 SoC/DB8074 board * Added binding spec for GSBI configuration node * tag 'qcom-dt-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom: soc: qcom: Add device tree binding for GSBI ARM: dts: msm: Add SDHC controller nodes for MSM8974 and DB8074 board ARM: dts: MSM8974: Add pinctrl node Signed-off-by: Arnd Bergmann <arnd@arndb.de>wifi-calibration
Arnd Bergmann
commit
4078679ecf
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QCOM GSBI (General Serial Bus Interface) Driver
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The GSBI controller is modeled as a node with zero or more child nodes, each
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representing a serial sub-node device that is mux'd as part of the GSBI
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configuration settings. The mode setting will govern the input/output mode of
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the 4 GSBI IOs.
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Required properties:
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- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064
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- reg: Address range for GSBI registers
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- clocks: required clock
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- clock-names: must contain "iface" entry
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- qcom,mode : indicates MUX value for configuration of the serial interface.
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Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values.
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Optional properties:
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- qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
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dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
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Required properties if child node exists:
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- #address-cells: Must be 1
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- #size-cells: Must be 1
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- ranges: Must be present
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Properties for children:
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A GSBI controller node can contain 0 or more child nodes representing serial
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devices. These serial devices can be a QCOM UART, I2C controller, spi
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controller, or some combination of aforementioned devices.
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See the following for child node definitions:
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Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt
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Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
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Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
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Example for APQ8064:
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#include <dt-bindings/soc/qcom,gsbi.h>
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gsbi4@16300000 {
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compatible = "qcom,gsbi-v1.0.0";
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reg = <0x16300000 0x100>;
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clocks = <&gcc GSBI4_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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qcom,mode = <GSBI_PROT_I2C_UART>;
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qcom,crci = <GSBI_CRCI_QUP>;
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/* child nodes go under here */
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i2c_qup4: i2c@16380000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x16380000 0x1000>;
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interrupts = <0 153 0>;
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clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <200000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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uart4: serial@16340000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16340000 0x1000>,
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<0x16300000 0x1000>;
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interrupts = <0 152 0x0>;
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clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
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clock-names = "core", "iface";
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status = "ok";
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};
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};
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@ -3,4 +3,17 @@
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/ {
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model = "Qualcomm APQ8074 Dragonboard";
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compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";
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soc: soc {
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sdhci@f9824900 {
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bus-width = <8>;
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non-removable;
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status = "ok";
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};
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sdhci@f98a4900 {
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cd-gpios = <&msmgpio 62 0x1>;
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bus-width = <4>;
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};
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};
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};
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@ -192,11 +192,62 @@
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clock-names = "core", "iface";
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};
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sdhci@f9824900 {
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compatible = "qcom,sdhci-msm-v4";
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reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
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reg-names = "hc_mem", "core_mem";
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interrupts = <0 123 0>, <0 138 0>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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sdhci@f98a4900 {
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compatible = "qcom,sdhci-msm-v4";
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reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
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reg-names = "hc_mem", "core_mem";
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interrupts = <0 125 0>, <0 221 0>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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rng@f9bff000 {
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compatible = "qcom,prng";
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reg = <0xf9bff000 0x200>;
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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clock-names = "core";
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};
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msmgpio: pinctrl@fd510000 {
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compatible = "qcom,msm8974-pinctrl";
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reg = <0xfd510000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 208 0>;
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spi8_default: spi8_default {
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mosi {
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pins = "gpio45";
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function = "blsp_spi8";
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};
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miso {
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pins = "gpio46";
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function = "blsp_spi8";
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};
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cs {
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pins = "gpio47";
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function = "blsp_spi8";
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};
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clk {
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pins = "gpio48";
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function = "blsp_spi8";
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};
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};
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};
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};
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};
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@ -0,0 +1,26 @@
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/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DT_BINDINGS_QCOM_GSBI_H
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#define __DT_BINDINGS_QCOM_GSBI_H
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#define GSBI_PROT_IDLE 0
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#define GSBI_PROT_I2C_UIM 1
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#define GSBI_PROT_I2C 2
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#define GSBI_PROT_SPI 3
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#define GSBI_PROT_UART_W_FC 4
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#define GSBI_PROT_UIM 5
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#define GSBI_PROT_I2C_UART 6
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#define GSBI_CRCI_QUP 0
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#define GSBI_CRCI_UART 1
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#endif
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