Pull sn2-mmio-writes into release branch
Hand-fixed conflicts: include/asm-ia64/machvec_sn2.h Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Tony Luck
commit
409761bb6a
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@ -3,7 +3,7 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
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* Copyright (C) 1999,2001-2006 Silicon Graphics, Inc. All rights reserved.
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*/
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#include <linux/config.h>
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@ -498,6 +498,7 @@ void __init sn_setup(char **cmdline_p)
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* for sn.
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*/
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pm_power_off = ia64_sn_power_down;
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current->thread.flags |= IA64_THREAD_MIGRATION;
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}
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/**
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@ -660,7 +661,8 @@ void __init sn_cpu_init(void)
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SH2_PIO_WRITE_STATUS_1, SH2_PIO_WRITE_STATUS_3};
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u64 *pio;
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pio = is_shub1() ? pio1 : pio2;
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pda->pio_write_status_addr = (volatile unsigned long *) LOCAL_MMR_ADDR(pio[slice]);
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pda->pio_write_status_addr =
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(volatile unsigned long *)GLOBAL_MMR_ADDR(nasid, pio[slice]);
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pda->pio_write_status_val = is_shub1() ? SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK : 0;
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}
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@ -93,6 +93,27 @@ static inline unsigned long wait_piowc(void)
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return (ws & SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK) != 0;
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}
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/**
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* sn_migrate - SN-specific task migration actions
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* @task: Task being migrated to new CPU
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*
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* SN2 PIO writes from separate CPUs are not guaranteed to arrive in order.
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* Context switching user threads which have memory-mapped MMIO may cause
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* PIOs to issue from seperate CPUs, thus the PIO writes must be drained
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* from the previous CPU's Shub before execution resumes on the new CPU.
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*/
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void sn_migrate(struct task_struct *task)
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{
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pda_t *last_pda = pdacpu(task_thread_info(task)->last_cpu);
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volatile unsigned long *adr = last_pda->pio_write_status_addr;
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unsigned long val = last_pda->pio_write_status_val;
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/* Drain PIO writes from old CPU's Shub */
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while (unlikely((*adr & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK)
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!= val))
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cpu_relax();
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}
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void sn_tlb_migrate_finish(struct mm_struct *mm)
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{
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/* flush_tlb_mm is inefficient if more than 1 users of mm */
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@ -20,6 +20,7 @@ struct scatterlist;
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struct page;
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struct mm_struct;
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struct pci_bus;
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struct task_struct;
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typedef void ia64_mv_setup_t (char **);
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typedef void ia64_mv_cpu_init_t (void);
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@ -34,6 +35,7 @@ typedef int ia64_mv_pci_legacy_read_t (struct pci_bus *, u16 port, u32 *val,
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u8 size);
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typedef int ia64_mv_pci_legacy_write_t (struct pci_bus *, u16 port, u32 val,
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u8 size);
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typedef void ia64_mv_migrate_t(struct task_struct * task);
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/* DMA-mapping interface: */
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typedef void ia64_mv_dma_init (void);
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@ -85,6 +87,11 @@ machvec_noop_mm (struct mm_struct *mm)
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{
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}
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static inline void
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machvec_noop_task (struct task_struct *task)
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{
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}
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extern void machvec_setup (char **);
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extern void machvec_timer_interrupt (int, void *, struct pt_regs *);
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extern void machvec_dma_sync_single (struct device *, dma_addr_t, size_t, int);
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@ -146,6 +153,7 @@ extern void machvec_tlb_migrate_finish (struct mm_struct *);
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# define platform_readw_relaxed ia64_mv.readw_relaxed
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# define platform_readl_relaxed ia64_mv.readl_relaxed
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# define platform_readq_relaxed ia64_mv.readq_relaxed
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# define platform_migrate ia64_mv.migrate
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# endif
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/* __attribute__((__aligned__(16))) is required to make size of the
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@ -194,6 +202,7 @@ struct ia64_machine_vector {
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ia64_mv_readw_relaxed_t *readw_relaxed;
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ia64_mv_readl_relaxed_t *readl_relaxed;
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ia64_mv_readq_relaxed_t *readq_relaxed;
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ia64_mv_migrate_t *migrate;
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} __attribute__((__aligned__(16))); /* align attrib? see above comment */
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#define MACHVEC_INIT(name) \
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@ -238,6 +247,7 @@ struct ia64_machine_vector {
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platform_readw_relaxed, \
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platform_readl_relaxed, \
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platform_readq_relaxed, \
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platform_migrate, \
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}
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extern struct ia64_machine_vector ia64_mv;
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@ -386,5 +396,8 @@ extern ia64_mv_dma_supported swiotlb_dma_supported;
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#ifndef platform_readq_relaxed
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# define platform_readq_relaxed __ia64_readq_relaxed
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#endif
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#ifndef platform_migrate
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# define platform_migrate machvec_noop_task
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#endif
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#endif /* _ASM_IA64_MACHVEC_H */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2002-2003, 2006 Silicon Graphics, Inc. All Rights Reserved.
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* Copyright (c) 2002-2003,2006 Silicon Graphics, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License
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@ -66,6 +66,7 @@ extern ia64_mv_dma_sync_single_for_device sn_dma_sync_single_for_device;
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extern ia64_mv_dma_sync_sg_for_device sn_dma_sync_sg_for_device;
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extern ia64_mv_dma_mapping_error sn_dma_mapping_error;
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extern ia64_mv_dma_supported sn_dma_supported;
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extern ia64_mv_migrate_t sn_migrate;
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/*
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* This stuff has dual use!
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@ -115,6 +116,7 @@ extern ia64_mv_dma_supported sn_dma_supported;
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#define platform_dma_sync_sg_for_device sn_dma_sync_sg_for_device
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#define platform_dma_mapping_error sn_dma_mapping_error
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#define platform_dma_supported sn_dma_supported
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#define platform_migrate sn_migrate
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#include <asm/sn/io.h>
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@ -50,7 +50,8 @@
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#define IA64_THREAD_PM_VALID (__IA64_UL(1) << 2) /* performance registers valid? */
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#define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3) /* don't log unaligned accesses */
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#define IA64_THREAD_UAC_SIGBUS (__IA64_UL(1) << 4) /* generate SIGBUS on unaligned acc. */
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/* bit 5 is currently unused */
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#define IA64_THREAD_MIGRATION (__IA64_UL(1) << 5) /* require migration
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sync at ctx sw */
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#define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6) /* don't log any fpswa faults */
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#define IA64_THREAD_FPEMU_SIGFPE (__IA64_UL(1) << 7) /* send a SIGFPE for fpswa faults */
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@ -244,6 +244,13 @@ extern void ia64_load_extra (struct task_struct *task);
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__ia64_save_fpu((prev)->thread.fph); \
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} \
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__switch_to(prev, next, last); \
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/* "next" in old context is "current" in new context */ \
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if (unlikely((current->thread.flags & IA64_THREAD_MIGRATION) && \
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(task_cpu(current) != \
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task_thread_info(current)->last_cpu))) { \
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platform_migrate(current); \
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task_thread_info(current)->last_cpu = task_cpu(current); \
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} \
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} while (0)
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#else
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# define switch_to(prev,next,last) __switch_to(prev, next, last)
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@ -26,6 +26,7 @@ struct thread_info {
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struct exec_domain *exec_domain;/* execution domain */
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__u32 flags; /* thread_info flags (see TIF_*) */
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__u32 cpu; /* current CPU */
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__u32 last_cpu; /* Last CPU thread ran on */
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mm_segment_t addr_limit; /* user-level address space limit */
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int preempt_count; /* 0=premptable, <0=BUG; will also serve as bh-counter */
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struct restart_block restart_block;
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