ehci-fsl: fix cache coherency problem on system with large memory
The patch fixes bug http://bugzilla.kernel.org/show_bug.cgi?id=7482. It sets USB snooping on 4G space for PowerPC platforms without CONFIG_NOT_COHERENT_CACHE defined. Reported-by: Stefan Meyer <reyems@telkomsa.net> Signed-off-by: Li Yang <leoli@freescale.com> Cc: Greg KH <greg@kroah.com> Cc: David Brownell <david-b@pacbell.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -193,6 +193,19 @@ static void mpc83xx_usb_setup(struct usb_hcd *hcd)
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out_be32(non_ehci + FSL_SOC_USB_CTRL, 0x00000004);
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out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0000001b);
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#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
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/*
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* Turn on cache snooping hardware, since some PowerPC platforms
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* wholly rely on hardware to deal with cache coherent
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*/
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/* Setup Snooping for all the 4GB space */
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/* SNOOP1 starts from 0x0, size 2G */
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out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0 | SNOOP_SIZE_2GB);
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/* SNOOP2 starts from 0x80000000, size 2G */
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out_be32(non_ehci + FSL_SOC_USB_SNOOP2, 0x80000000 | SNOOP_SIZE_2GB);
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#endif
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if (pdata->operating_mode == FSL_USB2_DR_HOST)
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mpc83xx_setup_phy(ehci, pdata->phy_mode, 0);
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@ -34,4 +34,5 @@
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#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
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#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
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#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
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#define SNOOP_SIZE_2GB 0x1e
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#endif /* _EHCI_FSL_H */
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