Merge branch 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: drm/i915: Add new GET_PIPE_FROM_CRTC_ID ioctl. drm/i915: Set HDMI hot plug interrupt enable for only the output in question. drm/i915: Include 965GME pci ID in IS_I965GM(dev) to match UMS. drm/i915: Use the GM45 VGA hotplug workaround on G45 as well. drm/i915: ignore LVDS on intel graphics systems that lie about having it drm/i915: sanity check IER at wait_request time drm/i915: workaround IGD i2c bus issue in kernel side (v2) drm/i915: Don't allow binding objects into the last page of the aperture. drm/i915: save/restore fence registers across suspend/resume drm/i915: x86 always has writeq. Add I915_READ64 for symmetry.
This commit is contained in:
commit
40f293ff83
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@ -1011,8 +1011,16 @@ static int i915_load_modeset_init(struct drm_device *dev)
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/* Basic memrange allocator for stolen space (aka vram) */
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drm_mm_init(&dev_priv->vram, 0, prealloc_size);
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/* Let GEM Manage from end of prealloc space to end of aperture */
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i915_gem_do_init(dev, prealloc_size, agp_size);
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/* Let GEM Manage from end of prealloc space to end of aperture.
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*
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* However, leave one page at the end still bound to the scratch page.
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* There are a number of places where the hardware apparently
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* prefetches past the end of the object, and we've seen multiple
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* hangs with the GPU head pointer stuck in a batchbuffer bound
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* at the last page of the aperture. One page should be enough to
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* keep any prefetching inside of the aperture.
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*/
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i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
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ret = i915_gem_init_ringbuffer(dev);
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if (ret)
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@ -1350,6 +1358,7 @@ struct drm_ioctl_desc i915_ioctls[] = {
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DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
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DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
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DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),
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DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
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};
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int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
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@ -283,6 +283,7 @@ typedef struct drm_i915_private {
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u8 saveAR[21];
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u8 saveDACMASK;
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u8 saveCR[37];
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uint64_t saveFENCE[16];
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struct {
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struct drm_mm gtt_space;
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@ -705,13 +706,8 @@ extern void intel_modeset_cleanup(struct drm_device *dev);
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#define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
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#define I915_READ8(reg) readb(dev_priv->regs + (reg))
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#define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
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#ifdef writeq
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#define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
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#else
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#define I915_WRITE64(reg, val) (writel(val, dev_priv->regs + (reg)), \
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writel(upper_32_bits(val), dev_priv->regs + \
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(reg) + 4))
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#endif
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#define I915_READ64(reg) readq(dev_priv->regs + (reg))
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#define POSTING_READ(reg) (void)I915_READ(reg)
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#define I915_VERBOSE 0
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@ -790,7 +786,8 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
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(dev)->pci_device == 0x2E22 || \
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(dev)->pci_device == 0x2E32)
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#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
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#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
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(dev)->pci_device == 0x2A12)
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#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
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@ -1691,11 +1691,20 @@ static int
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i915_wait_request(struct drm_device *dev, uint32_t seqno)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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u32 ier;
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int ret = 0;
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BUG_ON(seqno == 0);
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if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
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ier = I915_READ(IER);
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if (!ier) {
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DRM_ERROR("something (likely vbetool) disabled "
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"interrupts, re-enabling\n");
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i915_driver_irq_preinstall(dev);
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i915_driver_irq_postinstall(dev);
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}
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dev_priv->mm.waiting_gem_seqno = seqno;
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i915_user_irq_get(dev);
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ret = wait_event_interruptible(dev_priv->irq_queue,
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@ -526,6 +526,7 @@
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#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
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#define D_STATE 0x6104
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#define CG_2D_DIS 0x6200
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#define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24)
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#define CG_3D_DIS 0x6204
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/*
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@ -349,6 +349,18 @@ int i915_save_state(struct drm_device *dev)
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for (i = 0; i < 3; i++)
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dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
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/* Fences */
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if (IS_I965G(dev)) {
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for (i = 0; i < 16; i++)
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dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
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} else {
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for (i = 0; i < 8; i++)
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dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
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if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
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for (i = 0; i < 8; i++)
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dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
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}
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i915_save_vga(dev);
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return 0;
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@ -371,6 +383,18 @@ int i915_restore_state(struct drm_device *dev)
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/* Display arbitration */
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I915_WRITE(DSPARB, dev_priv->saveDSPARB);
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/* Fences */
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if (IS_I965G(dev)) {
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for (i = 0; i < 16; i++)
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I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
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} else {
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for (i = 0; i < 8; i++)
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I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
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if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
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for (i = 0; i < 8; i++)
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I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
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}
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/* Pipe & plane A info */
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/* Prime the clock */
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if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
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@ -161,7 +161,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
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hotplug_en &= CRT_FORCE_HOTPLUG_MASK;
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hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
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if (IS_GM45(dev))
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if (IS_G4X(dev))
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hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
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hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
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@ -1804,6 +1804,37 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
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}
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}
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int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
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struct drm_crtc *crtc = NULL;
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int pipe = -1;
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if (!dev_priv) {
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DRM_ERROR("called with no initialization\n");
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return -EINVAL;
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}
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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if (crtc->base.id == pipe_from_crtc_id->crtc_id) {
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pipe = intel_crtc->pipe;
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break;
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}
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}
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if (pipe == -1) {
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DRM_ERROR("no such CRTC id\n");
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return -EINVAL;
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}
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pipe_from_crtc_id->pipe = pipe;
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return 0;
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}
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struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
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{
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struct drm_crtc *crtc = NULL;
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@ -109,7 +109,7 @@ struct intel_i2c_chan *intel_i2c_create(struct drm_device *dev, const u32 reg,
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void intel_i2c_destroy(struct intel_i2c_chan *chan);
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int intel_ddc_get_modes(struct intel_output *intel_output);
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extern bool intel_ddc_probe(struct intel_output *intel_output);
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void intel_i2c_quirk_set(struct drm_device *dev, bool enable);
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extern void intel_crt_init(struct drm_device *dev);
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extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg);
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extern bool intel_sdvo_init(struct drm_device *dev, int output_device);
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@ -125,6 +125,8 @@ extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
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extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
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struct drm_crtc *crtc);
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int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern void intel_wait_for_vblank(struct drm_device *dev);
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extern struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe);
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extern struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
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@ -155,11 +155,18 @@ intel_hdmi_detect(struct drm_connector *connector)
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temp = I915_READ(PORT_HOTPLUG_EN);
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I915_WRITE(PORT_HOTPLUG_EN,
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temp |
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HDMIB_HOTPLUG_INT_EN |
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HDMIC_HOTPLUG_INT_EN |
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HDMID_HOTPLUG_INT_EN);
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switch (hdmi_priv->sdvox_reg) {
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case SDVOB:
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temp |= HDMIB_HOTPLUG_INT_EN;
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break;
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case SDVOC:
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temp |= HDMIC_HOTPLUG_INT_EN;
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break;
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default:
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return connector_status_unknown;
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}
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I915_WRITE(PORT_HOTPLUG_EN, temp);
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POSTING_READ(PORT_HOTPLUG_EN);
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@ -34,6 +34,21 @@
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#include "i915_drm.h"
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#include "i915_drv.h"
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void intel_i2c_quirk_set(struct drm_device *dev, bool enable)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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/* When using bit bashing for I2C, this bit needs to be set to 1 */
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if (!IS_IGD(dev))
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return;
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if (enable)
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I915_WRITE(CG_2D_DIS,
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I915_READ(CG_2D_DIS) | DPCUNIT_CLOCK_GATE_DISABLE);
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else
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I915_WRITE(CG_2D_DIS,
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I915_READ(CG_2D_DIS) & (~DPCUNIT_CLOCK_GATE_DISABLE));
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}
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/*
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* Intel GPIO access functions
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*/
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@ -153,8 +168,10 @@ struct intel_i2c_chan *intel_i2c_create(struct drm_device *dev, const u32 reg,
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goto out_free;
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/* JJJ: raise SCL and SDA? */
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intel_i2c_quirk_set(dev, true);
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set_data(chan, 1);
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set_clock(chan, 1);
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intel_i2c_quirk_set(dev, false);
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udelay(20);
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return chan;
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@ -384,7 +384,51 @@ static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
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.destroy = intel_lvds_enc_destroy,
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};
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static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
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{
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DRM_DEBUG("Skipping LVDS initialization for %s\n", id->ident);
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return 1;
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}
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/* These systems claim to have LVDS, but really don't */
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static const struct dmi_system_id __initdata intel_no_lvds[] = {
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{
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.callback = intel_no_lvds_dmi_callback,
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.ident = "Apple Mac Mini (Core series)",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
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DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
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},
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},
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{
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.callback = intel_no_lvds_dmi_callback,
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.ident = "Apple Mac Mini (Core 2 series)",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
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DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
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},
|
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},
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{
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.callback = intel_no_lvds_dmi_callback,
|
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.ident = "MSI IM-945GSE-A",
|
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.matches = {
|
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DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
|
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DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
|
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},
|
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},
|
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{
|
||||
.callback = intel_no_lvds_dmi_callback,
|
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.ident = "Dell Studio Hybrid",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
|
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DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
|
||||
},
|
||||
},
|
||||
|
||||
/* FIXME: add a check for the Aopen Mini PC */
|
||||
|
||||
{ } /* terminating entry */
|
||||
};
|
||||
|
||||
/**
|
||||
* intel_lvds_init - setup LVDS connectors on this device
|
||||
|
@ -404,15 +448,9 @@ void intel_lvds_init(struct drm_device *dev)
|
|||
u32 lvds;
|
||||
int pipe;
|
||||
|
||||
/* Blacklist machines that we know falsely report LVDS. */
|
||||
/* FIXME: add a check for the Aopen Mini PC */
|
||||
|
||||
/* Apple Mac Mini Core Duo and Mac Mini Core 2 Duo */
|
||||
if(dmi_match(DMI_PRODUCT_NAME, "Macmini1,1") ||
|
||||
dmi_match(DMI_PRODUCT_NAME, "Macmini2,1")) {
|
||||
DRM_DEBUG("Skipping LVDS initialization for Apple Mac Mini\n");
|
||||
/* Skip init on machines we know falsely report LVDS */
|
||||
if (dmi_check_system(intel_no_lvds))
|
||||
return;
|
||||
}
|
||||
|
||||
intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL);
|
||||
if (!intel_output) {
|
||||
|
|
|
@ -27,6 +27,7 @@
|
|||
#include <linux/fb.h>
|
||||
#include "drmP.h"
|
||||
#include "intel_drv.h"
|
||||
#include "i915_drv.h"
|
||||
|
||||
/**
|
||||
* intel_ddc_probe
|
||||
|
@ -52,7 +53,10 @@ bool intel_ddc_probe(struct intel_output *intel_output)
|
|||
}
|
||||
};
|
||||
|
||||
intel_i2c_quirk_set(intel_output->ddc_bus->drm_dev, true);
|
||||
ret = i2c_transfer(&intel_output->ddc_bus->adapter, msgs, 2);
|
||||
intel_i2c_quirk_set(intel_output->ddc_bus->drm_dev, false);
|
||||
|
||||
if (ret == 2)
|
||||
return true;
|
||||
|
||||
|
@ -70,8 +74,10 @@ int intel_ddc_get_modes(struct intel_output *intel_output)
|
|||
struct edid *edid;
|
||||
int ret = 0;
|
||||
|
||||
intel_i2c_quirk_set(intel_output->ddc_bus->drm_dev, true);
|
||||
edid = drm_get_edid(&intel_output->base,
|
||||
&intel_output->ddc_bus->adapter);
|
||||
intel_i2c_quirk_set(intel_output->ddc_bus->drm_dev, false);
|
||||
if (edid) {
|
||||
drm_mode_connector_update_edid_property(&intel_output->base,
|
||||
edid);
|
||||
|
|
|
@ -184,6 +184,7 @@ typedef struct _drm_i915_sarea {
|
|||
#define DRM_I915_GEM_GET_TILING 0x22
|
||||
#define DRM_I915_GEM_GET_APERTURE 0x23
|
||||
#define DRM_I915_GEM_MMAP_GTT 0x24
|
||||
#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
|
||||
|
||||
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
|
||||
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
|
||||
|
@ -219,6 +220,7 @@ typedef struct _drm_i915_sarea {
|
|||
#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
|
||||
#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
|
||||
#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
|
||||
#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_intel_get_pipe_from_crtc_id)
|
||||
|
||||
/* Allow drivers to submit batchbuffers directly to hardware, relying
|
||||
* on the security mechanisms provided by hardware.
|
||||
|
@ -657,4 +659,12 @@ struct drm_i915_gem_get_aperture {
|
|||
__u64 aper_available_size;
|
||||
};
|
||||
|
||||
struct drm_i915_get_pipe_from_crtc_id {
|
||||
/** ID of CRTC being requested **/
|
||||
__u32 crtc_id;
|
||||
|
||||
/** pipe of requested CRTC **/
|
||||
__u32 pipe;
|
||||
};
|
||||
|
||||
#endif /* _I915_DRM_H_ */
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||||
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Reference in a new issue