[PATCH] ppc32: Dump error status for both PLB segments on 440SP
The PowerPC 440SP SoC has two Processor Local Bus (PLB) segments (a high-throughput segment and a low-latency segment). Fix our PLB register definitions to cope with this, and add code to dump the status of both segments when a machine check occurs. Signed-off-by: Roland Dreier <rolandd@cisco.com> Cc: Matt Porter <mporter@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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@ -214,9 +214,20 @@ void __init ibm44x_platform_init(unsigned long r3, unsigned long r4, unsigned lo
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/* Called from machine_check_exception */
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void platform_machine_check(struct pt_regs *regs)
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{
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#ifdef CONFIG_440SP
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printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x%08x\n",
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mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
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mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESRH),
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mfdcr(DCRN_PLB0_BESRL));
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printk("PLB1: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x%08x\n",
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mfdcr(DCRN_PLB1_BEARH), mfdcr(DCRN_PLB1_BEARL),
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mfdcr(DCRN_PLB1_ACR), mfdcr(DCRN_PLB1_BESRH),
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mfdcr(DCRN_PLB1_BESRL));
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#else
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printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x\n",
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mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
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mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESR));
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#endif
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printk("POB0: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n",
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mfdcr(DCRN_POB0_BEARH), mfdcr(DCRN_POB0_BEARL),
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mfdcr(DCRN_POB0_BESR0), mfdcr(DCRN_POB0_BESR1));
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@ -302,6 +302,23 @@
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#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */
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#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */
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#if defined(CONFIG_440SP)
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/* 440SP PLB Arbiter DCRs */
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#define DCRN_PLB_REVID 0x080 /* PLB Revision ID */
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#define DCRN_PLB_CCR 0x088 /* PLB Crossbar Control */
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#define DCRN_PLB0_ACR 0x081 /* PLB Arbiter Control */
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#define DCRN_PLB0_BESRL 0x082 /* PLB Error Status */
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#define DCRN_PLB0_BESRH 0x083 /* PLB Error Status */
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#define DCRN_PLB0_BEARL 0x084 /* PLB Error Address Low */
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#define DCRN_PLB0_BEARH 0x085 /* PLB Error Address High */
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#define DCRN_PLB1_ACR 0x089 /* PLB Arbiter Control */
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#define DCRN_PLB1_BESRL 0x08a /* PLB Error Status */
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#define DCRN_PLB1_BESRH 0x08b /* PLB Error Status */
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#define DCRN_PLB1_BEARL 0x08c /* PLB Error Address Low */
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#define DCRN_PLB1_BEARH 0x08d /* PLB Error Address High */
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#else
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/* 440GP/GX PLB Arbiter DCRs */
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#define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */
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#define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */
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@ -309,6 +326,7 @@
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#define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */
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#define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */
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#define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */
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#endif
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/* 440GP/GX PLB to OPB bridge DCRs */
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#define DCRN_POB0_BESR0 0x090
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