ntb: intel: remove b2b memory window workaround for Skylake NTB
The workaround code is never used because Skylake NTB does not need it. Reported-by: Allen Hubbe <allen.hubbe@dell.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
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3a814a04e6
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4201a9918c
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@ -1742,89 +1742,18 @@ static int skx_setup_b2b_mw(struct intel_ntb_dev *ndev,
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{
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struct pci_dev *pdev;
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void __iomem *mmio;
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resource_size_t bar_size;
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phys_addr_t bar_addr;
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int b2b_bar;
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u8 bar_sz;
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pdev = ndev->ntb.pdev;
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mmio = ndev->self_mmio;
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if (ndev->b2b_idx == UINT_MAX) {
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dev_dbg(&pdev->dev, "not using b2b mw\n");
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b2b_bar = 0;
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ndev->b2b_off = 0;
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} else {
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b2b_bar = ndev_mw_to_bar(ndev, ndev->b2b_idx);
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if (b2b_bar < 0)
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return -EIO;
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dev_dbg(&pdev->dev, "using b2b mw bar %d\n", b2b_bar);
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bar_size = pci_resource_len(ndev->ntb.pdev, b2b_bar);
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dev_dbg(&pdev->dev, "b2b bar size %#llx\n", bar_size);
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if (b2b_mw_share && ((bar_size >> 1) >= XEON_B2B_MIN_SIZE)) {
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dev_dbg(&pdev->dev, "b2b using first half of bar\n");
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ndev->b2b_off = bar_size >> 1;
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} else if (bar_size >= XEON_B2B_MIN_SIZE) {
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dev_dbg(&pdev->dev, "b2b using whole bar\n");
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ndev->b2b_off = 0;
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--ndev->mw_count;
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} else {
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dev_dbg(&pdev->dev, "b2b bar size is too small\n");
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return -EIO;
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}
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}
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/*
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* Reset the secondary bar sizes to match the primary bar sizes,
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* except disable or halve the size of the b2b secondary bar.
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*/
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pci_read_config_byte(pdev, SKX_IMBAR1SZ_OFFSET, &bar_sz);
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dev_dbg(&pdev->dev, "IMBAR1SZ %#x\n", bar_sz);
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if (b2b_bar == 1) {
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if (ndev->b2b_off)
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bar_sz -= 1;
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else
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bar_sz = 0;
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}
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pci_write_config_byte(pdev, SKX_EMBAR1SZ_OFFSET, bar_sz);
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pci_read_config_byte(pdev, SKX_EMBAR1SZ_OFFSET, &bar_sz);
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dev_dbg(&pdev->dev, "EMBAR1SZ %#x\n", bar_sz);
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pci_read_config_byte(pdev, SKX_IMBAR2SZ_OFFSET, &bar_sz);
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dev_dbg(&pdev->dev, "IMBAR2SZ %#x\n", bar_sz);
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if (b2b_bar == 2) {
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if (ndev->b2b_off)
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bar_sz -= 1;
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else
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bar_sz = 0;
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}
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pci_write_config_byte(pdev, SKX_EMBAR2SZ_OFFSET, bar_sz);
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pci_read_config_byte(pdev, SKX_EMBAR2SZ_OFFSET, &bar_sz);
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dev_dbg(&pdev->dev, "EMBAR2SZ %#x\n", bar_sz);
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/* SBAR01 hit by first part of the b2b bar */
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if (b2b_bar == 0)
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bar_addr = addr->bar0_addr;
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else if (b2b_bar == 1)
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bar_addr = addr->bar2_addr64;
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else if (b2b_bar == 2)
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bar_addr = addr->bar4_addr64;
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else
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return -EIO;
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/* setup incoming bar limits == base addrs (zero length windows) */
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bar_addr = addr->bar2_addr64 + (b2b_bar == 1 ? ndev->b2b_off : 0);
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bar_addr = addr->bar2_addr64;
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iowrite64(bar_addr, mmio + SKX_IMBAR1XLMT_OFFSET);
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bar_addr = ioread64(mmio + SKX_IMBAR1XLMT_OFFSET);
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dev_dbg(&pdev->dev, "IMBAR1XLMT %#018llx\n", bar_addr);
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bar_addr = addr->bar4_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0);
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bar_addr = addr->bar4_addr64;
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iowrite64(bar_addr, mmio + SKX_IMBAR2XLMT_OFFSET);
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bar_addr = ioread64(mmio + SKX_IMBAR2XLMT_OFFSET);
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dev_dbg(&pdev->dev, "IMBAR2XLMT %#018llx\n", bar_addr);
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