Merge tag 'drm-intel-fixes-2014-02-14' of ssh://git.freedesktop.org/git/drm-intel into drm-fixes
3 fixes plus 1 prep patch, all four cc: stable. Jani will take over from here and the plan is that he'll do 3.14-fixes for the entire release just to work things out a bit. * tag 'drm-intel-fixes-2014-02-14' of ssh://git.freedesktop.org/git/drm-intel: drm/i915/dp: add native aux defer retry limit drm/i915/dp: increase native aux defer retry timeout drm/i915: Prevent MI_DISPLAY_FLIP straddling two cachelines on IVB drm/i915: Add intel_ring_cachline_align()
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commit
42738c2b39
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@ -8586,6 +8586,20 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
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if (ring->id == RCS)
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len += 6;
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/*
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* BSpec MI_DISPLAY_FLIP for IVB:
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* "The full packet must be contained within the same cache line."
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*
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* Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
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* cacheline, if we ever start emitting more commands before
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* the MI_DISPLAY_FLIP we may need to first emit everything else,
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* then do the cacheline alignment, and finally emit the
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* MI_DISPLAY_FLIP.
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*/
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ret = intel_ring_cacheline_align(ring);
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if (ret)
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goto err_unpin;
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ret = intel_ring_begin(ring, len);
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if (ret)
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goto err_unpin;
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@ -537,6 +537,7 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
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uint8_t msg[20];
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int msg_bytes;
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uint8_t ack;
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int retry;
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if (WARN_ON(send_bytes > 16))
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return -E2BIG;
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@ -548,19 +549,21 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
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msg[3] = send_bytes - 1;
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memcpy(&msg[4], send, send_bytes);
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msg_bytes = send_bytes + 4;
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for (;;) {
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for (retry = 0; retry < 7; retry++) {
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ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
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if (ret < 0)
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return ret;
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ack >>= 4;
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if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
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break;
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return send_bytes;
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else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
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udelay(100);
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usleep_range(400, 500);
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else
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return -EIO;
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}
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return send_bytes;
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DRM_ERROR("too many retries, giving up\n");
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return -EIO;
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}
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/* Write a single byte to the aux channel in native mode */
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@ -582,6 +585,7 @@ intel_dp_aux_native_read(struct intel_dp *intel_dp,
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int reply_bytes;
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uint8_t ack;
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int ret;
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int retry;
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if (WARN_ON(recv_bytes > 19))
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return -E2BIG;
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@ -595,7 +599,7 @@ intel_dp_aux_native_read(struct intel_dp *intel_dp,
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msg_bytes = 4;
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reply_bytes = recv_bytes + 1;
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for (;;) {
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for (retry = 0; retry < 7; retry++) {
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ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
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reply, reply_bytes);
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if (ret == 0)
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@ -608,10 +612,13 @@ intel_dp_aux_native_read(struct intel_dp *intel_dp,
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return ret - 1;
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}
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else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
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udelay(100);
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usleep_range(400, 500);
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else
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return -EIO;
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}
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DRM_ERROR("too many retries, giving up\n");
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return -EIO;
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}
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static int
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@ -1653,6 +1653,27 @@ int intel_ring_begin(struct intel_ring_buffer *ring,
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return 0;
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}
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/* Align the ring tail to a cacheline boundary */
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int intel_ring_cacheline_align(struct intel_ring_buffer *ring)
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{
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int num_dwords = (64 - (ring->tail & 63)) / sizeof(uint32_t);
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int ret;
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if (num_dwords == 0)
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return 0;
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ret = intel_ring_begin(ring, num_dwords);
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if (ret)
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return ret;
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while (num_dwords--)
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intel_ring_emit(ring, MI_NOOP);
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intel_ring_advance(ring);
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return 0;
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}
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void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
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{
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struct drm_i915_private *dev_priv = ring->dev->dev_private;
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@ -233,6 +233,7 @@ intel_write_status_page(struct intel_ring_buffer *ring,
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void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
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int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
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int __must_check intel_ring_cacheline_align(struct intel_ring_buffer *ring);
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static inline void intel_ring_emit(struct intel_ring_buffer *ring,
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u32 data)
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{
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