[MIPS] Replace BARRIER with more appropriate hazard barrier.
This is the unchanged part 2 of Chris' hazard cleanup. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -26,11 +26,6 @@ extern void build_tlb_refill_handler(void);
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*/
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#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
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/* CP0 hazard avoidance. */
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#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
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"nop; nop; nop; nop; nop; nop;\n\t" \
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".set reorder\n\t")
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/* Atomicity and interruptability */
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#ifdef CONFIG_MIPS_MT_SMTC
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@ -126,7 +121,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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start += (PAGE_SIZE << 1);
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mtc0_tlbw_hazard();
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tlb_probe();
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BARRIER;
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tlb_probe_hazard();
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idx = read_c0_index();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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@ -168,7 +163,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
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start += (PAGE_SIZE << 1);
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mtc0_tlbw_hazard();
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tlb_probe();
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BARRIER;
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tlb_probe_hazard();
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idx = read_c0_index();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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@ -202,7 +197,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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write_c0_entryhi(page | newpid);
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mtc0_tlbw_hazard();
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tlb_probe();
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BARRIER;
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tlb_probe_hazard();
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idx = read_c0_index();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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@ -235,7 +230,7 @@ void local_flush_tlb_one(unsigned long page)
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write_c0_entryhi(page);
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mtc0_tlbw_hazard();
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tlb_probe();
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BARRIER;
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tlb_probe_hazard();
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idx = read_c0_index();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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@ -279,7 +274,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
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pgdp = pgd_offset(vma->vm_mm, address);
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mtc0_tlbw_hazard();
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tlb_probe();
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BARRIER;
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tlb_probe_hazard();
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pudp = pud_offset(pgdp, address);
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pmdp = pmd_offset(pudp, address);
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idx = read_c0_index();
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@ -320,7 +315,7 @@ static void r4k_update_mmu_cache_hwbug(struct vm_area_struct * vma,
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pgdp = pgd_offset(vma->vm_mm, address);
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mtc0_tlbw_hazard();
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tlb_probe();
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BARRIER;
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tlb_probe_hazard();
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pmdp = pmd_offset(pgdp, address);
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idx = read_c0_index();
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ptep = pte_offset_map(pmdp, address);
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@ -351,7 +346,7 @@ void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
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wired = read_c0_wired();
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write_c0_wired(wired + 1);
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write_c0_index(wired);
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BARRIER;
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tlbw_use_hazard(); /* What is the hazard here? */
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write_c0_pagemask(pagemask);
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write_c0_entryhi(entryhi);
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write_c0_entrylo0(entrylo0);
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@ -361,7 +356,7 @@ void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
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tlbw_use_hazard();
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write_c0_entryhi(old_ctx);
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BARRIER;
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tlbw_use_hazard(); /* What is the hazard here? */
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write_c0_pagemask(old_pagemask);
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local_flush_tlb_all();
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EXIT_CRITICAL(flags);
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