sparc64: Define VA hole at run time, rather than at compile time.
Now that we use 4-level page tables, we can provide up to 53-bits of virtual address space to the user. Adjust the VA hole based upon the capabilities of the cpu type probed. Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Bob Picco <bob.picco@oracle.com>
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@ -102,21 +102,14 @@ typedef unsigned long pgprot_t;
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typedef pte_t *pgtable_t;
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/* These two values define the virtual address space range in which we
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* must forbid 64-bit user processes from making mappings. It used to
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* represent precisely the virtual address space hole present in most
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* early sparc64 chips including UltraSPARC-I. But now it also is
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* further constrained by the limits of our page tables, which is
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* 43-bits of virtual address.
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*/
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#define SPARC64_VA_HOLE_TOP _AC(0xfffffc0000000000,UL)
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#define SPARC64_VA_HOLE_BOTTOM _AC(0x0000040000000000,UL)
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extern unsigned long sparc64_va_hole_top;
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extern unsigned long sparc64_va_hole_bottom;
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/* The next two defines specify the actual exclusion region we
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* enforce, wherein we use a 4GB red zone on each side of the VA hole.
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*/
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#define VA_EXCLUDE_START (SPARC64_VA_HOLE_BOTTOM - (1UL << 32UL))
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#define VA_EXCLUDE_END (SPARC64_VA_HOLE_TOP + (1UL << 32UL))
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#define VA_EXCLUDE_START (sparc64_va_hole_bottom - (1UL << 32UL))
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#define VA_EXCLUDE_END (sparc64_va_hole_top + (1UL << 32UL))
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#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_32BIT) ? \
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_AC(0x0000000070000000,UL) : \
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@ -1630,25 +1630,46 @@ static void __init page_offset_shift_patch(unsigned long phys_bits)
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}
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}
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unsigned long sparc64_va_hole_top = 0xfffff80000000000UL;
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unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
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static void __init setup_page_offset(void)
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{
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unsigned long max_phys_bits = 40;
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if (tlb_type == cheetah || tlb_type == cheetah_plus) {
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/* Cheetah/Panther support a full 64-bit virtual
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* address, so we can use all that our page tables
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* support.
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*/
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sparc64_va_hole_top = 0xfff0000000000000UL;
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sparc64_va_hole_bottom = 0x0010000000000000UL;
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max_phys_bits = 42;
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} else if (tlb_type == hypervisor) {
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switch (sun4v_chip_type) {
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case SUN4V_CHIP_NIAGARA1:
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case SUN4V_CHIP_NIAGARA2:
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/* T1 and T2 support 48-bit virtual addresses. */
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sparc64_va_hole_top = 0xffff800000000000UL;
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sparc64_va_hole_bottom = 0x0000800000000000UL;
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max_phys_bits = 39;
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break;
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case SUN4V_CHIP_NIAGARA3:
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/* T3 supports 48-bit virtual addresses. */
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sparc64_va_hole_top = 0xffff800000000000UL;
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sparc64_va_hole_bottom = 0x0000800000000000UL;
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max_phys_bits = 43;
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break;
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case SUN4V_CHIP_NIAGARA4:
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case SUN4V_CHIP_NIAGARA5:
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case SUN4V_CHIP_SPARC64X:
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default:
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/* T4 and later support 52-bit virtual addresses. */
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sparc64_va_hole_top = 0xfff8000000000000UL;
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sparc64_va_hole_bottom = 0x0008000000000000UL;
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max_phys_bits = 47;
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break;
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}
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