clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCs
The patch enables CPU multiplexer clock on MT2701/MT7623 SoC which fixes up cpufreq driver fails at acquiring intermediate clock source when driver probe is called. Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -20,6 +20,7 @@
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include "clk-cpumux.h"
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#include <dt-bindings/clock/mt2701-clk.h>
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@ -493,6 +494,10 @@ static const char * const cpu_parents[] = {
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"mmpll"
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};
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static const struct mtk_composite cpu_muxes[] __initconst = {
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MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
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};
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static const struct mtk_composite top_muxes[] = {
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MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
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0x0040, 0, 3, 7, CLK_IS_CRITICAL),
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@ -759,6 +764,9 @@ static void mtk_infrasys_init_early(struct device_node *node)
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mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
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infra_clk_data);
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mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
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infra_clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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@ -221,7 +221,8 @@
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#define CLK_INFRA_PMICWRAP 17
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#define CLK_INFRA_DDCCI 18
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#define CLK_INFRA_CLK_13M 19
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#define CLK_INFRA_NR 20
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#define CLK_INFRA_CPUSEL 20
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#define CLK_INFRA_NR 21
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/* PERICFG */
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