pinctrl: samsung: Remove hardcoded register offsets
This patch replaces statically hardcoded register offsets of Exynos SoCs with an array of register offsets in samsung_pin_bank_type struct. Thanks to this change, support for SoCs with other set and order of registers can be added (e.g. S3C24xx and S3C64xx). Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Tomasz Figa
Linus Walleij
parent
499147c9db
commit
43fc9e7fab
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@ -37,10 +37,12 @@
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static struct samsung_pin_bank_type bank_type_off = {
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.fld_width = { 4, 1, 2, 2, 2, 2, },
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.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
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};
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static struct samsung_pin_bank_type bank_type_alive = {
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.fld_width = { 4, 1, 2, 2, },
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.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
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};
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/* list of external wakeup controllers supported */
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@ -126,7 +128,7 @@ static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
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con |= trig_type << shift;
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writel(con, d->virt_base + reg_con);
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reg_con = bank->pctl_offset;
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reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
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shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
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mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
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@ -309,7 +311,7 @@ static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
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con |= trig_type << shift;
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writel(con, d->virt_base + reg_con);
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reg_con = bank->pctl_offset;
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reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
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shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
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mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
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@ -275,10 +275,6 @@ static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata,
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*offset = pin - b->pin_base;
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if (bank)
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*bank = b;
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/* some banks have two config registers in a single bank */
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if (*offset * b->func_width > BITS_PER_LONG)
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*reg += 4;
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}
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/* enable or disable a pinmux function */
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@ -310,11 +306,11 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
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spin_lock_irqsave(&bank->slock, flags);
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data = readl(reg);
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data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]);
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data &= ~(mask << shift);
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if (enable)
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data |= drvdata->pin_groups[group].func << shift;
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writel(data, reg);
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writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]);
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spin_unlock_irqrestore(&bank->slock, flags);
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}
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@ -355,7 +351,8 @@ static int samsung_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
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drvdata = pinctrl_dev_get_drvdata(pctldev);
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pin_offset = offset - bank->pin_base;
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reg = drvdata->virt_base + bank->pctl_offset;
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reg = drvdata->virt_base + bank->pctl_offset +
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type->reg_offset[PINCFG_TYPE_FUNC];
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mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1;
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shift = pin_offset * type->fld_width[PINCFG_TYPE_FUNC];
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@ -401,28 +398,11 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
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&pin_offset, &bank);
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type = bank->type;
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switch (cfg_type) {
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case PINCFG_TYPE_PUD:
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cfg_reg = PUD_REG;
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break;
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case PINCFG_TYPE_DRV:
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cfg_reg = DRV_REG;
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break;
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case PINCFG_TYPE_CON_PDN:
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cfg_reg = CONPDN_REG;
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break;
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case PINCFG_TYPE_PUD_PDN:
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cfg_reg = PUDPDN_REG;
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break;
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default:
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WARN_ON(1);
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return -EINVAL;
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}
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if (cfg_type >= PINCFG_TYPE_NUM || !type->fld_width[cfg_type])
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return -EINVAL;
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width = type->fld_width[cfg_type];
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cfg_reg = type->reg_offset[cfg_type];
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spin_lock_irqsave(&bank->slock, flags);
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@ -511,11 +491,11 @@ static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
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spin_lock_irqsave(&bank->slock, flags);
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data = readl(reg + DAT_REG);
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data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]);
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data &= ~(1 << offset);
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if (value)
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data |= 1 << offset;
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writel(data, reg + DAT_REG);
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writel(data, reg + type->reg_offset[PINCFG_TYPE_DAT]);
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spin_unlock_irqrestore(&bank->slock, flags);
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}
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@ -526,10 +506,11 @@ static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
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void __iomem *reg;
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u32 data;
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struct samsung_pin_bank *bank = gc_to_pin_bank(gc);
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struct samsung_pin_bank_type *type = bank->type;
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reg = bank->drvdata->virt_base + bank->pctl_offset;
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data = readl(reg + DAT_REG);
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data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]);
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data >>= offset;
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data &= 1;
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return data;
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@ -25,13 +25,6 @@
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#include <linux/gpio.h>
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/* register offsets within a pin bank */
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#define DAT_REG 0x4
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#define PUD_REG 0x8
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#define DRV_REG 0xC
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#define CONPDN_REG 0x10
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#define PUDPDN_REG 0x14
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/* pinmux function number for pin as gpio output line */
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#define FUNC_OUTPUT 0x1
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@ -111,9 +104,11 @@ struct samsung_pinctrl_drv_data;
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/**
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* struct samsung_pin_bank_type: pin bank type description
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* @fld_width: widths of configuration bitfields (0 if unavailable)
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* @reg_offset: offsets of configuration registers (don't care of width is 0)
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*/
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struct samsung_pin_bank_type {
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u8 fld_width[PINCFG_TYPE_NUM];
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u8 reg_offset[PINCFG_TYPE_NUM];
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};
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/**
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