vfio/pci: Hide broken INTx support from user
INTx masking has two components, the first is that we need the ability to prevent the device from continuing to assert INTx. This is provided via the DisINTx bit in the command register and is the only thing we can really probe for when testing if INTx masking is supported. The second component is that the device needs to indicate if INTx is asserted via the interrupt status bit in the device status register. With these two features we can generically determine if one of the devices we own is asserting INTx, signal the user, and mask the interrupt while the user services the device. Generally if one or both of these components is broken we resort to APIC level interrupt masking, which requires an exclusive interrupt since we have no way to determine the source of the interrupt in a shared configuration. This often makes it difficult or impossible to configure the system for userspace use of the device, for an interrupt mode that the user may not need. One possible configuration of broken INTx masking is that the DisINTx support is fully functional, but the interrupt status bit never signals interrupt assertion. In this case we do have the ability to prevent the device from asserting INTx, but lack the ability to identify the interrupt source. For this case we can simply pretend that the device lacks INTx support entirely, keeping DisINTx set on the physical device, virtualizing this bit for the user, and virtualizing the interrupt pin register to indicate no INTx support. We already support virtualization of the DisINTx bit and already virtualize the interrupt pin for platforms without INTx support. By tying these components together, setting DisINTx on open and reset, and identifying devices broken in this particular way, we can provide support for them w/o the handicap of APIC level INTx masking. Intel i40e (XL710/X710) 10/20/40GbE NICs have been identified as being broken in this specific way. We leave the vfio-pci.nointxmask option as a mechanism to bypass this support, enabling INTx on the device with all the requirements of APIC level masking. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Cc: John Ronciak <john.ronciak@intel.com> Cc: Jesse Brandeburg <jesse.brandeburg@intel.com>
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@ -113,6 +113,35 @@ static inline bool vfio_pci_is_vga(struct pci_dev *pdev)
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static void vfio_pci_try_bus_reset(struct vfio_pci_device *vdev);
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static void vfio_pci_disable(struct vfio_pci_device *vdev);
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/*
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* INTx masking requires the ability to disable INTx signaling via PCI_COMMAND
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* _and_ the ability detect when the device is asserting INTx via PCI_STATUS.
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* If a device implements the former but not the latter we would typically
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* expect broken_intx_masking be set and require an exclusive interrupt.
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* However since we do have control of the device's ability to assert INTx,
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* we can instead pretend that the device does not implement INTx, virtualizing
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* the pin register to report zero and maintaining DisINTx set on the host.
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*/
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static bool vfio_pci_nointx(struct pci_dev *pdev)
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{
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switch (pdev->vendor) {
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case PCI_VENDOR_ID_INTEL:
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switch (pdev->device) {
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/* All i40e (XL710/X710) 10/20/40GbE NICs */
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case 0x1572:
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case 0x1574:
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case 0x1580 ... 0x1581:
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case 0x1583 ... 0x1589:
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case 0x37d0 ... 0x37d2:
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return true;
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default:
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return false;
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}
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}
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return false;
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}
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static int vfio_pci_enable(struct vfio_pci_device *vdev)
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{
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struct pci_dev *pdev = vdev->pdev;
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@ -136,6 +165,21 @@ static int vfio_pci_enable(struct vfio_pci_device *vdev)
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pr_debug("%s: Couldn't store %s saved state\n",
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__func__, dev_name(&pdev->dev));
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if (likely(!nointxmask)) {
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if (vfio_pci_nointx(pdev)) {
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dev_info(&pdev->dev, "Masking broken INTx support\n");
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vdev->nointx = true;
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pci_intx(pdev, 0);
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} else
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vdev->pci_2_3 = pci_intx_mask_supported(pdev);
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}
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pci_read_config_word(pdev, PCI_COMMAND, &cmd);
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if (vdev->pci_2_3 && (cmd & PCI_COMMAND_INTX_DISABLE)) {
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cmd &= ~PCI_COMMAND_INTX_DISABLE;
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pci_write_config_word(pdev, PCI_COMMAND, cmd);
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}
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ret = vfio_config_init(vdev);
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if (ret) {
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kfree(vdev->pci_saved_state);
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@ -144,15 +188,6 @@ static int vfio_pci_enable(struct vfio_pci_device *vdev)
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return ret;
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}
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if (likely(!nointxmask))
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vdev->pci_2_3 = pci_intx_mask_supported(pdev);
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pci_read_config_word(pdev, PCI_COMMAND, &cmd);
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if (vdev->pci_2_3 && (cmd & PCI_COMMAND_INTX_DISABLE)) {
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cmd &= ~PCI_COMMAND_INTX_DISABLE;
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pci_write_config_word(pdev, PCI_COMMAND, cmd);
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}
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msix_pos = pdev->msix_cap;
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if (msix_pos) {
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u16 flags;
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@ -304,7 +339,7 @@ static int vfio_pci_get_irq_count(struct vfio_pci_device *vdev, int irq_type)
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if (irq_type == VFIO_PCI_INTX_IRQ_INDEX) {
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u8 pin;
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pci_read_config_byte(vdev->pdev, PCI_INTERRUPT_PIN, &pin);
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if (IS_ENABLED(CONFIG_VFIO_PCI_INTX) && pin)
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if (IS_ENABLED(CONFIG_VFIO_PCI_INTX) && !vdev->nointx && pin)
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return 1;
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} else if (irq_type == VFIO_PCI_MSI_IRQ_INDEX) {
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@ -408,6 +408,7 @@ static void vfio_bar_restore(struct vfio_pci_device *vdev)
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{
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struct pci_dev *pdev = vdev->pdev;
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u32 *rbar = vdev->rbar;
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u16 cmd;
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int i;
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if (pdev->is_virtfn)
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@ -420,6 +421,12 @@ static void vfio_bar_restore(struct vfio_pci_device *vdev)
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pci_user_write_config_dword(pdev, i, *rbar);
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pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar);
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if (vdev->nointx) {
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pci_user_read_config_word(pdev, PCI_COMMAND, &cmd);
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cmd |= PCI_COMMAND_INTX_DISABLE;
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pci_user_write_config_word(pdev, PCI_COMMAND, cmd);
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}
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}
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static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar)
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@ -1545,7 +1552,7 @@ int vfio_config_init(struct vfio_pci_device *vdev)
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*(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device);
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}
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if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX))
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if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX) || vdev->nointx)
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vconfig[PCI_INTERRUPT_PIN] = 0;
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ret = vfio_cap_init(vdev);
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@ -83,6 +83,7 @@ struct vfio_pci_device {
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bool bardirty;
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bool has_vga;
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bool needs_reset;
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bool nointx;
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struct pci_saved_state *pci_saved_state;
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int refcnt;
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struct eventfd_ctx *err_trigger;
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