Merge remote-tracking branches 'spi/topic/xilinx' and 'spi/topic/xtfpga' into spi-next
This commit is contained in:
commit
45b15d98a9
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@ -0,0 +1,9 @@
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Cadence Xtensa XTFPGA platform SPI controller.
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This simple SPI master controller is built into xtfpga bitstreams and is used
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to control daughterboard audio codec.
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Required properties:
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- compatible: should be "cdns,xtfpga-spi".
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- reg: physical base address of the controller and length of memory mapped
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region.
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@ -9782,6 +9782,12 @@ L: linux-serial@vger.kernel.org
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S: Maintained
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S: Maintained
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F: drivers/tty/serial/uartlite.c
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F: drivers/tty/serial/uartlite.c
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XTENSA XTFPGA PLATFORM SUPPORT
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M: Max Filippov <jcmvbkbc@gmail.com>
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L: linux-xtensa@linux-xtensa.org
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S: Maintained
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F: drivers/spi/spi-xtensa-xtfpga.c
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YAM DRIVER FOR AX.25
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YAM DRIVER FOR AX.25
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M: Jean-Paul Roubelat <jpr@f6fbb.org>
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M: Jean-Paul Roubelat <jpr@f6fbb.org>
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L: linux-hams@vger.kernel.org
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L: linux-hams@vger.kernel.org
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@ -538,6 +538,19 @@ config SPI_XILINX
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Or for the DS570, see "XPS Serial Peripheral Interface (SPI) (v2.00b)"
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Or for the DS570, see "XPS Serial Peripheral Interface (SPI) (v2.00b)"
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config SPI_XTENSA_XTFPGA
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tristate "Xtensa SPI controller for xtfpga"
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depends on (XTENSA && XTENSA_PLATFORM_XTFPGA) || COMPILE_TEST
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select SPI_BITBANG
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help
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SPI driver for xtfpga SPI master controller.
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This simple SPI master controller is built into xtfpga bitstreams
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and is used to control daughterboard audio codec. It always transfers
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16 bit words in SPI mode 0, automatically asserting CS on transfer
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start and deasserting on end.
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config SPI_NUC900
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config SPI_NUC900
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tristate "Nuvoton NUC900 series SPI"
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tristate "Nuvoton NUC900 series SPI"
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depends on ARCH_W90X900
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depends on ARCH_W90X900
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@ -81,3 +81,4 @@ obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
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obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
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obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
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obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o
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obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o
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obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
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obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
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obj-$(CONFIG_SPI_XTENSA_XTFPGA) += spi-xtensa-xtfpga.o
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@ -87,10 +87,10 @@ struct xilinx_spi {
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const u8 *tx_ptr; /* pointer in the Rx buffer */
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const u8 *tx_ptr; /* pointer in the Rx buffer */
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int remaining_bytes; /* the number of bytes left to transfer */
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int remaining_bytes; /* the number of bytes left to transfer */
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u8 bits_per_word;
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u8 bits_per_word;
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unsigned int (*read_fn) (void __iomem *);
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unsigned int (*read_fn)(void __iomem *);
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void (*write_fn) (u32, void __iomem *);
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void (*write_fn)(u32, void __iomem *);
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void (*tx_fn) (struct xilinx_spi *);
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void (*tx_fn)(struct xilinx_spi *);
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void (*rx_fn) (struct xilinx_spi *);
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void (*rx_fn)(struct xilinx_spi *);
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};
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};
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static void xspi_write32(u32 val, void __iomem *addr)
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static void xspi_write32(u32 val, void __iomem *addr)
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@ -208,26 +208,11 @@ static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
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}
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}
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/* spi_bitbang requires custom setup_transfer() to be defined if there is a
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/* spi_bitbang requires custom setup_transfer() to be defined if there is a
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* custom txrx_bufs(). We have nothing to setup here as the SPI IP block
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* custom txrx_bufs().
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* supports 8 or 16 bits per word which cannot be changed in software.
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* SPI clock can't be changed in software either.
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* Check for correct bits per word. Chip select delay calculations could be
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* added here as soon as bitbang_work() can be made aware of the delay value.
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*/
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*/
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static int xilinx_spi_setup_transfer(struct spi_device *spi,
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static int xilinx_spi_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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struct spi_transfer *t)
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{
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{
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struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
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u8 bits_per_word;
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bits_per_word = (t && t->bits_per_word)
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? t->bits_per_word : spi->bits_per_word;
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if (bits_per_word != xspi->bits_per_word) {
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dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
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__func__, bits_per_word);
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return -EINVAL;
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}
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return 0;
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return 0;
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}
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}
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@ -406,6 +391,7 @@ static int xilinx_spi_probe(struct platform_device *pdev)
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xspi->write_fn = xspi_write32_be;
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xspi->write_fn = xspi_write32_be;
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}
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}
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master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word);
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xspi->bits_per_word = bits_per_word;
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xspi->bits_per_word = bits_per_word;
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if (xspi->bits_per_word == 8) {
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if (xspi->bits_per_word == 8) {
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xspi->tx_fn = xspi_tx8;
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xspi->tx_fn = xspi_tx8;
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170
drivers/spi/spi-xtensa-xtfpga.c
Normal file
170
drivers/spi/spi-xtensa-xtfpga.c
Normal file
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@ -0,0 +1,170 @@
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/*
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* Xtensa xtfpga SPI controller driver
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*
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* Copyright (c) 2014 Cadence Design Systems Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#define XTFPGA_SPI_NAME "xtfpga_spi"
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#define XTFPGA_SPI_START 0x0
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#define XTFPGA_SPI_BUSY 0x4
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#define XTFPGA_SPI_DATA 0x8
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#define BUSY_WAIT_US 100
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struct xtfpga_spi {
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struct spi_bitbang bitbang;
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void __iomem *regs;
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u32 data;
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unsigned data_sz;
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};
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static inline void xtfpga_spi_write32(const struct xtfpga_spi *spi,
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unsigned addr, u32 val)
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{
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iowrite32(val, spi->regs + addr);
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}
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static inline unsigned int xtfpga_spi_read32(const struct xtfpga_spi *spi,
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unsigned addr)
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{
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return ioread32(spi->regs + addr);
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}
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static inline void xtfpga_spi_wait_busy(struct xtfpga_spi *xspi)
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{
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unsigned i;
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for (i = 0; xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY) &&
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i < BUSY_WAIT_US; ++i)
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udelay(1);
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WARN_ON_ONCE(i == BUSY_WAIT_US);
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}
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static u32 xtfpga_spi_txrx_word(struct spi_device *spi, unsigned nsecs,
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u32 v, u8 bits)
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{
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struct xtfpga_spi *xspi = spi_master_get_devdata(spi->master);
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xspi->data = (xspi->data << bits) | (v & GENMASK(bits - 1, 0));
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xspi->data_sz += bits;
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if (xspi->data_sz >= 16) {
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xtfpga_spi_write32(xspi, XTFPGA_SPI_DATA,
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xspi->data >> (xspi->data_sz - 16));
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xspi->data_sz -= 16;
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xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 1);
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xtfpga_spi_wait_busy(xspi);
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xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 0);
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}
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return 0;
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}
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static void xtfpga_spi_chipselect(struct spi_device *spi, int is_on)
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{
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struct xtfpga_spi *xspi = spi_master_get_devdata(spi->master);
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WARN_ON(xspi->data_sz != 0);
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xspi->data_sz = 0;
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}
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static int xtfpga_spi_probe(struct platform_device *pdev)
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{
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struct xtfpga_spi *xspi;
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struct resource *mem;
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int ret;
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struct spi_master *master;
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master = spi_alloc_master(&pdev->dev, sizeof(struct xtfpga_spi));
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if (!master)
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return -ENOMEM;
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master->flags = SPI_MASTER_NO_RX;
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master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
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master->bus_num = pdev->dev.id;
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master->dev.of_node = pdev->dev.of_node;
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xspi = spi_master_get_devdata(master);
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xspi->bitbang.master = master;
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xspi->bitbang.chipselect = xtfpga_spi_chipselect;
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xspi->bitbang.txrx_word[SPI_MODE_0] = xtfpga_spi_txrx_word;
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!mem) {
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dev_err(&pdev->dev, "No memory resource\n");
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ret = -ENODEV;
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goto err;
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}
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xspi->regs = devm_ioremap_resource(&pdev->dev, mem);
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if (IS_ERR(xspi->regs)) {
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ret = PTR_ERR(xspi->regs);
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goto err;
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}
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xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 0);
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usleep_range(1000, 2000);
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if (xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY)) {
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dev_err(&pdev->dev, "Device stuck in busy state\n");
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ret = -EBUSY;
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goto err;
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}
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ret = spi_bitbang_start(&xspi->bitbang);
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if (ret < 0) {
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dev_err(&pdev->dev, "spi_bitbang_start failed\n");
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goto err;
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}
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platform_set_drvdata(pdev, master);
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return 0;
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err:
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spi_master_put(master);
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return ret;
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}
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static int xtfpga_spi_remove(struct platform_device *pdev)
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{
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struct spi_master *master = platform_get_drvdata(pdev);
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struct xtfpga_spi *xspi = spi_master_get_devdata(master);
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spi_bitbang_stop(&xspi->bitbang);
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spi_master_put(master);
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return 0;
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}
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MODULE_ALIAS("platform:" XTFPGA_SPI_NAME);
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#ifdef CONFIG_OF
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static const struct of_device_id xtfpga_spi_of_match[] = {
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{ .compatible = "cdns,xtfpga-spi", },
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{}
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};
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MODULE_DEVICE_TABLE(of, xtfpga_spi_of_match);
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#endif
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static struct platform_driver xtfpga_spi_driver = {
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.probe = xtfpga_spi_probe,
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.remove = xtfpga_spi_remove,
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.driver = {
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.name = XTFPGA_SPI_NAME,
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.owner = THIS_MODULE,
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.of_match_table = of_match_ptr(xtfpga_spi_of_match),
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},
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};
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module_platform_driver(xtfpga_spi_driver);
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MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>");
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MODULE_DESCRIPTION("xtensa xtfpga SPI driver");
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MODULE_LICENSE("GPL");
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