ARM: dts: imx: Fix "ERROR: code indent should use tabs where possible"
Fixed code indent tabs in respetcive imx23, imx51, imx53, imx6dl, imx6q and imx6sx dtsi and dts files. Signed-off-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
parent
a7859df4fd
commit
4631170793
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@ -464,7 +464,7 @@
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reg = <0x80038000 0x2000>;
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reg = <0x80038000 0x2000>;
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status = "disabled";
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status = "disabled";
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};
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};
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};
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};
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apbx@80040000 {
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apbx@80040000 {
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compatible = "simple-bus";
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compatible = "simple-bus";
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@ -103,8 +103,8 @@
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reg = <0x50004000 0x4000>;
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reg = <0x50004000 0x4000>;
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interrupts = <1>;
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interrupts = <1>;
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clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
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clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_ESDHC1_PER_GATE>;
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<&clks IMX5_CLK_ESDHC1_PER_GATE>;
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clock-names = "ipg", "ahb", "per";
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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bus-width = <4>;
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status = "disabled";
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status = "disabled";
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@ -115,8 +115,8 @@
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reg = <0x50008000 0x4000>;
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reg = <0x50008000 0x4000>;
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interrupts = <2>;
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interrupts = <2>;
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clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
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clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_ESDHC2_PER_GATE>;
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<&clks IMX5_CLK_ESDHC2_PER_GATE>;
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clock-names = "ipg", "ahb", "per";
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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bus-width = <4>;
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status = "disabled";
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status = "disabled";
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@ -127,7 +127,7 @@
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reg = <0x5000c000 0x4000>;
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reg = <0x5000c000 0x4000>;
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interrupts = <33>;
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interrupts = <33>;
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clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
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clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
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<&clks IMX5_CLK_UART3_PER_GATE>;
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<&clks IMX5_CLK_UART3_PER_GATE>;
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clock-names = "ipg", "per";
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clock-names = "ipg", "per";
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status = "disabled";
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status = "disabled";
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};
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};
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@ -139,7 +139,7 @@
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reg = <0x50010000 0x4000>;
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reg = <0x50010000 0x4000>;
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interrupts = <36>;
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interrupts = <36>;
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clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
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clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
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<&clks IMX5_CLK_ECSPI1_PER_GATE>;
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<&clks IMX5_CLK_ECSPI1_PER_GATE>;
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clock-names = "ipg", "per";
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clock-names = "ipg", "per";
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status = "disabled";
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status = "disabled";
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};
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};
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@ -164,8 +164,8 @@
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reg = <0x50020000 0x4000>;
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reg = <0x50020000 0x4000>;
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interrupts = <3>;
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interrupts = <3>;
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clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
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clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_ESDHC3_PER_GATE>;
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<&clks IMX5_CLK_ESDHC3_PER_GATE>;
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clock-names = "ipg", "ahb", "per";
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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bus-width = <4>;
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status = "disabled";
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status = "disabled";
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@ -176,8 +176,8 @@
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reg = <0x50024000 0x4000>;
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reg = <0x50024000 0x4000>;
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interrupts = <4>;
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interrupts = <4>;
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clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
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clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_ESDHC4_PER_GATE>;
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<&clks IMX5_CLK_ESDHC4_PER_GATE>;
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clock-names = "ipg", "ahb", "per";
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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bus-width = <4>;
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status = "disabled";
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status = "disabled";
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@ -279,7 +279,7 @@
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reg = <0x53fa0000 0x4000>;
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reg = <0x53fa0000 0x4000>;
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interrupts = <39>;
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interrupts = <39>;
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clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
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clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
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<&clks IMX5_CLK_GPT_HF_GATE>;
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<&clks IMX5_CLK_GPT_HF_GATE>;
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clock-names = "ipg", "per";
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clock-names = "ipg", "per";
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};
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};
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@ -298,7 +298,7 @@
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compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
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compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
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reg = <0x53fb4000 0x4000>;
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reg = <0x53fb4000 0x4000>;
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clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
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clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
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<&clks IMX5_CLK_PWM1_HF_GATE>;
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<&clks IMX5_CLK_PWM1_HF_GATE>;
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clock-names = "ipg", "per";
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clock-names = "ipg", "per";
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interrupts = <61>;
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interrupts = <61>;
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};
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};
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@ -308,7 +308,7 @@
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compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
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compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
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reg = <0x53fb8000 0x4000>;
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reg = <0x53fb8000 0x4000>;
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clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
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clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
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<&clks IMX5_CLK_PWM2_HF_GATE>;
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<&clks IMX5_CLK_PWM2_HF_GATE>;
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clock-names = "ipg", "per";
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clock-names = "ipg", "per";
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interrupts = <94>;
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interrupts = <94>;
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};
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};
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@ -318,7 +318,7 @@
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reg = <0x53fbc000 0x4000>;
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reg = <0x53fbc000 0x4000>;
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interrupts = <31>;
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interrupts = <31>;
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clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
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clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
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<&clks IMX5_CLK_UART1_PER_GATE>;
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<&clks IMX5_CLK_UART1_PER_GATE>;
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clock-names = "ipg", "per";
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clock-names = "ipg", "per";
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status = "disabled";
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status = "disabled";
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};
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};
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@ -328,7 +328,7 @@
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reg = <0x53fc0000 0x4000>;
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reg = <0x53fc0000 0x4000>;
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interrupts = <32>;
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interrupts = <32>;
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clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
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clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
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<&clks IMX5_CLK_UART2_PER_GATE>;
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<&clks IMX5_CLK_UART2_PER_GATE>;
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clock-names = "ipg", "per";
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clock-names = "ipg", "per";
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status = "disabled";
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status = "disabled";
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};
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};
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@ -383,7 +383,7 @@
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reg = <0x53ff0000 0x4000>;
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reg = <0x53ff0000 0x4000>;
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interrupts = <13>;
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interrupts = <13>;
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clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
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clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
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<&clks IMX5_CLK_UART4_PER_GATE>;
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<&clks IMX5_CLK_UART4_PER_GATE>;
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clock-names = "ipg", "per";
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clock-names = "ipg", "per";
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status = "disabled";
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status = "disabled";
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};
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};
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@ -401,7 +401,7 @@
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reg = <0x63f90000 0x4000>;
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reg = <0x63f90000 0x4000>;
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interrupts = <86>;
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interrupts = <86>;
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clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
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clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
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<&clks IMX5_CLK_UART5_PER_GATE>;
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<&clks IMX5_CLK_UART5_PER_GATE>;
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clock-names = "ipg", "per";
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clock-names = "ipg", "per";
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status = "disabled";
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status = "disabled";
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};
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};
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@ -420,7 +420,7 @@
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reg = <0x63fac000 0x4000>;
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reg = <0x63fac000 0x4000>;
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interrupts = <37>;
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interrupts = <37>;
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clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
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clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
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<&clks IMX5_CLK_ECSPI2_PER_GATE>;
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<&clks IMX5_CLK_ECSPI2_PER_GATE>;
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clock-names = "ipg", "per";
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clock-names = "ipg", "per";
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status = "disabled";
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status = "disabled";
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};
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};
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@ -430,7 +430,7 @@
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reg = <0x63fb0000 0x4000>;
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reg = <0x63fb0000 0x4000>;
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interrupts = <6>;
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interrupts = <6>;
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clocks = <&clks IMX5_CLK_SDMA_GATE>,
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clocks = <&clks IMX5_CLK_SDMA_GATE>,
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<&clks IMX5_CLK_SDMA_GATE>;
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<&clks IMX5_CLK_SDMA_GATE>;
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clock-names = "ipg", "ahb";
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clock-names = "ipg", "ahb";
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fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
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fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
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};
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};
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@ -442,7 +442,7 @@
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reg = <0x63fc0000 0x4000>;
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reg = <0x63fc0000 0x4000>;
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interrupts = <38>;
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interrupts = <38>;
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clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
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clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
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<&clks IMX5_CLK_CSPI_IPG_GATE>;
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<&clks IMX5_CLK_CSPI_IPG_GATE>;
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clock-names = "ipg", "per";
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clock-names = "ipg", "per";
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status = "disabled";
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status = "disabled";
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};
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};
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@ -492,8 +492,8 @@
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reg = <0x63fec000 0x4000>;
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reg = <0x63fec000 0x4000>;
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interrupts = <87>;
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interrupts = <87>;
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clocks = <&clks IMX5_CLK_FEC_GATE>,
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clocks = <&clks IMX5_CLK_FEC_GATE>,
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<&clks IMX5_CLK_FEC_GATE>,
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<&clks IMX5_CLK_FEC_GATE>,
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<&clks IMX5_CLK_FEC_GATE>;
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<&clks IMX5_CLK_FEC_GATE>;
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clock-names = "ipg", "ahb", "ptp";
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clock-names = "ipg", "ahb", "ptp";
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status = "disabled";
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status = "disabled";
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};
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};
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@ -130,8 +130,8 @@
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reg = <0x40000000 0x20000000>;
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reg = <0x40000000 0x20000000>;
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interrupts = <11 10>;
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interrupts = <11 10>;
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clocks = <&clks IMX5_CLK_IPU_GATE>,
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clocks = <&clks IMX5_CLK_IPU_GATE>,
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<&clks IMX5_CLK_IPU_DI0_GATE>,
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<&clks IMX5_CLK_IPU_DI0_GATE>,
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<&clks IMX5_CLK_IPU_DI1_GATE>;
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<&clks IMX5_CLK_IPU_DI1_GATE>;
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clock-names = "bus", "di0", "di1";
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clock-names = "bus", "di0", "di1";
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resets = <&src 2>;
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resets = <&src 2>;
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@ -169,8 +169,8 @@
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reg = <0x70004000 0x4000>;
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reg = <0x70004000 0x4000>;
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interrupts = <1>;
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interrupts = <1>;
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clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
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clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_ESDHC1_PER_GATE>;
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<&clks IMX5_CLK_ESDHC1_PER_GATE>;
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clock-names = "ipg", "ahb", "per";
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clock-names = "ipg", "ahb", "per";
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status = "disabled";
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status = "disabled";
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};
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};
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@ -180,8 +180,8 @@
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reg = <0x70008000 0x4000>;
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reg = <0x70008000 0x4000>;
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interrupts = <2>;
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interrupts = <2>;
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clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
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clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_ESDHC2_PER_GATE>;
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<&clks IMX5_CLK_ESDHC2_PER_GATE>;
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clock-names = "ipg", "ahb", "per";
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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bus-width = <4>;
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status = "disabled";
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status = "disabled";
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reg = <0x7000c000 0x4000>;
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reg = <0x7000c000 0x4000>;
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interrupts = <33>;
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interrupts = <33>;
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clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
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clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
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<&clks IMX5_CLK_UART3_PER_GATE>;
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<&clks IMX5_CLK_UART3_PER_GATE>;
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clock-names = "ipg", "per";
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clock-names = "ipg", "per";
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status = "disabled";
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status = "disabled";
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};
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};
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reg = <0x70010000 0x4000>;
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reg = <0x70010000 0x4000>;
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interrupts = <36>;
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interrupts = <36>;
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clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
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clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
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<&clks IMX5_CLK_ECSPI1_PER_GATE>;
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<&clks IMX5_CLK_ECSPI1_PER_GATE>;
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clock-names = "ipg", "per";
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clock-names = "ipg", "per";
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status = "disabled";
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status = "disabled";
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};
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};
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reg = <0x70020000 0x4000>;
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reg = <0x70020000 0x4000>;
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interrupts = <3>;
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interrupts = <3>;
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clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
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clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_ESDHC3_PER_GATE>;
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<&clks IMX5_CLK_ESDHC3_PER_GATE>;
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clock-names = "ipg", "ahb", "per";
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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bus-width = <4>;
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status = "disabled";
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status = "disabled";
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reg = <0x70024000 0x4000>;
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reg = <0x70024000 0x4000>;
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interrupts = <4>;
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interrupts = <4>;
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clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
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clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_ESDHC4_PER_GATE>;
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<&clks IMX5_CLK_ESDHC4_PER_GATE>;
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clock-names = "ipg", "ahb", "per";
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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bus-width = <4>;
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status = "disabled";
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status = "disabled";
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reg = <0x73fa0000 0x4000>;
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reg = <0x73fa0000 0x4000>;
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interrupts = <39>;
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interrupts = <39>;
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clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
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clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
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<&clks IMX5_CLK_GPT_HF_GATE>;
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<&clks IMX5_CLK_GPT_HF_GATE>;
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clock-names = "ipg", "per";
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clock-names = "ipg", "per";
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};
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};
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compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
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compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
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reg = <0x73fb4000 0x4000>;
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reg = <0x73fb4000 0x4000>;
|
||||||
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_PWM1_HF_GATE>;
|
<&clks IMX5_CLK_PWM1_HF_GATE>;
|
||||||
clock-names = "ipg", "per";
|
clock-names = "ipg", "per";
|
||||||
interrupts = <61>;
|
interrupts = <61>;
|
||||||
};
|
};
|
||||||
|
@ -388,7 +388,7 @@
|
||||||
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
|
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
|
||||||
reg = <0x73fb8000 0x4000>;
|
reg = <0x73fb8000 0x4000>;
|
||||||
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_PWM2_HF_GATE>;
|
<&clks IMX5_CLK_PWM2_HF_GATE>;
|
||||||
clock-names = "ipg", "per";
|
clock-names = "ipg", "per";
|
||||||
interrupts = <94>;
|
interrupts = <94>;
|
||||||
};
|
};
|
||||||
|
@ -398,7 +398,7 @@
|
||||||
reg = <0x73fbc000 0x4000>;
|
reg = <0x73fbc000 0x4000>;
|
||||||
interrupts = <31>;
|
interrupts = <31>;
|
||||||
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_UART1_PER_GATE>;
|
<&clks IMX5_CLK_UART1_PER_GATE>;
|
||||||
clock-names = "ipg", "per";
|
clock-names = "ipg", "per";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
@ -408,7 +408,7 @@
|
||||||
reg = <0x73fc0000 0x4000>;
|
reg = <0x73fc0000 0x4000>;
|
||||||
interrupts = <32>;
|
interrupts = <32>;
|
||||||
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_UART2_PER_GATE>;
|
<&clks IMX5_CLK_UART2_PER_GATE>;
|
||||||
clock-names = "ipg", "per";
|
clock-names = "ipg", "per";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
@ -456,7 +456,7 @@
|
||||||
reg = <0x83fac000 0x4000>;
|
reg = <0x83fac000 0x4000>;
|
||||||
interrupts = <37>;
|
interrupts = <37>;
|
||||||
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
|
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
|
||||||
clock-names = "ipg", "per";
|
clock-names = "ipg", "per";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
@ -466,7 +466,7 @@
|
||||||
reg = <0x83fb0000 0x4000>;
|
reg = <0x83fb0000 0x4000>;
|
||||||
interrupts = <6>;
|
interrupts = <6>;
|
||||||
clocks = <&clks IMX5_CLK_SDMA_GATE>,
|
clocks = <&clks IMX5_CLK_SDMA_GATE>,
|
||||||
<&clks IMX5_CLK_SDMA_GATE>;
|
<&clks IMX5_CLK_SDMA_GATE>;
|
||||||
clock-names = "ipg", "ahb";
|
clock-names = "ipg", "ahb";
|
||||||
#dma-cells = <3>;
|
#dma-cells = <3>;
|
||||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
|
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
|
||||||
|
@ -479,7 +479,7 @@
|
||||||
reg = <0x83fc0000 0x4000>;
|
reg = <0x83fc0000 0x4000>;
|
||||||
interrupts = <38>;
|
interrupts = <38>;
|
||||||
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_CSPI_IPG_GATE>;
|
<&clks IMX5_CLK_CSPI_IPG_GATE>;
|
||||||
clock-names = "ipg", "per";
|
clock-names = "ipg", "per";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
@ -582,8 +582,8 @@
|
||||||
reg = <0x83fec000 0x4000>;
|
reg = <0x83fec000 0x4000>;
|
||||||
interrupts = <87>;
|
interrupts = <87>;
|
||||||
clocks = <&clks IMX5_CLK_FEC_GATE>,
|
clocks = <&clks IMX5_CLK_FEC_GATE>,
|
||||||
<&clks IMX5_CLK_FEC_GATE>,
|
<&clks IMX5_CLK_FEC_GATE>,
|
||||||
<&clks IMX5_CLK_FEC_GATE>;
|
<&clks IMX5_CLK_FEC_GATE>;
|
||||||
clock-names = "ipg", "ahb", "ptp";
|
clock-names = "ipg", "ahb", "ptp";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
|
@ -131,8 +131,8 @@
|
||||||
reg = <0x18000000 0x08000000>;
|
reg = <0x18000000 0x08000000>;
|
||||||
interrupts = <11 10>;
|
interrupts = <11 10>;
|
||||||
clocks = <&clks IMX5_CLK_IPU_GATE>,
|
clocks = <&clks IMX5_CLK_IPU_GATE>,
|
||||||
<&clks IMX5_CLK_IPU_DI0_GATE>,
|
<&clks IMX5_CLK_IPU_DI0_GATE>,
|
||||||
<&clks IMX5_CLK_IPU_DI1_GATE>;
|
<&clks IMX5_CLK_IPU_DI1_GATE>;
|
||||||
clock-names = "bus", "di0", "di1";
|
clock-names = "bus", "di0", "di1";
|
||||||
resets = <&src 2>;
|
resets = <&src 2>;
|
||||||
|
|
||||||
|
@ -199,8 +199,8 @@
|
||||||
reg = <0x50004000 0x4000>;
|
reg = <0x50004000 0x4000>;
|
||||||
interrupts = <1>;
|
interrupts = <1>;
|
||||||
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_DUMMY>,
|
<&clks IMX5_CLK_DUMMY>,
|
||||||
<&clks IMX5_CLK_ESDHC1_PER_GATE>;
|
<&clks IMX5_CLK_ESDHC1_PER_GATE>;
|
||||||
clock-names = "ipg", "ahb", "per";
|
clock-names = "ipg", "ahb", "per";
|
||||||
bus-width = <4>;
|
bus-width = <4>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
@ -211,8 +211,8 @@
|
||||||
reg = <0x50008000 0x4000>;
|
reg = <0x50008000 0x4000>;
|
||||||
interrupts = <2>;
|
interrupts = <2>;
|
||||||
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_DUMMY>,
|
<&clks IMX5_CLK_DUMMY>,
|
||||||
<&clks IMX5_CLK_ESDHC2_PER_GATE>;
|
<&clks IMX5_CLK_ESDHC2_PER_GATE>;
|
||||||
clock-names = "ipg", "ahb", "per";
|
clock-names = "ipg", "ahb", "per";
|
||||||
bus-width = <4>;
|
bus-width = <4>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
@ -223,7 +223,7 @@
|
||||||
reg = <0x5000c000 0x4000>;
|
reg = <0x5000c000 0x4000>;
|
||||||
interrupts = <33>;
|
interrupts = <33>;
|
||||||
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_UART3_PER_GATE>;
|
<&clks IMX5_CLK_UART3_PER_GATE>;
|
||||||
clock-names = "ipg", "per";
|
clock-names = "ipg", "per";
|
||||||
dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
|
dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
|
||||||
dma-names = "rx", "tx";
|
dma-names = "rx", "tx";
|
||||||
|
@ -237,7 +237,7 @@
|
||||||
reg = <0x50010000 0x4000>;
|
reg = <0x50010000 0x4000>;
|
||||||
interrupts = <36>;
|
interrupts = <36>;
|
||||||
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_ECSPI1_PER_GATE>;
|
<&clks IMX5_CLK_ECSPI1_PER_GATE>;
|
||||||
clock-names = "ipg", "per";
|
clock-names = "ipg", "per";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
@ -264,8 +264,8 @@
|
||||||
reg = <0x50020000 0x4000>;
|
reg = <0x50020000 0x4000>;
|
||||||
interrupts = <3>;
|
interrupts = <3>;
|
||||||
clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_DUMMY>,
|
<&clks IMX5_CLK_DUMMY>,
|
||||||
<&clks IMX5_CLK_ESDHC3_PER_GATE>;
|
<&clks IMX5_CLK_ESDHC3_PER_GATE>;
|
||||||
clock-names = "ipg", "ahb", "per";
|
clock-names = "ipg", "ahb", "per";
|
||||||
bus-width = <4>;
|
bus-width = <4>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
@ -276,8 +276,8 @@
|
||||||
reg = <0x50024000 0x4000>;
|
reg = <0x50024000 0x4000>;
|
||||||
interrupts = <4>;
|
interrupts = <4>;
|
||||||
clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_DUMMY>,
|
<&clks IMX5_CLK_DUMMY>,
|
||||||
<&clks IMX5_CLK_ESDHC4_PER_GATE>;
|
<&clks IMX5_CLK_ESDHC4_PER_GATE>;
|
||||||
clock-names = "ipg", "ahb", "per";
|
clock-names = "ipg", "ahb", "per";
|
||||||
bus-width = <4>;
|
bus-width = <4>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
@ -419,7 +419,7 @@
|
||||||
reg = <0x53fa0000 0x4000>;
|
reg = <0x53fa0000 0x4000>;
|
||||||
interrupts = <39>;
|
interrupts = <39>;
|
||||||
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_GPT_HF_GATE>;
|
<&clks IMX5_CLK_GPT_HF_GATE>;
|
||||||
clock-names = "ipg", "per";
|
clock-names = "ipg", "per";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -440,11 +440,11 @@
|
||||||
reg = <0x53fa8008 0x4>;
|
reg = <0x53fa8008 0x4>;
|
||||||
gpr = <&gpr>;
|
gpr = <&gpr>;
|
||||||
clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
|
clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
|
||||||
<&clks IMX5_CLK_LDB_DI1_SEL>,
|
<&clks IMX5_CLK_LDB_DI1_SEL>,
|
||||||
<&clks IMX5_CLK_IPU_DI0_SEL>,
|
<&clks IMX5_CLK_IPU_DI0_SEL>,
|
||||||
<&clks IMX5_CLK_IPU_DI1_SEL>,
|
<&clks IMX5_CLK_IPU_DI1_SEL>,
|
||||||
<&clks IMX5_CLK_LDB_DI0_GATE>,
|
<&clks IMX5_CLK_LDB_DI0_GATE>,
|
||||||
<&clks IMX5_CLK_LDB_DI1_GATE>;
|
<&clks IMX5_CLK_LDB_DI1_GATE>;
|
||||||
clock-names = "di0_pll", "di1_pll",
|
clock-names = "di0_pll", "di1_pll",
|
||||||
"di0_sel", "di1_sel",
|
"di0_sel", "di1_sel",
|
||||||
"di0", "di1";
|
"di0", "di1";
|
||||||
|
@ -486,7 +486,7 @@
|
||||||
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
|
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
|
||||||
reg = <0x53fb4000 0x4000>;
|
reg = <0x53fb4000 0x4000>;
|
||||||
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_PWM1_HF_GATE>;
|
<&clks IMX5_CLK_PWM1_HF_GATE>;
|
||||||
clock-names = "ipg", "per";
|
clock-names = "ipg", "per";
|
||||||
interrupts = <61>;
|
interrupts = <61>;
|
||||||
};
|
};
|
||||||
|
@ -496,7 +496,7 @@
|
||||||
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
|
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
|
||||||
reg = <0x53fb8000 0x4000>;
|
reg = <0x53fb8000 0x4000>;
|
||||||
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_PWM2_HF_GATE>;
|
<&clks IMX5_CLK_PWM2_HF_GATE>;
|
||||||
clock-names = "ipg", "per";
|
clock-names = "ipg", "per";
|
||||||
interrupts = <94>;
|
interrupts = <94>;
|
||||||
};
|
};
|
||||||
|
@ -506,7 +506,7 @@
|
||||||
reg = <0x53fbc000 0x4000>;
|
reg = <0x53fbc000 0x4000>;
|
||||||
interrupts = <31>;
|
interrupts = <31>;
|
||||||
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_UART1_PER_GATE>;
|
<&clks IMX5_CLK_UART1_PER_GATE>;
|
||||||
clock-names = "ipg", "per";
|
clock-names = "ipg", "per";
|
||||||
dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
|
dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
|
||||||
dma-names = "rx", "tx";
|
dma-names = "rx", "tx";
|
||||||
|
@ -518,7 +518,7 @@
|
||||||
reg = <0x53fc0000 0x4000>;
|
reg = <0x53fc0000 0x4000>;
|
||||||
interrupts = <32>;
|
interrupts = <32>;
|
||||||
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_UART2_PER_GATE>;
|
<&clks IMX5_CLK_UART2_PER_GATE>;
|
||||||
clock-names = "ipg", "per";
|
clock-names = "ipg", "per";
|
||||||
dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
|
dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
|
||||||
dma-names = "rx", "tx";
|
dma-names = "rx", "tx";
|
||||||
|
@ -530,7 +530,7 @@
|
||||||
reg = <0x53fc8000 0x4000>;
|
reg = <0x53fc8000 0x4000>;
|
||||||
interrupts = <82>;
|
interrupts = <82>;
|
||||||
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_CAN1_SERIAL_GATE>;
|
<&clks IMX5_CLK_CAN1_SERIAL_GATE>;
|
||||||
clock-names = "ipg", "per";
|
clock-names = "ipg", "per";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
@ -540,7 +540,7 @@
|
||||||
reg = <0x53fcc000 0x4000>;
|
reg = <0x53fcc000 0x4000>;
|
||||||
interrupts = <83>;
|
interrupts = <83>;
|
||||||
clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_CAN2_SERIAL_GATE>;
|
<&clks IMX5_CLK_CAN2_SERIAL_GATE>;
|
||||||
clock-names = "ipg", "per";
|
clock-names = "ipg", "per";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
@ -603,7 +603,7 @@
|
||||||
reg = <0x53ff0000 0x4000>;
|
reg = <0x53ff0000 0x4000>;
|
||||||
interrupts = <13>;
|
interrupts = <13>;
|
||||||
clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_UART4_PER_GATE>;
|
<&clks IMX5_CLK_UART4_PER_GATE>;
|
||||||
clock-names = "ipg", "per";
|
clock-names = "ipg", "per";
|
||||||
dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
|
dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
|
||||||
dma-names = "rx", "tx";
|
dma-names = "rx", "tx";
|
||||||
|
@ -635,7 +635,7 @@
|
||||||
reg = <0x63f90000 0x4000>;
|
reg = <0x63f90000 0x4000>;
|
||||||
interrupts = <86>;
|
interrupts = <86>;
|
||||||
clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_UART5_PER_GATE>;
|
<&clks IMX5_CLK_UART5_PER_GATE>;
|
||||||
clock-names = "ipg", "per";
|
clock-names = "ipg", "per";
|
||||||
dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
|
dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
|
||||||
dma-names = "rx", "tx";
|
dma-names = "rx", "tx";
|
||||||
|
@ -656,7 +656,7 @@
|
||||||
reg = <0x63fac000 0x4000>;
|
reg = <0x63fac000 0x4000>;
|
||||||
interrupts = <37>;
|
interrupts = <37>;
|
||||||
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
|
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
|
||||||
clock-names = "ipg", "per";
|
clock-names = "ipg", "per";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
@ -666,7 +666,7 @@
|
||||||
reg = <0x63fb0000 0x4000>;
|
reg = <0x63fb0000 0x4000>;
|
||||||
interrupts = <6>;
|
interrupts = <6>;
|
||||||
clocks = <&clks IMX5_CLK_SDMA_GATE>,
|
clocks = <&clks IMX5_CLK_SDMA_GATE>,
|
||||||
<&clks IMX5_CLK_SDMA_GATE>;
|
<&clks IMX5_CLK_SDMA_GATE>;
|
||||||
clock-names = "ipg", "ahb";
|
clock-names = "ipg", "ahb";
|
||||||
#dma-cells = <3>;
|
#dma-cells = <3>;
|
||||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||||
|
@ -679,7 +679,7 @@
|
||||||
reg = <0x63fc0000 0x4000>;
|
reg = <0x63fc0000 0x4000>;
|
||||||
interrupts = <38>;
|
interrupts = <38>;
|
||||||
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_CSPI_IPG_GATE>;
|
<&clks IMX5_CLK_CSPI_IPG_GATE>;
|
||||||
clock-names = "ipg", "per";
|
clock-names = "ipg", "per";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
@ -755,8 +755,8 @@
|
||||||
reg = <0x63fec000 0x4000>;
|
reg = <0x63fec000 0x4000>;
|
||||||
interrupts = <87>;
|
interrupts = <87>;
|
||||||
clocks = <&clks IMX5_CLK_FEC_GATE>,
|
clocks = <&clks IMX5_CLK_FEC_GATE>,
|
||||||
<&clks IMX5_CLK_FEC_GATE>,
|
<&clks IMX5_CLK_FEC_GATE>,
|
||||||
<&clks IMX5_CLK_FEC_GATE>;
|
<&clks IMX5_CLK_FEC_GATE>;
|
||||||
clock-names = "ipg", "ahb", "ptp";
|
clock-names = "ipg", "ahb", "ptp";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
@ -766,7 +766,7 @@
|
||||||
reg = <0x63ff0000 0x1000>;
|
reg = <0x63ff0000 0x1000>;
|
||||||
interrupts = <92>;
|
interrupts = <92>;
|
||||||
clocks = <&clks IMX5_CLK_TVE_GATE>,
|
clocks = <&clks IMX5_CLK_TVE_GATE>,
|
||||||
<&clks IMX5_CLK_IPU_DI1_SEL>;
|
<&clks IMX5_CLK_IPU_DI1_SEL>;
|
||||||
clock-names = "tve", "di_sel";
|
clock-names = "tve", "di_sel";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
||||||
|
@ -782,7 +782,7 @@
|
||||||
reg = <0x63ff4000 0x1000>;
|
reg = <0x63ff4000 0x1000>;
|
||||||
interrupts = <9>;
|
interrupts = <9>;
|
||||||
clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
|
clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
|
||||||
<&clks IMX5_CLK_VPU_GATE>;
|
<&clks IMX5_CLK_VPU_GATE>;
|
||||||
clock-names = "per", "ahb";
|
clock-names = "per", "ahb";
|
||||||
resets = <&src 1>;
|
resets = <&src 1>;
|
||||||
iram = <&ocram>;
|
iram = <&ocram>;
|
||||||
|
@ -793,7 +793,7 @@
|
||||||
reg = <0x63ff8000 0x4000>;
|
reg = <0x63ff8000 0x4000>;
|
||||||
interrupts = <19 20>;
|
interrupts = <19 20>;
|
||||||
clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
|
clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
|
||||||
<&clks IMX5_CLK_SAHARA_IPG_GATE>;
|
<&clks IMX5_CLK_SAHARA_IPG_GATE>;
|
||||||
clock-names = "ipg", "ahb";
|
clock-names = "ipg", "ahb";
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
@ -390,7 +390,7 @@
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */
|
||||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */
|
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */
|
||||||
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */
|
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */
|
||||||
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */
|
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */
|
||||||
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
||||||
>;
|
>;
|
||||||
|
|
|
@ -105,7 +105,7 @@
|
||||||
pixelclk-active = <1>;
|
pixelclk-active = <1>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
&can1 {
|
&can1 {
|
||||||
|
|
|
@ -199,7 +199,7 @@
|
||||||
pixelclk-active = <0>;
|
pixelclk-active = <0>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
&ipu1_di0_disp0 {
|
&ipu1_di0_disp0 {
|
||||||
|
|
|
@ -23,5 +23,5 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
&sata {
|
&sata {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
|
@ -105,7 +105,7 @@
|
||||||
pixelclk-active = <1>;
|
pixelclk-active = <1>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
&can1 {
|
&can1 {
|
||||||
|
|
|
@ -199,7 +199,7 @@
|
||||||
pixelclk-active = <0>;
|
pixelclk-active = <0>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
&ipu1_di0_disp0 {
|
&ipu1_di0_disp0 {
|
||||||
|
|
|
@ -105,7 +105,7 @@
|
||||||
pixelclk-active = <1>;
|
pixelclk-active = <1>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
&can1 {
|
&can1 {
|
||||||
|
|
|
@ -199,7 +199,7 @@
|
||||||
pixelclk-active = <0>;
|
pixelclk-active = <0>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
&ds1339 {
|
&ds1339 {
|
||||||
|
|
|
@ -192,10 +192,10 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
&i2c4 {
|
&i2c4 {
|
||||||
clock-frequency = <100000>;
|
clock-frequency = <100000>;
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&pinctrl_i2c4>;
|
pinctrl-0 = <&pinctrl_i2c4>;
|
||||||
status = "okay";
|
status = "okay";
|
||||||
|
|
||||||
codec: wm8962@1a {
|
codec: wm8962@1a {
|
||||||
compatible = "wlf,wm8962";
|
compatible = "wlf,wm8962";
|
||||||
|
|
|
@ -858,7 +858,7 @@
|
||||||
fsl,num-tx-queues=<3>;
|
fsl,num-tx-queues=<3>;
|
||||||
fsl,num-rx-queues=<3>;
|
fsl,num-rx-queues=<3>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
mlb: mlb@0218c000 {
|
mlb: mlb@0218c000 {
|
||||||
reg = <0x0218c000 0x4000>;
|
reg = <0x0218c000 0x4000>;
|
||||||
|
@ -1181,7 +1181,7 @@
|
||||||
fsl,adck-max-frequency = <30000000>, <40000000>,
|
fsl,adck-max-frequency = <30000000>, <40000000>,
|
||||||
<20000000>;
|
<20000000>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
adc2: adc@02284000 {
|
adc2: adc@02284000 {
|
||||||
compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
|
compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
|
||||||
|
@ -1192,7 +1192,7 @@
|
||||||
fsl,adck-max-frequency = <30000000>, <40000000>,
|
fsl,adck-max-frequency = <30000000>, <40000000>,
|
||||||
<20000000>;
|
<20000000>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
wdog3: wdog@02288000 {
|
wdog3: wdog@02288000 {
|
||||||
compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
|
compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
|
||||||
|
|
Loading…
Reference in a new issue