[PATCH] skge: gmac register access errors in dual port
Merge of four previous patches and the Kconfig fix * Remove debug printk's * whitespace cleanup and version number change * clear interrupts, reset phy, and reset hardware on shutdown * ignore 64bit counter overflow interrupts * fix a couple of places where second port could clobber state of first port. Signed-off-by: Stephen Hemminger <shemminger@osdl.org> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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@ -1951,7 +1951,7 @@ config SKGE
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---help---
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This driver support the Marvell Yukon or SysKonnect SK-98xx/SK-95xx
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and related Gigabit Ethernet adapters. It is a new smaller driver
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driver with better performance and more complete ethtool support.
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with better performance and more complete ethtool support.
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It does not support the link failover and network management
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features that "portable" vendor supplied sk98lin driver does.
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@ -42,7 +42,7 @@
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#include "skge.h"
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#define DRV_NAME "skge"
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#define DRV_VERSION "0.9"
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#define DRV_VERSION "1.0"
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#define PFX DRV_NAME " "
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#define DEFAULT_TX_RING_SIZE 128
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@ -669,7 +669,7 @@ static void skge_led(struct skge_port *skge, enum led_mode mode)
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PHY_M_LED_BLINK_RT(BLINK_84MS) |
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PHY_M_LEDC_TX_CTRL |
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PHY_M_LEDC_DP_CTRL);
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gm_phy_write(hw, port, PHY_MARV_LED_OVER,
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PHY_M_LED_MO_RX(MO_LED_OFF) |
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(skge->speed == SPEED_100 ?
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@ -876,7 +876,7 @@ static int skge_rx_fill(struct skge_port *skge)
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static void skge_link_up(struct skge_port *skge)
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{
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skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
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skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
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LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
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netif_carrier_on(skge->netdev);
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@ -987,6 +987,8 @@ static void genesis_reset(struct skge_hw *hw, int port)
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{
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const u8 zero[8] = { 0 };
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skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
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/* reset the statistics module */
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xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
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xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
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@ -1021,8 +1023,6 @@ static void bcom_check_link(struct skge_hw *hw, int port)
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(void) xm_phy_read(hw, port, PHY_BCOM_STAT);
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status = xm_phy_read(hw, port, PHY_BCOM_STAT);
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pr_debug("bcom_check_link status=0x%x\n", status);
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if ((status & PHY_ST_LSYNC) == 0) {
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u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
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cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
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@ -1106,8 +1106,6 @@ static void bcom_phy_init(struct skge_port *skge, int jumbo)
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{ 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
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};
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pr_debug("bcom_phy_init\n");
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/* read Id from external PHY (all have the same address) */
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id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
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@ -1340,6 +1338,8 @@ static void genesis_stop(struct skge_port *skge)
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int port = skge->port;
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u32 reg;
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genesis_reset(hw, port);
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/* Clear Tx packet arbiter timeout IRQ */
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skge_write16(hw, B3_PA_CTRL,
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port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
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@ -1465,7 +1465,6 @@ static void genesis_link_up(struct skge_port *skge)
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u16 cmd;
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u32 mode, msk;
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pr_debug("genesis_link_up\n");
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cmd = xm_read16(hw, port, XM_MMU_CMD);
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/*
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@ -1578,7 +1577,6 @@ static void yukon_init(struct skge_hw *hw, int port)
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struct skge_port *skge = netdev_priv(hw->dev[port]);
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u16 ctrl, ct1000, adv;
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pr_debug("yukon_init\n");
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if (skge->autoneg == AUTONEG_ENABLE) {
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u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
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@ -1677,9 +1675,11 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
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/* WA code for COMA mode -- set PHY reset */
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if (hw->chip_id == CHIP_ID_YUKON_LITE &&
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hw->chip_rev >= CHIP_REV_YU_LITE_A3)
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skge_write32(hw, B2_GP_IO,
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(skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));
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hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
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reg = skge_read32(hw, B2_GP_IO);
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reg |= GP_DIR_9 | GP_IO_9;
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skge_write32(hw, B2_GP_IO, reg);
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}
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/* hard reset */
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skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
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@ -1687,10 +1687,12 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
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/* WA code for COMA mode -- clear PHY reset */
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if (hw->chip_id == CHIP_ID_YUKON_LITE &&
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hw->chip_rev >= CHIP_REV_YU_LITE_A3)
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skge_write32(hw, B2_GP_IO,
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(skge_read32(hw, B2_GP_IO) | GP_DIR_9)
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& ~GP_IO_9);
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hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
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reg = skge_read32(hw, B2_GP_IO);
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reg |= GP_DIR_9;
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reg &= ~GP_IO_9;
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skge_write32(hw, B2_GP_IO, reg);
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}
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/* Set hardware config mode */
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reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
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@ -1729,7 +1731,7 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
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}
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gma_write16(hw, port, GM_GP_CTRL, reg);
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skge_read16(hw, GMAC_IRQ_SRC);
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skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
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yukon_init(hw, port);
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@ -1801,20 +1803,26 @@ static void yukon_stop(struct skge_port *skge)
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struct skge_hw *hw = skge->hw;
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int port = skge->port;
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if (hw->chip_id == CHIP_ID_YUKON_LITE &&
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hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
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skge_write32(hw, B2_GP_IO,
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skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9);
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}
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skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
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yukon_reset(hw, port);
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gma_write16(hw, port, GM_GP_CTRL,
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gma_read16(hw, port, GM_GP_CTRL)
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& ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
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gma_read16(hw, port, GM_GP_CTRL);
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if (hw->chip_id == CHIP_ID_YUKON_LITE &&
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hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
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u32 io = skge_read32(hw, B2_GP_IO);
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io |= GP_DIR_9 | GP_IO_9;
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skge_write32(hw, B2_GP_IO, io);
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skge_read32(hw, B2_GP_IO);
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}
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/* set GPHY Control reset */
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skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
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skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
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skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
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skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
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}
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static void yukon_get_stats(struct skge_port *skge, u64 *data)
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@ -1873,10 +1881,8 @@ static void yukon_link_up(struct skge_port *skge)
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int port = skge->port;
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u16 reg;
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pr_debug("yukon_link_up\n");
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/* Enable Transmit FIFO Underrun */
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skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK);
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skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
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reg = gma_read16(hw, port, GM_GP_CTRL);
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if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
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@ -1896,7 +1902,6 @@ static void yukon_link_down(struct skge_port *skge)
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int port = skge->port;
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u16 ctrl;
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pr_debug("yukon_link_down\n");
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gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
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ctrl = gma_read16(hw, port, GM_GP_CTRL);
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@ -2112,7 +2117,6 @@ static int skge_up(struct net_device *dev)
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skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
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skge_led(skge, LED_MODE_ON);
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pr_debug("skge_up completed\n");
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return 0;
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free_rx_ring:
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@ -2135,15 +2139,20 @@ static int skge_down(struct net_device *dev)
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netif_stop_queue(dev);
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skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
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if (hw->chip_id == CHIP_ID_GENESIS)
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genesis_stop(skge);
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else
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yukon_stop(skge);
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hw->intr_mask &= ~portirqmask[skge->port];
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skge_write32(hw, B0_IMSK, hw->intr_mask);
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/* Stop transmitter */
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skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
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skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
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RB_RST_SET|RB_DIS_OP_MD);
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if (hw->chip_id == CHIP_ID_GENESIS)
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genesis_stop(skge);
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else
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yukon_stop(skge);
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/* Disable Force Sync bit and Enable Alloc bit */
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skge_write8(hw, SK_REG(port, TXA_CTRL),
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@ -2367,8 +2376,6 @@ static void genesis_set_multicast(struct net_device *dev)
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u32 mode;
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u8 filter[8];
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pr_debug("genesis_set_multicast flags=%x count=%d\n", dev->flags, dev->mc_count);
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mode = xm_read32(hw, port, XM_MODE);
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mode |= XM_MD_ENA_HASH;
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if (dev->flags & IFF_PROMISC)
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@ -2530,8 +2537,6 @@ static int skge_poll(struct net_device *dev, int *budget)
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unsigned int to_do = min(dev->quota, *budget);
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unsigned int work_done = 0;
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pr_debug("skge_poll\n");
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for (e = ring->to_clean; work_done < to_do; e = e->next) {
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struct skge_rx_desc *rd = e->desc;
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struct sk_buff *skb;
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@ -2672,9 +2677,9 @@ static void skge_error_irq(struct skge_hw *hw)
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if (hw->chip_id == CHIP_ID_GENESIS) {
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/* clear xmac errors */
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if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
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skge_write16(hw, SK_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
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skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
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if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
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skge_write16(hw, SK_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
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skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
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} else {
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/* Timestamp (unused) overflow */
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if (hwstatus & IS_IRQ_TIST_OV)
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skge_write32(hw, B0_IMSK, hw->intr_mask);
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if (hw->chip_id != CHIP_ID_GENESIS)
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skge_write8(hw, GMAC_IRQ_MSK, 0);
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spin_lock_bh(&hw->phy_lock);
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for (i = 0; i < hw->ports; i++) {
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if (hw->chip_id == CHIP_ID_GENESIS)
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@ -3230,6 +3232,11 @@ static void __devexit skge_remove(struct pci_dev *pdev)
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dev0 = hw->dev[0];
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unregister_netdev(dev0);
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skge_write32(hw, B0_IMSK, 0);
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skge_write16(hw, B0_LED, LED_STAT_OFF);
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skge_pci_clear(hw);
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skge_write8(hw, B0_CTST, CS_RST_SET);
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tasklet_kill(&hw->ext_tasklet);
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free_irq(pdev->irq, hw);
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@ -3238,7 +3245,7 @@ static void __devexit skge_remove(struct pci_dev *pdev)
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if (dev1)
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free_netdev(dev1);
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free_netdev(dev0);
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skge_write16(hw, B0_LED, LED_STAT_OFF);
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iounmap(hw->regs);
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kfree(hw);
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pci_set_drvdata(pdev, NULL);
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@ -3257,7 +3264,10 @@ static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
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struct skge_port *skge = netdev_priv(dev);
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if (netif_running(dev)) {
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netif_carrier_off(dev);
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skge_down(dev);
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if (skge->wol)
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netif_stop_queue(dev);
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else
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skge_down(dev);
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}
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netif_device_detach(dev);
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wol |= skge->wol;
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@ -2008,7 +2008,7 @@ enum {
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GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
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GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
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#define GMAC_DEF_MSK (GM_IS_TX_CO_OV | GM_IS_RX_CO_OV | GM_IS_TX_FF_UR)
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#define GMAC_DEF_MSK (GM_IS_RX_FF_OR | GM_IS_TX_FF_UR)
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/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
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/* Bits 15.. 2: reserved */
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