drm/i915: Add setters for min/max frequency
Provide a standardized sysfs interface for setting min, and max frequencies. The code which reads the limits were lifted from the debugfs files. As a brief explanation, the limits are similar to the CPU p-states. We have 3 states: RP0 - ie. max frequency RP1 - ie. "preferred min" frequency RPn - seriously lowest frequency Initially Daniel asked me to clamp the writes to supported values, but in conforming to the way the cpufreq drivers seem to work, instead return -EINVAL (noticed by Jesse in discussion). The values can be used by userspace wishing to control the limits of the GPU (see the CC list for people who care). v4: Make exceeding the soft limits return -EINVAL as well (Daniel) v3: bug fix (Ben) - was passing the MHz value to gen6_set_rps instead of the step value. To fix, deal only with step values by doing the divide at the top. v2: add the dropped mutex_unlock in error cases (Chris) EINVAL on both too min, or too max (Daniel) v2 Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> CC: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -238,6 +238,45 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute
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return snprintf(buf, PAGE_SIZE, "%d", ret);
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}
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static ssize_t gt_max_freq_mhz_store(struct device *kdev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
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struct drm_device *dev = minor->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 val, rp_state_cap, hw_max, hw_min;
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ssize_t ret;
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ret = kstrtou32(buf, 0, &val);
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if (ret)
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return ret;
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val /= GT_FREQUENCY_MULTIPLIER;
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ret = mutex_lock_interruptible(&dev->struct_mutex);
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if (ret)
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return ret;
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rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
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hw_max = (rp_state_cap & 0xff);
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hw_min = ((rp_state_cap & 0xff0000) >> 16);
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if (val < hw_min || val > hw_max || val < dev_priv->rps.min_delay) {
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mutex_unlock(&dev->struct_mutex);
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return -EINVAL;
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}
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if (dev_priv->rps.cur_delay > val)
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gen6_set_rps(dev_priv->dev, val);
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dev_priv->rps.max_delay = val;
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mutex_unlock(&dev->struct_mutex);
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return count;
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}
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static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
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{
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struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
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@ -255,9 +294,49 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute
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return snprintf(buf, PAGE_SIZE, "%d", ret);
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}
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static ssize_t gt_min_freq_mhz_store(struct device *kdev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
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struct drm_device *dev = minor->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 val, rp_state_cap, hw_max, hw_min;
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ssize_t ret;
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ret = kstrtou32(buf, 0, &val);
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if (ret)
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return ret;
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val /= GT_FREQUENCY_MULTIPLIER;
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ret = mutex_lock_interruptible(&dev->struct_mutex);
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if (ret)
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return ret;
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rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
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hw_max = (rp_state_cap & 0xff);
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hw_min = ((rp_state_cap & 0xff0000) >> 16);
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if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) {
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mutex_unlock(&dev->struct_mutex);
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return -EINVAL;
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}
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if (dev_priv->rps.cur_delay < val)
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gen6_set_rps(dev_priv->dev, val);
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dev_priv->rps.min_delay = val;
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mutex_unlock(&dev->struct_mutex);
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return count;
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}
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static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
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static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, NULL);
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static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, NULL);
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static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
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static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
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static const struct attribute *gen6_attrs[] = {
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&dev_attr_gt_cur_freq_mhz.attr,
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