[media] fc2580: improve set params logic
Calculate PLL dividers slightly differently, most likely it is now correct. Move some register values to innitab. Use jiffies to poll filter lock. Fix logging. Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
This commit is contained in:
Antti Palosaari
Mauro Carvalho Chehab
parent
ef39830dda
commit
46de761572
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@ -33,11 +33,6 @@
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* fc2580_wr_regs()
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* fc2580_rd_regs()
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* could not be used for accessing more than one register at once.
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*
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* TODO:
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* Currently it blind writes bunch of static registers from the
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* fc2580_freq_regs_lut[] when fc2580_set_params() is called. Add some
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* logic to reduce unneeded register writes.
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*/
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/* write multiple registers */
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@ -137,107 +132,110 @@ static int fc2580_wr_reg_ff(struct fc2580_priv *priv, u8 reg, u8 val)
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return fc2580_wr_regs(priv, reg, &val, 1);
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}
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static int fc2580_set_params(struct dvb_frontend *fe)
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{
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struct fc2580_priv *priv = fe->tuner_priv;
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struct i2c_client *client = priv->client;
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struct dtv_frontend_properties *c = &fe->dtv_property_cache;
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int ret = 0, i;
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unsigned int r_val, n_val, k_val, k_val_reg, f_ref;
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u8 tmp_val, r18_val;
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int ret, i;
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unsigned int uitmp, div_ref, div_ref_val, div_n, k, k_cw, div_out;
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u64 f_vco;
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u8 u8tmp, synth_config;
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unsigned long timeout;
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/*
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* Fractional-N synthesizer/PLL.
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* Most likely all those PLL calculations are not correct. I am not
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* sure, but it looks like it is divider based Fractional-N synthesizer.
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* There is divider for reference clock too?
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* Anyhow, synthesizer calculation results seems to be quite correct.
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*/
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dev_dbg(&priv->i2c->dev, "%s: delivery_system=%d frequency=%d " \
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"bandwidth_hz=%d\n", __func__,
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c->delivery_system, c->frequency, c->bandwidth_hz);
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dev_dbg(&client->dev,
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"delivery_system=%u frequency=%u bandwidth_hz=%u\n",
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c->delivery_system, c->frequency, c->bandwidth_hz);
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 1);
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/* PLL */
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/*
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* Fractional-N synthesizer
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*
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* +---------------------------------------+
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* v |
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* Fref +----+ +----+ +-------+ +----+ +------+ +---+
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* ------> | /R | --> | PD | --> | VCO | ------> | /2 | --> | /N.F | <-- | K |
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* +----+ +----+ +-------+ +----+ +------+ +---+
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* |
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* |
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* v
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* +-------+ Fout
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* | /Rout | ------>
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* +-------+
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*/
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for (i = 0; i < ARRAY_SIZE(fc2580_pll_lut); i++) {
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if (c->frequency <= fc2580_pll_lut[i].freq)
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break;
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}
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if (i == ARRAY_SIZE(fc2580_pll_lut))
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if (i == ARRAY_SIZE(fc2580_pll_lut)) {
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ret = -EINVAL;
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goto err;
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}
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f_vco = c->frequency;
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f_vco *= fc2580_pll_lut[i].div;
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if (f_vco >= 2600000000UL)
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tmp_val = 0x0e | fc2580_pll_lut[i].band;
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#define DIV_PRE_N 2
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#define F_REF priv->clk
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div_out = fc2580_pll_lut[i].div_out;
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f_vco = (u64) c->frequency * div_out;
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synth_config = fc2580_pll_lut[i].band;
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if (f_vco < 2600000000ULL)
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synth_config |= 0x06;
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else
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tmp_val = 0x06 | fc2580_pll_lut[i].band;
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synth_config |= 0x0e;
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ret = fc2580_wr_reg(priv, 0x02, tmp_val);
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if (ret < 0)
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goto err;
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if (f_vco >= 2UL * 76 * priv->clk) {
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r_val = 1;
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r18_val = 0x00;
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} else if (f_vco >= 1UL * 76 * priv->clk) {
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r_val = 2;
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r18_val = 0x10;
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/* select reference divider R (keep PLL div N in valid range) */
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#define DIV_N_MIN 76
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if (f_vco >= div_u64((u64) DIV_PRE_N * DIV_N_MIN * F_REF, 1)) {
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div_ref = 1;
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div_ref_val = 0x00;
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} else if (f_vco >= div_u64((u64) DIV_PRE_N * DIV_N_MIN * F_REF, 2)) {
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div_ref = 2;
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div_ref_val = 0x10;
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} else {
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r_val = 4;
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r18_val = 0x20;
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div_ref = 4;
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div_ref_val = 0x20;
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}
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f_ref = 2UL * priv->clk / r_val;
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n_val = div_u64_rem(f_vco, f_ref, &k_val);
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k_val_reg = div_u64(1ULL * k_val * (1 << 20), f_ref);
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/* calculate PLL integer and fractional control word */
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uitmp = DIV_PRE_N * F_REF / div_ref;
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div_n = div_u64_rem(f_vco, uitmp, &k);
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k_cw = div_u64((u64) k * 0x100000, uitmp);
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ret = fc2580_wr_reg(priv, 0x18, r18_val | ((k_val_reg >> 16) & 0xff));
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dev_dbg(&client->dev,
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"frequency=%u f_vco=%llu F_REF=%u div_ref=%u div_n=%u k=%u div_out=%u k_cw=%0x\n",
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c->frequency, f_vco, F_REF, div_ref, div_n, k, div_out, k_cw);
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ret = fc2580_wr_reg(priv, 0x02, synth_config);
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if (ret < 0)
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goto err;
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ret = fc2580_wr_reg(priv, 0x1a, (k_val_reg >> 8) & 0xff);
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ret = fc2580_wr_reg(priv, 0x18, div_ref_val << 0 | k_cw >> 16);
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if (ret < 0)
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goto err;
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ret = fc2580_wr_reg(priv, 0x1b, (k_val_reg >> 0) & 0xff);
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ret = fc2580_wr_reg(priv, 0x1a, (k_cw >> 8) & 0xff);
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if (ret < 0)
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goto err;
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ret = fc2580_wr_reg(priv, 0x1c, n_val);
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ret = fc2580_wr_reg(priv, 0x1b, (k_cw >> 0) & 0xff);
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if (ret < 0)
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goto err;
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if (priv->clk >= 28000000) {
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ret = fc2580_wr_reg(priv, 0x4b, 0x22);
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if (ret < 0)
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goto err;
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}
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if (fc2580_pll_lut[i].band == 0x00) {
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if (c->frequency <= 794000000)
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tmp_val = 0x9f;
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else
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tmp_val = 0x8f;
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ret = fc2580_wr_reg(priv, 0x2d, tmp_val);
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if (ret < 0)
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goto err;
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}
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ret = fc2580_wr_reg(priv, 0x1c, div_n);
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if (ret < 0)
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goto err;
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/* registers */
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for (i = 0; i < ARRAY_SIZE(fc2580_freq_regs_lut); i++) {
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if (c->frequency <= fc2580_freq_regs_lut[i].freq)
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break;
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}
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if (i == ARRAY_SIZE(fc2580_freq_regs_lut))
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if (i == ARRAY_SIZE(fc2580_freq_regs_lut)) {
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ret = -EINVAL;
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goto err;
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}
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ret = fc2580_wr_reg_ff(priv, 0x25, fc2580_freq_regs_lut[i].r25_val);
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if (ret < 0)
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@ -340,16 +338,18 @@ static int fc2580_set_params(struct dvb_frontend *fe)
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if (c->bandwidth_hz <= fc2580_if_filter_lut[i].freq)
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break;
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}
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if (i == ARRAY_SIZE(fc2580_if_filter_lut))
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if (i == ARRAY_SIZE(fc2580_if_filter_lut)) {
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ret = -EINVAL;
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goto err;
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}
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ret = fc2580_wr_reg(priv, 0x36, fc2580_if_filter_lut[i].r36_val);
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if (ret < 0)
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goto err;
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ret = fc2580_wr_reg(priv, 0x37, div_u64(1ULL * priv->clk *
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fc2580_if_filter_lut[i].mul, 1000000000));
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u8tmp = div_u64((u64) priv->clk * fc2580_if_filter_lut[i].mul,
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1000000000);
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ret = fc2580_wr_reg(priv, 0x37, u8tmp);
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if (ret < 0)
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goto err;
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@ -357,36 +357,25 @@ static int fc2580_set_params(struct dvb_frontend *fe)
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if (ret < 0)
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goto err;
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/* calibration? */
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ret = fc2580_wr_reg(priv, 0x2e, 0x09);
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if (ret < 0)
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goto err;
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for (i = 0; i < 5; i++) {
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ret = fc2580_rd_reg(priv, 0x2f, &tmp_val);
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if (ret < 0)
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timeout = jiffies + msecs_to_jiffies(30);
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for (uitmp = ~0xc0; !time_after(jiffies, timeout) && uitmp != 0xc0;) {
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/* trigger filter */
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ret = fc2580_wr_reg(priv, 0x2e, 0x09);
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if (ret)
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goto err;
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/* done when [7:6] are set */
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if ((tmp_val & 0xc0) == 0xc0)
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break;
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/* locked when [7:6] are set (val: d7 6MHz, d5 7MHz, cd 8MHz) */
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ret = fc2580_rd_reg(priv, 0x2f, &u8tmp);
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if (ret)
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goto err;
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uitmp = u8tmp & 0xc0;
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ret = fc2580_wr_reg(priv, 0x2e, 0x01);
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if (ret < 0)
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if (ret)
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goto err;
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ret = fc2580_wr_reg(priv, 0x2e, 0x09);
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if (ret < 0)
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goto err;
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usleep_range(5000, 25000);
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}
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dev_dbg(&priv->i2c->dev, "%s: loop=%i\n", __func__, i);
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ret = fc2580_wr_reg(priv, 0x2e, 0x01);
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if (ret < 0)
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goto err;
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if (uitmp != 0xc0)
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dev_dbg(&client->dev, "filter did not lock %02x\n", uitmp);
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0);
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@ -396,7 +385,7 @@ err:
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0);
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dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
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dev_dbg(&client->dev, "failed=%d\n", ret);
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return ret;
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}
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@ -50,7 +50,7 @@ static const struct fc2580_reg_val fc2580_init_reg_vals[] = {
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struct fc2580_pll {
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u32 freq;
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u8 div;
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u8 div_out;
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u8 band;
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};
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@ -110,15 +110,15 @@ static const struct fc2580_freq_regs fc2580_freq_regs_lut[] = {
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0x50, 0x0f, 0x07, 0x00, 0x15, 0x03, 0x05, 0x10, 0x12, 0x08,
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0x0a, 0x78, 0x32, 0x54},
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{ 538000000,
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0xf0, 0x77, 0x53, 0x60, 0xff, 0xff, 0xff, 0x09, 0xff, 0x8c,
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0xf0, 0x77, 0x53, 0x60, 0xff, 0xff, 0x9f, 0x09, 0xff, 0x8c,
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0x50, 0x13, 0x07, 0x06, 0x15, 0x06, 0x08, 0x10, 0x12, 0x0b,
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0x0c, 0x78, 0x32, 0x14},
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{ 794000000,
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0xf0, 0x77, 0x53, 0x60, 0xff, 0xff, 0xff, 0x09, 0xff, 0x8c,
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0xf0, 0x77, 0x53, 0x60, 0xff, 0xff, 0x9f, 0x09, 0xff, 0x8c,
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0x50, 0x15, 0x03, 0x03, 0x15, 0x03, 0x05, 0x0c, 0x0e, 0x0b,
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0x0c, 0x78, 0x32, 0x14},
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{1000000000,
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0xf0, 0x77, 0x53, 0x60, 0xff, 0xff, 0xff, 0x09, 0xff, 0x8c,
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0xf0, 0x77, 0x53, 0x60, 0xff, 0xff, 0x8f, 0x09, 0xff, 0x8c,
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0x50, 0x15, 0x07, 0x06, 0x15, 0x07, 0x09, 0x10, 0x12, 0x0b,
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0x0c, 0x78, 0x32, 0x14},
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{0xffffffff,
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