spi-atmel: support inter-word delay
If the SPI slave requires an inter-word delay, configure the DLYBCT register accordingly. Tested on a SAMA5D2 board (derived from SAMA5D2-Xplained reference board). Signed-off-by: Jonas Bonn <jonas@norrbonn.se> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> CC: Nicolas Ferre <nicolas.ferre@microchip.com> CC: Mark Brown <broonie@kernel.org> CC: Alexandre Belloni <alexandre.belloni@bootlin.com> CC: Ludovic Desroches <ludovic.desroches@microchip.com> CC: linux-spi@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -1201,13 +1201,14 @@ static int atmel_spi_setup(struct spi_device *spi)
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csr |= SPI_BIT(CSAAT);
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/* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
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*
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* DLYBCT would add delays between words, slowing down transfers.
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* It could potentially be useful to cope with DMA bottlenecks, but
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* in those cases it's probably best to just use a lower bitrate.
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*/
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csr |= SPI_BF(DLYBS, 0);
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csr |= SPI_BF(DLYBCT, 0);
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/* DLYBCT adds delays between words. This is useful for slow devices
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* that need a bit of time to setup the next transfer.
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*/
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csr |= SPI_BF(DLYBCT,
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(as->spi_clk / 1000000 * spi->word_delay_usecs) >> 5);
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asd = spi->controller_state;
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if (!asd) {
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