PCI: dra7xx: Add TI DRA7xx PCIe driver
Add support for PCIe controller in DRA7xx. This driver re-uses the designware core code that is already present in kernel. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Cc: Mohit Kumar <mohit.kumar@st.com> Cc: Marek Vasut <marex@denx.de> Cc: Arnd Bergmann <arnd@arndb.de>
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59
Documentation/devicetree/bindings/pci/ti-pci.txt
Normal file
59
Documentation/devicetree/bindings/pci/ti-pci.txt
Normal file
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@ -0,0 +1,59 @@
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TI PCI Controllers
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PCIe Designware Controller
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- compatible: Should be "ti,dra7-pcie""
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- reg : Two register ranges as listed in the reg-names property
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- reg-names : The first entry must be "ti-conf" for the TI specific registers
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The second entry must be "rc-dbics" for the designware pcie
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registers
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The third entry must be "config" for the PCIe configuration space
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- phys : list of PHY specifiers (used by generic PHY framework)
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- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
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number of PHYs as specified in *phys* property.
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- ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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where <X> is the instance number of the pcie from the HW spec.
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- interrupts : Two interrupt entries must be specified. The first one is for
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main interrupt line and the second for MSI interrupt line.
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- #address-cells,
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#size-cells,
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#interrupt-cells,
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device_type,
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ranges,
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num-lanes,
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interrupt-map-mask,
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interrupt-map : as specified in ../designware-pcie.txt
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Example:
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axi {
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compatible = "simple-bus";
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#size-cells = <1>;
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#address-cells = <1>;
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ranges = <0x51000000 0x51000000 0x3000
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0x0 0x20000000 0x10000000>;
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pcie@51000000 {
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compatible = "ti,dra7-pcie";
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reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
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reg-names = "rc_dbics", "ti_conf", "config";
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interrupts = <0 232 0x4>, <0 233 0x4>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x81000000 0 0 0x03000 0 0x00010000
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0x82000000 0 0x20013000 0x13000 0 0xffed000>;
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#interrupt-cells = <1>;
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num-lanes = <1>;
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ti,hwmods = "pcie1";
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phys = <&pcie1_phy>;
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phy-names = "pcie-phy0";
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 1>,
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<0 0 0 2 &pcie_intc 2>,
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<0 0 0 3 &pcie_intc 3>,
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<0 0 0 4 &pcie_intc 4>;
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pcie_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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};
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@ -6796,6 +6796,14 @@ S: Supported
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F: Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
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F: drivers/pci/host/pci-tegra.c
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PCI DRIVER FOR TI DRA7XX
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M: Kishon Vijay Abraham I <kishon@ti.com>
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L: linux-omap@vger.kernel.org
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L: linux-pci@vger.kernel.org
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S: Supported
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F: Documentation/devicetree/bindings/pci/ti-pci.txt
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F: drivers/pci/host/pci-dra7xx.c
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PCI DRIVER FOR RENESAS R-CAR
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M: Simon Horman <horms@verge.net.au>
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L: linux-pci@vger.kernel.org
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@ -1,6 +1,15 @@
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menu "PCI host controller drivers"
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depends on PCI
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config PCI_DRA7XX
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bool "TI DRA7xx PCIe controller"
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select PCIE_DW
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depends on OF && HAS_IOMEM && TI_PIPE3
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help
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Enables support for the PCIe controller in the DRA7xx SoC. There
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are two instances of PCIe controller in DRA7xx. This controller can
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act both as EP and RC. This reuses the Designware core.
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config PCI_MVEBU
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bool "Marvell EBU PCIe controller"
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depends on ARCH_MVEBU || ARCH_DOVE || ARCH_KIRKWOOD
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@ -1,4 +1,5 @@
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obj-$(CONFIG_PCIE_DW) += pcie-designware.o
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obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
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obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
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obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
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obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
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458
drivers/pci/host/pci-dra7xx.c
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458
drivers/pci/host/pci-dra7xx.c
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/*
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* pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
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*
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* Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
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*
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* Authors: Kishon Vijay Abraham I <kishon@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/resource.h>
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#include <linux/types.h>
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#include "pcie-designware.h"
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/* PCIe controller wrapper DRA7XX configuration registers */
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#define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024
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#define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028
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#define ERR_SYS BIT(0)
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#define ERR_FATAL BIT(1)
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#define ERR_NONFATAL BIT(2)
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#define ERR_COR BIT(3)
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#define ERR_AXI BIT(4)
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#define ERR_ECRC BIT(5)
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#define PME_TURN_OFF BIT(8)
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#define PME_TO_ACK BIT(9)
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#define PM_PME BIT(10)
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#define LINK_REQ_RST BIT(11)
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#define LINK_UP_EVT BIT(12)
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#define CFG_BME_EVT BIT(13)
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#define CFG_MSE_EVT BIT(14)
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#define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
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ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
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LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)
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#define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034
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#define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038
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#define INTA BIT(0)
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#define INTB BIT(1)
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#define INTC BIT(2)
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#define INTD BIT(3)
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#define MSI BIT(4)
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#define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
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#define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
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#define LTSSM_EN 0x1
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#define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
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#define LINK_UP BIT(16)
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struct dra7xx_pcie {
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void __iomem *base;
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struct phy **phy;
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int phy_count;
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struct device *dev;
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struct pcie_port pp;
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};
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#define to_dra7xx_pcie(x) container_of((x), struct dra7xx_pcie, pp)
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static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
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{
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return readl(pcie->base + offset);
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}
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static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
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u32 value)
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{
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writel(value, pcie->base + offset);
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}
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static int dra7xx_pcie_link_up(struct pcie_port *pp)
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{
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
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u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
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return !!(reg & LINK_UP);
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}
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static int dra7xx_pcie_establish_link(struct pcie_port *pp)
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{
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u32 reg;
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unsigned int retries = 1000;
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
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if (dw_pcie_link_up(pp)) {
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dev_err(pp->dev, "link is already up\n");
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return 0;
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}
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reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
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reg |= LTSSM_EN;
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
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while (retries--) {
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reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
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if (reg & LINK_UP)
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break;
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usleep_range(10, 20);
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}
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if (retries == 0) {
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dev_err(pp->dev, "link is not up\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp)
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{
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
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~INTERRUPTS);
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dra7xx_pcie_writel(dra7xx,
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PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, INTERRUPTS);
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
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~LEG_EP_INTERRUPTS & ~MSI);
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if (IS_ENABLED(CONFIG_PCI_MSI))
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dra7xx_pcie_writel(dra7xx,
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PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, MSI);
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else
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dra7xx_pcie_writel(dra7xx,
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PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
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LEG_EP_INTERRUPTS);
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}
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static void dra7xx_pcie_host_init(struct pcie_port *pp)
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{
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dw_pcie_setup_rc(pp);
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dra7xx_pcie_establish_link(pp);
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if (IS_ENABLED(CONFIG_PCI_MSI))
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dw_pcie_msi_init(pp);
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dra7xx_pcie_enable_interrupts(pp);
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}
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static struct pcie_host_ops dra7xx_pcie_host_ops = {
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.link_up = dra7xx_pcie_link_up,
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.host_init = dra7xx_pcie_host_init,
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};
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static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
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irq_set_chip_data(irq, domain->host_data);
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set_irq_flags(irq, IRQF_VALID);
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return 0;
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}
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static const struct irq_domain_ops intx_domain_ops = {
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.map = dra7xx_pcie_intx_map,
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};
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static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
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{
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struct device *dev = pp->dev;
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struct device_node *node = dev->of_node;
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struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
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if (!pcie_intc_node) {
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dev_err(dev, "No PCIe Intc node found\n");
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return PTR_ERR(pcie_intc_node);
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}
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pp->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
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&intx_domain_ops, pp);
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if (!pp->irq_domain) {
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dev_err(dev, "Failed to get a INTx IRQ domain\n");
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return PTR_ERR(pp->irq_domain);
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}
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return 0;
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}
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static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
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{
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struct pcie_port *pp = arg;
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
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u32 reg;
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reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
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switch (reg) {
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case MSI:
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dw_handle_msi_irq(pp);
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break;
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case INTA:
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case INTB:
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case INTC:
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case INTD:
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generic_handle_irq(irq_find_mapping(pp->irq_domain, ffs(reg)));
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break;
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}
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
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return IRQ_HANDLED;
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}
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static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
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{
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struct dra7xx_pcie *dra7xx = arg;
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u32 reg;
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reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
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if (reg & ERR_SYS)
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dev_dbg(dra7xx->dev, "System Error\n");
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if (reg & ERR_FATAL)
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dev_dbg(dra7xx->dev, "Fatal Error\n");
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if (reg & ERR_NONFATAL)
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dev_dbg(dra7xx->dev, "Non Fatal Error\n");
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if (reg & ERR_COR)
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dev_dbg(dra7xx->dev, "Correctable Error\n");
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if (reg & ERR_AXI)
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dev_dbg(dra7xx->dev, "AXI tag lookup fatal Error\n");
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if (reg & ERR_ECRC)
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dev_dbg(dra7xx->dev, "ECRC Error\n");
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if (reg & PME_TURN_OFF)
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dev_dbg(dra7xx->dev,
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"Power Management Event Turn-Off message received\n");
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if (reg & PME_TO_ACK)
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dev_dbg(dra7xx->dev,
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"Power Management Turn-Off Ack message received\n");
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if (reg & PM_PME)
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dev_dbg(dra7xx->dev,
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"PM Power Management Event message received\n");
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if (reg & LINK_REQ_RST)
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dev_dbg(dra7xx->dev, "Link Request Reset\n");
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if (reg & LINK_UP_EVT)
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dev_dbg(dra7xx->dev, "Link-up state change\n");
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if (reg & CFG_BME_EVT)
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dev_dbg(dra7xx->dev, "CFG 'Bus Master Enable' change\n");
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if (reg & CFG_MSE_EVT)
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dev_dbg(dra7xx->dev, "CFG 'Memory Space Enable' change\n");
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
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return IRQ_HANDLED;
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}
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static int add_pcie_port(struct dra7xx_pcie *dra7xx,
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struct platform_device *pdev)
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{
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int ret;
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struct pcie_port *pp;
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struct resource *res;
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struct device *dev = &pdev->dev;
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pp = &dra7xx->pp;
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pp->dev = dev;
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pp->ops = &dra7xx_pcie_host_ops;
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pp->irq = platform_get_irq(pdev, 1);
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if (pp->irq < 0) {
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dev_err(dev, "missing IRQ resource\n");
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return -EINVAL;
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}
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ret = devm_request_irq(&pdev->dev, pp->irq,
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dra7xx_pcie_msi_irq_handler, IRQF_SHARED,
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"dra7-pcie-msi", pp);
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if (ret) {
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dev_err(&pdev->dev, "failed to request irq\n");
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return ret;
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}
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if (!IS_ENABLED(CONFIG_PCI_MSI)) {
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ret = dra7xx_pcie_init_irq_domain(pp);
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if (ret < 0)
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return ret;
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
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pp->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
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if (!pp->dbi_base)
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return -ENOMEM;
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ret = dw_pcie_host_init(pp);
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if (ret) {
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dev_err(dra7xx->dev, "failed to initialize host\n");
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return ret;
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}
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return 0;
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}
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static int __init dra7xx_pcie_probe(struct platform_device *pdev)
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{
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u32 reg;
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int ret;
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int irq;
|
||||
int i;
|
||||
int phy_count;
|
||||
struct phy **phy;
|
||||
void __iomem *base;
|
||||
struct resource *res;
|
||||
struct dra7xx_pcie *dra7xx;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
char name[10];
|
||||
|
||||
dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
|
||||
if (!dra7xx)
|
||||
return -ENOMEM;
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(dev, "missing IRQ resource\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
|
||||
IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to request irq\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
|
||||
base = devm_ioremap_nocache(dev, res->start, resource_size(res));
|
||||
if (!base)
|
||||
return -ENOMEM;
|
||||
|
||||
phy_count = of_property_count_strings(np, "phy-names");
|
||||
if (phy_count < 0) {
|
||||
dev_err(dev, "unable to find the strings\n");
|
||||
return phy_count;
|
||||
}
|
||||
|
||||
phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
|
||||
if (!phy)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < phy_count; i++) {
|
||||
snprintf(name, sizeof(name), "pcie-phy%d", i);
|
||||
phy[i] = devm_phy_get(dev, name);
|
||||
if (IS_ERR(phy[i]))
|
||||
return PTR_ERR(phy[i]);
|
||||
|
||||
ret = phy_init(phy[i]);
|
||||
if (ret < 0)
|
||||
goto err_phy;
|
||||
|
||||
ret = phy_power_on(phy[i]);
|
||||
if (ret < 0) {
|
||||
phy_exit(phy[i]);
|
||||
goto err_phy;
|
||||
}
|
||||
}
|
||||
|
||||
dra7xx->base = base;
|
||||
dra7xx->phy = phy;
|
||||
dra7xx->dev = dev;
|
||||
dra7xx->phy_count = phy_count;
|
||||
|
||||
pm_runtime_enable(dev);
|
||||
ret = pm_runtime_get_sync(dev);
|
||||
if (IS_ERR_VALUE(ret)) {
|
||||
dev_err(dev, "pm_runtime_get_sync failed\n");
|
||||
goto err_phy;
|
||||
}
|
||||
|
||||
reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
|
||||
reg &= ~LTSSM_EN;
|
||||
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
|
||||
|
||||
platform_set_drvdata(pdev, dra7xx);
|
||||
|
||||
ret = add_pcie_port(dra7xx, pdev);
|
||||
if (ret < 0)
|
||||
goto err_add_port;
|
||||
|
||||
return 0;
|
||||
|
||||
err_add_port:
|
||||
pm_runtime_put(dev);
|
||||
pm_runtime_disable(dev);
|
||||
|
||||
err_phy:
|
||||
while (--i >= 0) {
|
||||
phy_power_off(phy[i]);
|
||||
phy_exit(phy[i]);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __exit dra7xx_pcie_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct dra7xx_pcie *dra7xx = platform_get_drvdata(pdev);
|
||||
struct pcie_port *pp = &dra7xx->pp;
|
||||
struct device *dev = &pdev->dev;
|
||||
int count = dra7xx->phy_count;
|
||||
|
||||
if (pp->irq_domain)
|
||||
irq_domain_remove(pp->irq_domain);
|
||||
pm_runtime_put(dev);
|
||||
pm_runtime_disable(dev);
|
||||
while (count--) {
|
||||
phy_power_off(dra7xx->phy[count]);
|
||||
phy_exit(dra7xx->phy[count]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_dra7xx_pcie_match[] = {
|
||||
{ .compatible = "ti,dra7-pcie", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, of_dra7xx_pcie_match);
|
||||
|
||||
static struct platform_driver dra7xx_pcie_driver = {
|
||||
.remove = __exit_p(dra7xx_pcie_remove),
|
||||
.driver = {
|
||||
.name = "dra7-pcie",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_dra7xx_pcie_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);
|
||||
|
||||
MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
|
||||
MODULE_DESCRIPTION("TI PCIe controller driver");
|
||||
MODULE_LICENSE("GPL v2");
|
Loading…
Reference in a new issue