Revert "i2c: designware: detect when dynamic tar update is possible"
commit12688dc21f
upstream. This reverts commit63d0f0a695
. It caused a regression on platforms where I2C controller is synthesized with dynamic TAR update disabled. Detection code is testing is bit DW_IC_CON_10BITADDR_MASTER in register DW_IC_CON read-only but fails to restore original value in case bit is read-write. Instead of fixing this we revert the commit since it was preparation for the commit0317e6c0f1
("i2c: designware: do not disable adapter after transfer") which was also reverted. Reported-by: Shah Nehal-Bakulchandra <Nehal-bakulchandra.Shah@amd.com> Reported-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Acked-By: Lucas De Marchi <lucas.demarchi@intel.com> Fixes:63d0f0a695
("i2c: designware: detect when dynamic tar update is possible") Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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17c4434214
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48a4158278
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@ -475,30 +475,28 @@ static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
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static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
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{
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struct i2c_msg *msgs = dev->msgs;
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u32 ic_tar = 0;
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u32 ic_con, ic_tar = 0;
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/* Disable the adapter */
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__i2c_dw_enable_and_wait(dev, false);
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/* if the slave address is ten bit address, enable 10BITADDR */
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if (dev->dynamic_tar_update_enabled) {
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ic_con = dw_readl(dev, DW_IC_CON);
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if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
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ic_con |= DW_IC_CON_10BITADDR_MASTER;
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/*
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* If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
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* mode has to be enabled via bit 12 of IC_TAR register,
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* otherwise bit 4 of IC_CON is used.
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* mode has to be enabled via bit 12 of IC_TAR register.
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* We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
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* detected from registers.
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*/
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if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
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ic_tar = DW_IC_TAR_10BITADDR_MASTER;
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ic_tar = DW_IC_TAR_10BITADDR_MASTER;
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} else {
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u32 ic_con = dw_readl(dev, DW_IC_CON);
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if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
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ic_con |= DW_IC_CON_10BITADDR_MASTER;
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else
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ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
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dw_writel(dev, ic_con, DW_IC_CON);
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ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
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}
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dw_writel(dev, ic_con, DW_IC_CON);
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/*
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* Set the slave (target) address and enable 10-bit addressing mode
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* if applicable.
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@ -923,7 +921,6 @@ int i2c_dw_probe(struct dw_i2c_dev *dev)
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{
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struct i2c_adapter *adap = &dev->adapter;
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int r;
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u32 reg;
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init_completion(&dev->cmd_complete);
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@ -931,26 +928,6 @@ int i2c_dw_probe(struct dw_i2c_dev *dev)
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if (r)
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return r;
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r = i2c_dw_acquire_lock(dev);
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if (r)
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return r;
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/*
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* Test if dynamic TAR update is enabled in this controller by writing
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* to IC_10BITADDR_MASTER field in IC_CON: when it is enabled this
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* field is read-only so it should not succeed
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*/
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reg = dw_readl(dev, DW_IC_CON);
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dw_writel(dev, reg ^ DW_IC_CON_10BITADDR_MASTER, DW_IC_CON);
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if ((dw_readl(dev, DW_IC_CON) & DW_IC_CON_10BITADDR_MASTER) ==
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(reg & DW_IC_CON_10BITADDR_MASTER)) {
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dev->dynamic_tar_update_enabled = true;
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dev_dbg(dev->dev, "Dynamic TAR update enabled");
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}
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i2c_dw_release_lock(dev);
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snprintf(adap->name, sizeof(adap->name),
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"Synopsys DesignWare I2C adapter");
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adap->retries = 3;
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@ -117,7 +117,6 @@ struct dw_i2c_dev {
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int (*acquire_lock)(struct dw_i2c_dev *dev);
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void (*release_lock)(struct dw_i2c_dev *dev);
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bool pm_runtime_disabled;
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bool dynamic_tar_update_enabled;
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};
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#define ACCESS_SWAP 0x00000001
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