Revert "MIPS: Allow ASID size to be determined at boot time."
This reverts commit d532f3d267
.
The original commit has several problems:
1) Doesn't work with 64-bit kernels.
2) Calls TLBMISS_HANDLER_SETUP() before the code is generated.
3) Calls TLBMISS_HANDLER_SETUP() twice in per_cpu_trap_init() when
only one call is needed.
[ralf@linux-mips.org: Also revert the bits of the ASID patch which were
hidden in the KVM merge.]
Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: "Steven J. Hill" <Steven.Hill@imgtec.com>
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/5242/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
parent
8ea6cd7af1
commit
48c4ac976a
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@ -336,7 +336,7 @@ enum emulation_result {
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#define VPN2_MASK 0xffffe000
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#define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && ((x).tlb_lo1 & MIPS3_PG_G))
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#define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
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#define TLB_ASID(x) (ASID_MASK((x).tlb_hi))
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#define TLB_ASID(x) ((x).tlb_hi & ASID_MASK)
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#define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) ? ((x).tlb_lo1 & MIPS3_PG_V) : ((x).tlb_lo0 & MIPS3_PG_V))
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struct kvm_mips_tlb {
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@ -67,68 +67,45 @@ extern unsigned long pgd_current[];
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TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
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#endif
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#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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#define ASID_INC(asid) \
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({ \
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unsigned long __asid = asid; \
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__asm__("1:\taddiu\t%0,1\t\t\t\t# patched\n\t" \
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".section\t__asid_inc,\"a\"\n\t" \
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".word\t1b\n\t" \
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".previous" \
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:"=r" (__asid) \
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:"0" (__asid)); \
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__asid; \
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})
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#define ASID_MASK(asid) \
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({ \
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unsigned long __asid = asid; \
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__asm__("1:\tandi\t%0,%1,0xfc0\t\t\t# patched\n\t" \
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".section\t__asid_mask,\"a\"\n\t" \
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".word\t1b\n\t" \
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".previous" \
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:"=r" (__asid) \
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:"r" (__asid)); \
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__asid; \
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})
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#define ASID_VERSION_MASK \
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({ \
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unsigned long __asid; \
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__asm__("1:\taddiu\t%0,$0,0xff00\t\t\t\t# patched\n\t" \
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".section\t__asid_version_mask,\"a\"\n\t" \
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".word\t1b\n\t" \
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".previous" \
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:"=r" (__asid)); \
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__asid; \
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})
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#define ASID_FIRST_VERSION \
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({ \
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unsigned long __asid = asid; \
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__asm__("1:\tli\t%0,0x100\t\t\t\t# patched\n\t" \
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".section\t__asid_first_version,\"a\"\n\t" \
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".word\t1b\n\t" \
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".previous" \
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:"=r" (__asid)); \
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__asid; \
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})
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#define ASID_INC 0x40
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#define ASID_MASK 0xfc0
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#define ASID_FIRST_VERSION_R3000 0x1000
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#define ASID_FIRST_VERSION_R4000 0x100
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#define ASID_FIRST_VERSION_R8000 0x1000
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#define ASID_FIRST_VERSION_RM9000 0x1000
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#elif defined(CONFIG_CPU_R8000)
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#define ASID_INC 0x10
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#define ASID_MASK 0xff0
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#elif defined(CONFIG_MIPS_MT_SMTC)
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#define ASID_INC 0x1
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extern unsigned long smtc_asid_mask;
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#define ASID_MASK (smtc_asid_mask)
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#define HW_ASID_MASK 0xff
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/* End SMTC/34K debug hack */
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#else /* FIXME: not correct for R6000 */
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#define ASID_INC 0x1
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#define ASID_MASK 0xff
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#ifdef CONFIG_MIPS_MT_SMTC
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#define SMTC_HW_ASID_MASK 0xff
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extern unsigned int smtc_asid_mask;
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#endif
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#define cpu_context(cpu, mm) ((mm)->context.asid[cpu])
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#define cpu_asid(cpu, mm) ASID_MASK(cpu_context((cpu), (mm)))
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#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK)
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#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
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static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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}
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/*
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* All unused by hardware upper bits will be considered
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* as a software asid extension.
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*/
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#define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
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#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
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#ifndef CONFIG_MIPS_MT_SMTC
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/* Normal, classic MIPS get_new_mmu_context */
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static inline void
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@ -137,7 +114,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
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extern void kvm_local_flush_tlb_all(void);
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unsigned long asid = asid_cache(cpu);
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if (!ASID_MASK((asid = ASID_INC(asid)))) {
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if (! ((asid += ASID_INC) & ASID_MASK) ) {
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if (cpu_has_vtag_icache)
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flush_icache_all();
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#ifdef CONFIG_VIRTUALIZATION
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@ -200,7 +177,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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* free up the ASID value for use and flush any old
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* instances of it from the TLB.
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*/
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oldasid = ASID_MASK(read_c0_entryhi());
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oldasid = (read_c0_entryhi() & ASID_MASK);
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if(smtc_live_asid[mytlb][oldasid]) {
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smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
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if(smtc_live_asid[mytlb][oldasid] == 0)
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@ -211,7 +188,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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* having ASID_MASK smaller than the hardware maximum,
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* make sure no "soft" bits become "hard"...
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*/
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write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK) |
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write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
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cpu_asid(cpu, next));
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ehb(); /* Make sure it propagates to TCStatus */
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evpe(mtflags);
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@ -264,15 +241,15 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next)
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#ifdef CONFIG_MIPS_MT_SMTC
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/* See comments for similar code above */
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mtflags = dvpe();
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oldasid = ASID_MASK(read_c0_entryhi());
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oldasid = read_c0_entryhi() & ASID_MASK;
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if(smtc_live_asid[mytlb][oldasid]) {
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smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
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if(smtc_live_asid[mytlb][oldasid] == 0)
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smtc_flush_tlb_asid(oldasid);
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}
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/* See comments for similar code above */
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write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK) |
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cpu_asid(cpu, next));
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write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
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cpu_asid(cpu, next));
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ehb(); /* Make sure it propagates to TCStatus */
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evpe(mtflags);
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#else
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@ -309,14 +286,14 @@ drop_mmu_context(struct mm_struct *mm, unsigned cpu)
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#ifdef CONFIG_MIPS_MT_SMTC
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/* See comments for similar code above */
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prevvpe = dvpe();
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oldasid = ASID_MASK(read_c0_entryhi());
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oldasid = (read_c0_entryhi() & ASID_MASK);
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if (smtc_live_asid[mytlb][oldasid]) {
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smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
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if(smtc_live_asid[mytlb][oldasid] == 0)
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smtc_flush_tlb_asid(oldasid);
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}
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/* See comments for similar code above */
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write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK)
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write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
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| cpu_asid(cpu, mm));
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ehb(); /* Make sure it propagates to TCStatus */
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evpe(prevvpe);
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@ -493,7 +493,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
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.set noreorder
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/* check if TLB contains a entry for EPC */
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MFC0 k1, CP0_ENTRYHI
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andi k1, 0xff /* ASID_MASK patched at run-time!! */
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andi k1, 0xff /* ASID_MASK */
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MFC0 k0, CP0_EPC
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PTR_SRL k0, _PAGE_SHIFT + 1
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PTR_SLL k0, _PAGE_SHIFT + 1
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@ -111,7 +111,7 @@ static int vpe0limit;
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static int ipibuffers;
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static int nostlb;
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static int asidmask;
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unsigned int smtc_asid_mask = 0xff;
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unsigned long smtc_asid_mask = 0xff;
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static int __init vpe0tcs(char *str)
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{
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@ -1395,7 +1395,7 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
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asid = asid_cache(cpu);
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do {
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if (!ASID_MASK(ASID_INC(asid))) {
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if (!((asid += ASID_INC) & ASID_MASK) ) {
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if (cpu_has_vtag_icache)
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flush_icache_all();
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/* Traverse all online CPUs (hack requires contiguous range) */
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@ -1414,7 +1414,7 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
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mips_ihb();
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}
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tcstat = read_tc_c0_tcstatus();
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smtc_live_asid[tlb][ASID_MASK(tcstat)] |= (asiduse)(0x1 << i);
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smtc_live_asid[tlb][(tcstat & ASID_MASK)] |= (asiduse)(0x1 << i);
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if (!prevhalt)
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write_tc_c0_tchalt(0);
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}
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@ -1423,7 +1423,7 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
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asid = ASID_FIRST_VERSION;
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local_flush_tlb_all(); /* start new asid cycle */
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}
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} while (smtc_live_asid[tlb][ASID_MASK(asid)]);
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} while (smtc_live_asid[tlb][(asid & ASID_MASK)]);
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/*
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* SMTC shares the TLB within VPEs and possibly across all VPEs.
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@ -1461,7 +1461,7 @@ void smtc_flush_tlb_asid(unsigned long asid)
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tlb_read();
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ehb();
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ehi = read_c0_entryhi();
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if (ASID_MASK(ehi) == asid) {
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if ((ehi & ASID_MASK) == asid) {
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/*
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* Invalidate only entries with specified ASID,
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* makiing sure all entries differ.
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@ -1656,7 +1656,6 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
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unsigned int cpu = smp_processor_id();
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unsigned int status_set = ST0_CU0;
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unsigned int hwrena = cpu_hwrena_impl_bits;
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unsigned long asid = 0;
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#ifdef CONFIG_MIPS_MT_SMTC
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int secondaryTC = 0;
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int bootTC = (cpu == 0);
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@ -1740,9 +1739,8 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
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}
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#endif /* CONFIG_MIPS_MT_SMTC */
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asid = ASID_FIRST_VERSION;
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cpu_data[cpu].asid_cache = asid;
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TLBMISS_HANDLER_SETUP();
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if (!cpu_data[cpu].asid_cache)
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cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
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atomic_inc(&init_mm.mm_count);
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current->active_mm = &init_mm;
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@ -525,16 +525,18 @@ kvm_mips_emulate_CP0(uint32_t inst, uint32_t *opc, uint32_t cause,
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printk("MTCz, cop0->reg[EBASE]: %#lx\n",
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kvm_read_c0_guest_ebase(cop0));
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} else if (rd == MIPS_CP0_TLB_HI && sel == 0) {
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uint32_t nasid = ASID_MASK(vcpu->arch.gprs[rt]);
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uint32_t nasid =
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vcpu->arch.gprs[rt] & ASID_MASK;
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if ((KSEGX(vcpu->arch.gprs[rt]) != CKSEG0)
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&&
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(ASID_MASK(kvm_read_c0_guest_entryhi(cop0))
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!= nasid)) {
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((kvm_read_c0_guest_entryhi(cop0) &
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ASID_MASK) != nasid)) {
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kvm_debug
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("MTCz, change ASID from %#lx to %#lx\n",
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ASID_MASK(kvm_read_c0_guest_entryhi(cop0)),
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ASID_MASK(vcpu->arch.gprs[rt]));
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kvm_read_c0_guest_entryhi(cop0) &
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ASID_MASK,
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vcpu->arch.gprs[rt] & ASID_MASK);
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/* Blow away the shadow host TLBs */
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kvm_mips_flush_host_tlb(1);
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@ -986,7 +988,8 @@ kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc, uint32_t cause,
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* resulting handler will do the right thing
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*/
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index = kvm_mips_guest_tlb_lookup(vcpu, (va & VPN2_MASK) |
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ASID_MASK(kvm_read_c0_guest_entryhi(cop0)));
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(kvm_read_c0_guest_entryhi
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(cop0) & ASID_MASK));
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if (index < 0) {
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vcpu->arch.host_cp0_entryhi = (va & VPN2_MASK);
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@ -1151,7 +1154,7 @@ kvm_mips_emulate_tlbmiss_ld(unsigned long cause, uint32_t *opc,
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struct kvm_vcpu_arch *arch = &vcpu->arch;
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enum emulation_result er = EMULATE_DONE;
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unsigned long entryhi = (vcpu->arch. host_cp0_badvaddr & VPN2_MASK) |
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ASID_MASK(kvm_read_c0_guest_entryhi(cop0));
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(kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
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if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
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/* save old pc */
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@ -1198,7 +1201,7 @@ kvm_mips_emulate_tlbinv_ld(unsigned long cause, uint32_t *opc,
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enum emulation_result er = EMULATE_DONE;
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unsigned long entryhi =
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(vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
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ASID_MASK(kvm_read_c0_guest_entryhi(cop0));
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(kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
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if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
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/* save old pc */
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@ -1243,7 +1246,7 @@ kvm_mips_emulate_tlbmiss_st(unsigned long cause, uint32_t *opc,
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struct kvm_vcpu_arch *arch = &vcpu->arch;
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enum emulation_result er = EMULATE_DONE;
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unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
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ASID_MASK(kvm_read_c0_guest_entryhi(cop0));
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(kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
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if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
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/* save old pc */
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@ -1287,7 +1290,7 @@ kvm_mips_emulate_tlbinv_st(unsigned long cause, uint32_t *opc,
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struct kvm_vcpu_arch *arch = &vcpu->arch;
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enum emulation_result er = EMULATE_DONE;
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unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
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ASID_MASK(kvm_read_c0_guest_entryhi(cop0));
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(kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
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if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
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/* save old pc */
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@ -1356,7 +1359,7 @@ kvm_mips_emulate_tlbmod(unsigned long cause, uint32_t *opc,
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{
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struct mips_coproc *cop0 = vcpu->arch.cop0;
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unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
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ASID_MASK(kvm_read_c0_guest_entryhi(cop0));
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(kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
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struct kvm_vcpu_arch *arch = &vcpu->arch;
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enum emulation_result er = EMULATE_DONE;
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@ -1783,8 +1786,8 @@ kvm_mips_handle_tlbmiss(unsigned long cause, uint32_t *opc,
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*/
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index = kvm_mips_guest_tlb_lookup(vcpu,
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(va & VPN2_MASK) |
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ASID_MASK(kvm_read_c0_guest_entryhi
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(vcpu->arch.cop0)));
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(kvm_read_c0_guest_entryhi
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(vcpu->arch.cop0) & ASID_MASK));
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if (index < 0) {
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if (exccode == T_TLB_LD_MISS) {
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er = kvm_mips_emulate_tlbmiss_ld(cause, opc, run, vcpu);
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@ -51,13 +51,13 @@ EXPORT_SYMBOL(kvm_mips_is_error_pfn);
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uint32_t kvm_mips_get_kernel_asid(struct kvm_vcpu *vcpu)
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{
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return ASID_MASK(vcpu->arch.guest_kernel_asid[smp_processor_id()]);
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return vcpu->arch.guest_kernel_asid[smp_processor_id()] & ASID_MASK;
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}
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uint32_t kvm_mips_get_user_asid(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return ASID_MASK(vcpu->arch.guest_user_asid[smp_processor_id()]);
|
||||
return vcpu->arch.guest_user_asid[smp_processor_id()] & ASID_MASK;
|
||||
}
|
||||
|
||||
inline uint32_t kvm_mips_get_commpage_asid (struct kvm_vcpu *vcpu)
|
||||
|
@ -84,7 +84,7 @@ void kvm_mips_dump_host_tlbs(void)
|
|||
old_pagemask = read_c0_pagemask();
|
||||
|
||||
printk("HOST TLBs:\n");
|
||||
printk("ASID: %#lx\n", ASID_MASK(read_c0_entryhi()));
|
||||
printk("ASID: %#lx\n", read_c0_entryhi() & ASID_MASK);
|
||||
|
||||
for (i = 0; i < current_cpu_data.tlbsize; i++) {
|
||||
write_c0_index(i);
|
||||
|
@ -428,7 +428,7 @@ int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long entryhi)
|
|||
|
||||
for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) {
|
||||
if (((TLB_VPN2(tlb[i]) & ~tlb[i].tlb_mask) == ((entryhi & VPN2_MASK) & ~tlb[i].tlb_mask)) &&
|
||||
(TLB_IS_GLOBAL(tlb[i]) || (TLB_ASID(tlb[i]) == ASID_MASK(entryhi)))) {
|
||||
(TLB_IS_GLOBAL(tlb[i]) || (TLB_ASID(tlb[i]) == (entryhi & ASID_MASK)))) {
|
||||
index = i;
|
||||
break;
|
||||
}
|
||||
|
@ -626,7 +626,7 @@ kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
|
|||
{
|
||||
unsigned long asid = asid_cache(cpu);
|
||||
|
||||
if (!(ASID_MASK(ASID_INC(asid)))) {
|
||||
if (!((asid += ASID_INC) & ASID_MASK)) {
|
||||
if (cpu_has_vtag_icache) {
|
||||
flush_icache_all();
|
||||
}
|
||||
|
@ -804,7 +804,8 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
|
|||
if (!newasid) {
|
||||
/* If we preempted while the guest was executing, then reload the pre-empted ASID */
|
||||
if (current->flags & PF_VCPU) {
|
||||
write_c0_entryhi(ASID_MASK(vcpu->arch.preempt_entryhi));
|
||||
write_c0_entryhi(vcpu->arch.
|
||||
preempt_entryhi & ASID_MASK);
|
||||
ehb();
|
||||
}
|
||||
} else {
|
||||
|
@ -816,11 +817,13 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
|
|||
*/
|
||||
if (current->flags & PF_VCPU) {
|
||||
if (KVM_GUEST_KERNEL_MODE(vcpu))
|
||||
write_c0_entryhi(ASID_MASK(vcpu->arch.
|
||||
guest_kernel_asid[cpu]));
|
||||
write_c0_entryhi(vcpu->arch.
|
||||
guest_kernel_asid[cpu] &
|
||||
ASID_MASK);
|
||||
else
|
||||
write_c0_entryhi(ASID_MASK(vcpu->arch.
|
||||
guest_user_asid[cpu]));
|
||||
write_c0_entryhi(vcpu->arch.
|
||||
guest_user_asid[cpu] &
|
||||
ASID_MASK);
|
||||
ehb();
|
||||
}
|
||||
}
|
||||
|
@ -879,7 +882,8 @@ uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu)
|
|||
kvm_mips_guest_tlb_lookup(vcpu,
|
||||
((unsigned long) opc & VPN2_MASK)
|
||||
|
|
||||
ASID_MASK(kvm_read_c0_guest_entryhi(cop0)));
|
||||
(kvm_read_c0_guest_entryhi
|
||||
(cop0) & ASID_MASK));
|
||||
if (index < 0) {
|
||||
kvm_err
|
||||
("%s: get_user_failed for %p, vcpu: %p, ASID: %#lx\n",
|
||||
|
|
|
@ -11,7 +11,6 @@
|
|||
#include <asm/page.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/tlbdebug.h>
|
||||
#include <asm/mmu_context.h>
|
||||
|
||||
static inline const char *msk2str(unsigned int mask)
|
||||
{
|
||||
|
@ -56,7 +55,7 @@ static void dump_tlb(int first, int last)
|
|||
s_pagemask = read_c0_pagemask();
|
||||
s_entryhi = read_c0_entryhi();
|
||||
s_index = read_c0_index();
|
||||
asid = ASID_MASK(s_entryhi);
|
||||
asid = s_entryhi & 0xff;
|
||||
|
||||
for (i = first; i <= last; i++) {
|
||||
write_c0_index(i);
|
||||
|
@ -86,7 +85,7 @@ static void dump_tlb(int first, int last)
|
|||
|
||||
printk("va=%0*lx asid=%02lx\n",
|
||||
width, (entryhi & ~0x1fffUL),
|
||||
ASID_MASK(entryhi));
|
||||
entryhi & 0xff);
|
||||
printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ",
|
||||
width,
|
||||
(entrylo0 << 6) & PAGE_MASK, c0,
|
||||
|
|
|
@ -9,7 +9,6 @@
|
|||
#include <linux/mm.h>
|
||||
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/tlbdebug.h>
|
||||
|
@ -22,7 +21,7 @@ static void dump_tlb(int first, int last)
|
|||
unsigned int asid;
|
||||
unsigned long entryhi, entrylo0;
|
||||
|
||||
asid = ASID_MASK(read_c0_entryhi());
|
||||
asid = read_c0_entryhi() & 0xfc0;
|
||||
|
||||
for (i = first; i <= last; i++) {
|
||||
write_c0_index(i<<8);
|
||||
|
@ -36,7 +35,7 @@ static void dump_tlb(int first, int last)
|
|||
|
||||
/* Unused entries have a virtual address of KSEG0. */
|
||||
if ((entryhi & 0xffffe000) != 0x80000000
|
||||
&& (ASID_MASK(entryhi) == asid)) {
|
||||
&& (entryhi & 0xfc0) == asid) {
|
||||
/*
|
||||
* Only print entries in use
|
||||
*/
|
||||
|
@ -45,7 +44,7 @@ static void dump_tlb(int first, int last)
|
|||
printk("va=%08lx asid=%08lx"
|
||||
" [pa=%06lx n=%d d=%d v=%d g=%d]",
|
||||
(entryhi & 0xffffe000),
|
||||
ASID_MASK(entryhi),
|
||||
entryhi & 0xfc0,
|
||||
entrylo0 & PAGE_MASK,
|
||||
(entrylo0 & (1 << 11)) ? 1 : 0,
|
||||
(entrylo0 & (1 << 10)) ? 1 : 0,
|
||||
|
|
|
@ -51,7 +51,7 @@ void local_flush_tlb_all(void)
|
|||
#endif
|
||||
|
||||
local_irq_save(flags);
|
||||
old_ctx = ASID_MASK(read_c0_entryhi());
|
||||
old_ctx = read_c0_entryhi() & ASID_MASK;
|
||||
write_c0_entrylo0(0);
|
||||
entry = r3k_have_wired_reg ? read_c0_wired() : 8;
|
||||
for (; entry < current_cpu_data.tlbsize; entry++) {
|
||||
|
@ -87,13 +87,13 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
|
|||
|
||||
#ifdef DEBUG_TLB
|
||||
printk("[tlbrange<%lu,0x%08lx,0x%08lx>]",
|
||||
ASID_MASK(cpu_context(cpu, mm)), start, end);
|
||||
cpu_context(cpu, mm) & ASID_MASK, start, end);
|
||||
#endif
|
||||
local_irq_save(flags);
|
||||
size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
||||
if (size <= current_cpu_data.tlbsize) {
|
||||
int oldpid = ASID_MASK(read_c0_entryhi());
|
||||
int newpid = ASID_MASK(cpu_context(cpu, mm));
|
||||
int oldpid = read_c0_entryhi() & ASID_MASK;
|
||||
int newpid = cpu_context(cpu, mm) & ASID_MASK;
|
||||
|
||||
start &= PAGE_MASK;
|
||||
end += PAGE_SIZE - 1;
|
||||
|
@ -166,10 +166,10 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
|
|||
#ifdef DEBUG_TLB
|
||||
printk("[tlbpage<%lu,0x%08lx>]", cpu_context(cpu, vma->vm_mm), page);
|
||||
#endif
|
||||
newpid = ASID_MASK(cpu_context(cpu, vma->vm_mm));
|
||||
newpid = cpu_context(cpu, vma->vm_mm) & ASID_MASK;
|
||||
page &= PAGE_MASK;
|
||||
local_irq_save(flags);
|
||||
oldpid = ASID_MASK(read_c0_entryhi());
|
||||
oldpid = read_c0_entryhi() & ASID_MASK;
|
||||
write_c0_entryhi(page | newpid);
|
||||
BARRIER;
|
||||
tlb_probe();
|
||||
|
@ -197,10 +197,10 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
|
|||
if (current->active_mm != vma->vm_mm)
|
||||
return;
|
||||
|
||||
pid = ASID_MASK(read_c0_entryhi());
|
||||
pid = read_c0_entryhi() & ASID_MASK;
|
||||
|
||||
#ifdef DEBUG_TLB
|
||||
if ((pid != ASID_MASK(cpu_context(cpu, vma->vm_mm))) || (cpu_context(cpu, vma->vm_mm) == 0)) {
|
||||
if ((pid != (cpu_context(cpu, vma->vm_mm) & ASID_MASK)) || (cpu_context(cpu, vma->vm_mm) == 0)) {
|
||||
printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%lu tlbpid=%d\n",
|
||||
(cpu_context(cpu, vma->vm_mm)), pid);
|
||||
}
|
||||
|
@ -241,7 +241,7 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
|
|||
|
||||
local_irq_save(flags);
|
||||
/* Save old context and create impossible VPN2 value */
|
||||
old_ctx = ASID_MASK(read_c0_entryhi());
|
||||
old_ctx = read_c0_entryhi() & ASID_MASK;
|
||||
old_pagemask = read_c0_pagemask();
|
||||
w = read_c0_wired();
|
||||
write_c0_wired(w + 1);
|
||||
|
@ -264,7 +264,7 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
|
|||
#endif
|
||||
|
||||
local_irq_save(flags);
|
||||
old_ctx = ASID_MASK(read_c0_entryhi());
|
||||
old_ctx = read_c0_entryhi() & ASID_MASK;
|
||||
write_c0_entrylo0(entrylo0);
|
||||
write_c0_entryhi(entryhi);
|
||||
write_c0_index(wired);
|
||||
|
|
|
@ -287,7 +287,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
|
|||
|
||||
ENTER_CRITICAL(flags);
|
||||
|
||||
pid = ASID_MASK(read_c0_entryhi());
|
||||
pid = read_c0_entryhi() & ASID_MASK;
|
||||
address &= (PAGE_MASK << 1);
|
||||
write_c0_entryhi(address | pid);
|
||||
pgdp = pgd_offset(vma->vm_mm, address);
|
||||
|
|
|
@ -195,7 +195,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
|
|||
if (current->active_mm != vma->vm_mm)
|
||||
return;
|
||||
|
||||
pid = ASID_MASK(read_c0_entryhi());
|
||||
pid = read_c0_entryhi() & ASID_MASK;
|
||||
|
||||
local_irq_save(flags);
|
||||
address &= PAGE_MASK;
|
||||
|
|
|
@ -29,7 +29,6 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/cache.h>
|
||||
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/war.h>
|
||||
|
@ -306,48 +305,6 @@ static struct uasm_reloc relocs[128] __cpuinitdata;
|
|||
static int check_for_high_segbits __cpuinitdata;
|
||||
#endif
|
||||
|
||||
static void __cpuinit insn_fixup(unsigned int **start, unsigned int **stop,
|
||||
unsigned int i_const)
|
||||
{
|
||||
unsigned int **p, *ip;
|
||||
|
||||
for (p = start; p < stop; p++) {
|
||||
ip = *p;
|
||||
*ip = (*ip & 0xffff0000) | i_const;
|
||||
}
|
||||
local_flush_icache_range((unsigned long)*p, (unsigned long)((*p) + 1));
|
||||
}
|
||||
|
||||
#define asid_insn_fixup(section, const) \
|
||||
do { \
|
||||
extern unsigned int *__start_ ## section; \
|
||||
extern unsigned int *__stop_ ## section; \
|
||||
insn_fixup(&__start_ ## section, &__stop_ ## section, const); \
|
||||
} while(0)
|
||||
|
||||
/*
|
||||
* Caller is assumed to flush the caches before the first context switch.
|
||||
*/
|
||||
static void __cpuinit setup_asid(unsigned int inc, unsigned int mask,
|
||||
unsigned int version_mask,
|
||||
unsigned int first_version)
|
||||
{
|
||||
extern asmlinkage void handle_ri_rdhwr_vivt(void);
|
||||
unsigned long *vivt_exc;
|
||||
|
||||
asid_insn_fixup(__asid_inc, inc);
|
||||
asid_insn_fixup(__asid_mask, mask);
|
||||
asid_insn_fixup(__asid_version_mask, version_mask);
|
||||
asid_insn_fixup(__asid_first_version, first_version);
|
||||
|
||||
/* Patch up the 'handle_ri_rdhwr_vivt' handler. */
|
||||
vivt_exc = (unsigned long *) &handle_ri_rdhwr_vivt;
|
||||
vivt_exc++;
|
||||
*vivt_exc = (*vivt_exc & ~mask) | mask;
|
||||
|
||||
current_cpu_data.asid_cache = first_version;
|
||||
}
|
||||
|
||||
static int check_for_high_segbits __cpuinitdata;
|
||||
|
||||
static unsigned int kscratch_used_mask __cpuinitdata;
|
||||
|
@ -2226,7 +2183,6 @@ void __cpuinit build_tlb_refill_handler(void)
|
|||
case CPU_TX3922:
|
||||
case CPU_TX3927:
|
||||
#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
|
||||
setup_asid(0x40, 0xfc0, 0xf000, ASID_FIRST_VERSION_R3000);
|
||||
if (cpu_has_local_ebase)
|
||||
build_r3000_tlb_refill_handler();
|
||||
if (!run_once) {
|
||||
|
@ -2252,11 +2208,6 @@ void __cpuinit build_tlb_refill_handler(void)
|
|||
break;
|
||||
|
||||
default:
|
||||
#ifndef CONFIG_MIPS_MT_SMTC
|
||||
setup_asid(0x1, 0xff, 0xff00, ASID_FIRST_VERSION_R4000);
|
||||
#else
|
||||
setup_asid(0x1, smtc_asid_mask, 0xff00, ASID_FIRST_VERSION_R4000);
|
||||
#endif
|
||||
if (!run_once) {
|
||||
scratch_reg = allocate_kscratch();
|
||||
#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
|
||||
|
|
Loading…
Reference in a new issue