dmaengine: Revert "drivers/dma: remove unused support for MEMSET operations"
This reverts commit 48a9db462d
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Some platforms actually need support for the memset operations. Bring it back.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
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fbea28a2af
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4983a501af
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@ -832,6 +832,8 @@ int dma_async_device_register(struct dma_device *device)
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!device->device_prep_dma_pq);
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!device->device_prep_dma_pq);
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BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
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BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
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!device->device_prep_dma_pq_val);
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!device->device_prep_dma_pq_val);
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BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) &&
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!device->device_prep_dma_memset);
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BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
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BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
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!device->device_prep_dma_interrupt);
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!device->device_prep_dma_interrupt);
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BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
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BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
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@ -65,6 +65,7 @@ enum dma_transaction_type {
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DMA_PQ,
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DMA_PQ,
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DMA_XOR_VAL,
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DMA_XOR_VAL,
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DMA_PQ_VAL,
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DMA_PQ_VAL,
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DMA_MEMSET,
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DMA_INTERRUPT,
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DMA_INTERRUPT,
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DMA_SG,
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DMA_SG,
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DMA_PRIVATE,
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DMA_PRIVATE,
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@ -570,6 +571,7 @@ struct dma_tx_state {
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* @copy_align: alignment shift for memcpy operations
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* @copy_align: alignment shift for memcpy operations
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* @xor_align: alignment shift for xor operations
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* @xor_align: alignment shift for xor operations
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* @pq_align: alignment shift for pq operations
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* @pq_align: alignment shift for pq operations
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* @fill_align: alignment shift for memset operations
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* @dev_id: unique device ID
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* @dev_id: unique device ID
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* @dev: struct device reference for dma mapping api
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* @dev: struct device reference for dma mapping api
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* @src_addr_widths: bit mask of src addr widths the device supports
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* @src_addr_widths: bit mask of src addr widths the device supports
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@ -588,6 +590,7 @@ struct dma_tx_state {
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* @device_prep_dma_xor_val: prepares a xor validation operation
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* @device_prep_dma_xor_val: prepares a xor validation operation
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* @device_prep_dma_pq: prepares a pq operation
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* @device_prep_dma_pq: prepares a pq operation
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* @device_prep_dma_pq_val: prepares a pqzero_sum operation
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* @device_prep_dma_pq_val: prepares a pqzero_sum operation
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* @device_prep_dma_memset: prepares a memset operation
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* @device_prep_dma_interrupt: prepares an end of chain interrupt operation
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* @device_prep_dma_interrupt: prepares an end of chain interrupt operation
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* @device_prep_slave_sg: prepares a slave dma operation
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* @device_prep_slave_sg: prepares a slave dma operation
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* @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
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* @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
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@ -620,6 +623,7 @@ struct dma_device {
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u8 copy_align;
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u8 copy_align;
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u8 xor_align;
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u8 xor_align;
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u8 pq_align;
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u8 pq_align;
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u8 fill_align;
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#define DMA_HAS_PQ_CONTINUE (1 << 15)
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#define DMA_HAS_PQ_CONTINUE (1 << 15)
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int dev_id;
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int dev_id;
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@ -650,6 +654,9 @@ struct dma_device {
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struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
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struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
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unsigned int src_cnt, const unsigned char *scf, size_t len,
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unsigned int src_cnt, const unsigned char *scf, size_t len,
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enum sum_check_flags *pqres, unsigned long flags);
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enum sum_check_flags *pqres, unsigned long flags);
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struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
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struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
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unsigned long flags);
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struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
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struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
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struct dma_chan *chan, unsigned long flags);
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struct dma_chan *chan, unsigned long flags);
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struct dma_async_tx_descriptor *(*device_prep_dma_sg)(
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struct dma_async_tx_descriptor *(*device_prep_dma_sg)(
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@ -745,6 +752,17 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
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return chan->device->device_prep_interleaved_dma(chan, xt, flags);
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return chan->device->device_prep_interleaved_dma(chan, xt, flags);
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}
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}
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static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset(
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struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
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unsigned long flags)
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{
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if (!chan || !chan->device)
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return NULL;
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return chan->device->device_prep_dma_memset(chan, dest, value,
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len, flags);
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}
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static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg(
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static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg(
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struct dma_chan *chan,
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struct dma_chan *chan,
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struct scatterlist *dst_sg, unsigned int dst_nents,
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struct scatterlist *dst_sg, unsigned int dst_nents,
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@ -820,6 +838,12 @@ static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
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return dmaengine_check_align(dev->pq_align, off1, off2, len);
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return dmaengine_check_align(dev->pq_align, off1, off2, len);
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}
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}
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static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
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size_t off2, size_t len)
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{
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return dmaengine_check_align(dev->fill_align, off1, off2, len);
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}
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static inline void
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static inline void
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dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
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dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
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{
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{
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