arm64: KVM: Add workaround for Cortex-A57 erratum 834220
Cortex-A57 parts up to r1p2 can misreport Stage 2 translation faults when a Stage 1 permission fault or device alignment fault should have been reported. This patch implements the workaround (which is to validate that the Stage-1 translation actually succeeds) by using code patching. Cc: stable@vger.kernel.org Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
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@ -316,6 +316,27 @@ config ARM64_ERRATUM_832075
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If unsure, say Y.
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config ARM64_ERRATUM_834220
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bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
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depends on KVM
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default y
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help
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This option adds an alternative code sequence to work around ARM
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erratum 834220 on Cortex-A57 parts up to r1p2.
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Affected Cortex-A57 parts might report a Stage 2 translation
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fault as the result of a Stage 1 fault for load crossing a
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page boundary when there is a permission or device memory
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alignment fault at Stage 1 and a translation fault at Stage 2.
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The workaround is to verify that the Stage 1 translation
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doesn't generate a fault before handling the Stage 2 fault.
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Please note that this does not necessarily enable the workaround,
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as it depends on the alternative framework, which will only patch
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the kernel if an affected CPU is detected.
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If unsure, say Y.
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config ARM64_ERRATUM_845719
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bool "Cortex-A53: 845719: a load might read incorrect data"
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depends on COMPAT
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@ -29,8 +29,9 @@
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#define ARM64_HAS_PAN 4
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#define ARM64_HAS_LSE_ATOMICS 5
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#define ARM64_WORKAROUND_CAVIUM_23154 6
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#define ARM64_WORKAROUND_834220 7
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#define ARM64_NCAPS 7
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#define ARM64_NCAPS 8
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#ifndef __ASSEMBLY__
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@ -75,6 +75,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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(1 << MIDR_VARIANT_SHIFT) | 2),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_834220
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{
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/* Cortex-A57 r0p0 - r1p2 */
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.desc = "ARM erratum 834220",
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.capability = ARM64_WORKAROUND_834220,
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MIDR_RANGE(MIDR_CORTEX_A57, 0x00,
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(1 << MIDR_VARIANT_SHIFT) | 2),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_845719
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{
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/* Cortex-A53 r0p[01234] */
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@ -1015,9 +1015,15 @@ el1_trap:
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b.ne 1f // Not an abort we care about
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/* This is an abort. Check for permission fault */
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alternative_if_not ARM64_WORKAROUND_834220
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and x2, x1, #ESR_ELx_FSC_TYPE
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cmp x2, #FSC_PERM
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b.ne 1f // Not a permission fault
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alternative_else
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nop // Use the permission fault path to
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nop // check for a valid S1 translation,
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nop // regardless of the ESR value.
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alternative_endif
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/*
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* Check for Stage-1 page table walk, which is guaranteed
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