ARC updates for 4.12
- AXS10x platform clk updates for I2S, PGU - Adding region based cache flush operation for ARCv2 cores - Enforcing PAE40 dependency on HIGHMEM - ptrace support for additional regs in ARCv2 cores - Fix build failure in linux-next dut to a header include ordering change -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZEeokAAoJEGnX8d3iisJe/zgP/jpqauxaulNK4BvjJ3pI0+Fn Pgz5Mgd/S7MzmiDPsb3H0YSWQMlxcSop+EPk8V4jXcXyTuDDaC7NzWLuKau2rjiB jdbTycsJ4xSS5A8NrnG6AeE8SYAubJmtEwD8JASx+trtLGGHCKdTsRIOQpm5faUn W2IFaXs9Jof5ZYL5btOzmIOOTxdR6f3Aegq/Zqb6rxqD8ZmtVapjPdIlqQEB/xw4 JSbTH9+HxI1+vpzCuOb1Ba4sglfFG9kH0xxWvMN5HuoYsdXG5KfjoXVsxUIEl/RC m+bNdDOg5nlCS0U5PngnJnm5beBsAS8BApTTTM3ALNWGrsn+a6/1PraLsIgfa/yI XgcXp80/rGiFqAA3+fUw+ly1oJb06V9p4SRCOaOTErqcxofS4upbJ7oTu5z0HwMV HM2aw8vxZ2j4Wqrl5U3fGE9KvifUMJKuhcumpzfcmDsTtklCis4z13nbF0texNF2 tj0yqxYlOSdx4PoVzQG9Audf0sDeKUJ6Of+aGAXW55Zwq+QQJoCCzMSvTEV/xH4P RUIFkkhCQzshVmUDgHnWAjccrxz/LUrO1zLpwmOD0QWjfJHhyhegrlXGuKxNiRH5 rijMkOIe+Z8yG/UKqW0nvtB9svS0y9vqh3kEG1DJIRnNg7U2Fmk7rB404fGuvh4B T8uxDhsWP60hMZX1rw6h =zJ9B -----END PGP SIGNATURE----- Merge tag 'arc-4.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC updates from Vineet Gupta: - AXS10x platform clk updates for I2S, PGU - add region based cache flush operation for ARCv2 cores - enforce PAE40 dependency on HIGHMEM - ptrace support for additional regs in ARCv2 cores - fix build failure in linux-next dut to a header include ordering change * tag 'arc-4.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: Revert "ARCv2: Allow enabling PAE40 w/o HIGHMEM" ARC: mm: fix build failure in linux-next for UP builds ARCv2: ptrace: provide regset for accumulator/r30 regs elf: Add ARCv2 specific core note section ARCv2: mm: micro-optimize region flush generated code ARCv2: mm: Merge 2 updates to DC_CTRL for region flush ARCv2: mm: Implement cache region flush operations ARC: mm: Move full_page computation into cache version agnostic wrapper arc: axs10x: Fix ARC PGU default clock frequency arc: axs10x: Add DT bindings for I2S audio playbackzero-colors
Linus Torvalds
commit
4a1e31c68e
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@ -444,6 +444,7 @@ config ARC_HAS_PAE40
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bool "Support for the 40-bit Physical Address Extension"
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default n
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depends on ISA_ARCV2
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select HIGHMEM
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help
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Enable access to physical memory beyond 4G, only supported on
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ARC cores with 40 bit Physical Addressing support
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@ -51,7 +51,7 @@
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pguclk: pguclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <74440000>;
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clock-frequency = <74250000>;
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};
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};
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@ -149,12 +149,13 @@
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interrupts = <14>;
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};
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i2c@0x1e000 {
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compatible = "snps,designware-i2c";
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i2s: i2s@1e000 {
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compatible = "snps,designware-i2s";
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reg = <0x1e000 0x100>;
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clock-frequency = <400000>;
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clocks = <&i2cclk>;
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clocks = <&i2sclk 0>;
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clock-names = "i2sclk";
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interrupts = <15>;
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#sound-dai-cells = <0>;
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};
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i2c@0x1f000 {
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@ -174,6 +175,7 @@
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adi,input-colorspace = "rgb";
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adi,input-clock = "1x";
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adi,clock-delay = <0x03>;
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#sound-dai-cells = <0>;
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ports {
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#address-cells = <1>;
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@ -295,5 +297,17 @@
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};
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};
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};
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sound_playback {
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compatible = "simple-audio-card";
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simple-audio-card,name = "AXS10x HDMI Audio";
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simple-audio-card,format = "i2s";
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simple-audio-card,cpu {
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sound-dai = <&i2s>;
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};
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simple-audio-card,codec {
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sound-dai = <&adv7511>;
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};
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};
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};
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};
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@ -62,6 +62,8 @@ extern unsigned long perip_base, perip_end;
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#define ARC_REG_IC_BCR 0x77 /* Build Config reg */
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#define ARC_REG_IC_IVIC 0x10
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#define ARC_REG_IC_CTRL 0x11
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#define ARC_REG_IC_IVIR 0x16
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#define ARC_REG_IC_ENDR 0x17
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#define ARC_REG_IC_IVIL 0x19
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#define ARC_REG_IC_PTAG 0x1E
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#define ARC_REG_IC_PTAG_HI 0x1F
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@ -76,6 +78,8 @@ extern unsigned long perip_base, perip_end;
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#define ARC_REG_DC_IVDL 0x4A
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#define ARC_REG_DC_FLSH 0x4B
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#define ARC_REG_DC_FLDL 0x4C
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#define ARC_REG_DC_STARTR 0x4D
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#define ARC_REG_DC_ENDR 0x4E
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#define ARC_REG_DC_PTAG 0x5C
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#define ARC_REG_DC_PTAG_HI 0x5F
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@ -83,6 +87,8 @@ extern unsigned long perip_base, perip_end;
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#define DC_CTRL_DIS 0x001
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#define DC_CTRL_INV_MODE_FLUSH 0x040
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#define DC_CTRL_FLUSH_STATUS 0x100
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#define DC_CTRL_RGN_OP_INV 0x200
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#define DC_CTRL_RGN_OP_MSK 0x200
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/*System-level cache (L2 cache) related Auxiliary registers */
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#define ARC_REG_SLC_CFG 0x901
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@ -9,6 +9,10 @@
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#ifndef _ASM_ARC_MMU_H
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#define _ASM_ARC_MMU_H
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#ifndef __ASSEMBLY__
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#include <linux/threads.h> /* NR_CPUS */
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#endif
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#if defined(CONFIG_ARC_MMU_V1)
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#define CONFIG_ARC_MMU_VER 1
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#elif defined(CONFIG_ARC_MMU_V2)
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@ -35,11 +35,11 @@
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#ifndef _ASM_ARC_PGTABLE_H
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#define _ASM_ARC_PGTABLE_H
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <linux/const.h>
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#define __ARCH_USE_5LEVEL_HACK
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#include <asm-generic/pgtable-nopmd.h>
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#include <linux/const.h>
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#include <asm/page.h>
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#include <asm/mmu.h> /* to propagate CONFIG_ARC_MMU_VER <n> */
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/**************************************************************************
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* Page Table Flags
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@ -27,6 +27,7 @@ typedef unsigned long elf_greg_t;
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typedef unsigned long elf_fpregset_t;
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#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
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#define ELF_ARCV2REG (sizeof(struct user_regs_arcv2) / sizeof(elf_greg_t))
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typedef elf_greg_t elf_gregset_t[ELF_NGREG];
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@ -47,6 +47,11 @@ struct user_regs_struct {
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unsigned long efa; /* break pt addr, for break points in delay slots */
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unsigned long stop_pc; /* give dbg stop_pc after ensuring brkpt trap */
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};
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struct user_regs_arcv2 {
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unsigned long r30, r58, r59;
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};
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#endif /* !__ASSEMBLY__ */
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#endif /* _UAPI__ASM_ARC_PTRACE_H */
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@ -184,19 +184,75 @@ static int genregs_set(struct task_struct *target,
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return ret;
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}
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#ifdef CONFIG_ISA_ARCV2
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static int arcv2regs_get(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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void *kbuf, void __user *ubuf)
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{
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const struct pt_regs *regs = task_pt_regs(target);
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int ret, copy_sz;
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if (IS_ENABLED(CONFIG_ARC_HAS_ACCL_REGS))
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copy_sz = sizeof(struct user_regs_arcv2);
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else
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copy_sz = 4; /* r30 only */
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/*
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* itemized copy not needed like above as layout of regs (r30,r58,r59)
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* is exactly same in kernel (pt_regs) and userspace (user_regs_arcv2)
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*/
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ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, ®s->r30,
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0, copy_sz);
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return ret;
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}
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static int arcv2regs_set(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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const void *kbuf, const void __user *ubuf)
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{
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const struct pt_regs *regs = task_pt_regs(target);
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int ret, copy_sz;
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if (IS_ENABLED(CONFIG_ARC_HAS_ACCL_REGS))
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copy_sz = sizeof(struct user_regs_arcv2);
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else
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copy_sz = 4; /* r30 only */
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, (void *)®s->r30,
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0, copy_sz);
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return ret;
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}
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#endif
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enum arc_getset {
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REGSET_GENERAL,
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REGSET_CMN,
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REGSET_ARCV2,
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};
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static const struct user_regset arc_regsets[] = {
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[REGSET_GENERAL] = {
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[REGSET_CMN] = {
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.core_note_type = NT_PRSTATUS,
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.n = ELF_NGREG,
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.size = sizeof(unsigned long),
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.align = sizeof(unsigned long),
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.get = genregs_get,
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.set = genregs_set,
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}
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},
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#ifdef CONFIG_ISA_ARCV2
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[REGSET_ARCV2] = {
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.core_note_type = NT_ARC_V2,
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.n = ELF_ARCV2REG,
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.size = sizeof(unsigned long),
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.align = sizeof(unsigned long),
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.get = arcv2regs_get,
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.set = arcv2regs_set,
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},
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#endif
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};
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static const struct user_regset_view user_arc_view = {
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@ -21,6 +21,10 @@
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#include <asm/cachectl.h>
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#include <asm/setup.h>
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#ifdef CONFIG_ISA_ARCV2
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#define USE_RGN_FLSH 1
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#endif
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static int l2_line_sz;
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static int ioc_exists;
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int slc_enable = 1, ioc_enable = 1;
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@ -28,7 +32,7 @@ unsigned long perip_base = ARC_UNCACHED_ADDR_SPACE; /* legacy value for boot */
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unsigned long perip_end = 0xFFFFFFFF; /* legacy value */
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void (*_cache_line_loop_ic_fn)(phys_addr_t paddr, unsigned long vaddr,
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unsigned long sz, const int cacheop);
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unsigned long sz, const int op, const int full_page);
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void (*__dma_cache_wback_inv)(phys_addr_t start, unsigned long sz);
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void (*__dma_cache_inv)(phys_addr_t start, unsigned long sz);
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@ -233,11 +237,10 @@ slc_chk:
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static inline
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void __cache_line_loop_v2(phys_addr_t paddr, unsigned long vaddr,
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unsigned long sz, const int op)
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unsigned long sz, const int op, const int full_page)
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{
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unsigned int aux_cmd;
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int num_lines;
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const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
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if (op == OP_INV_IC) {
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aux_cmd = ARC_REG_IC_IVIL;
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@ -279,11 +282,10 @@ void __cache_line_loop_v2(phys_addr_t paddr, unsigned long vaddr,
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*/
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static inline
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void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
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unsigned long sz, const int op)
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unsigned long sz, const int op, const int full_page)
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{
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unsigned int aux_cmd, aux_tag;
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int num_lines;
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const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
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if (op == OP_INV_IC) {
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aux_cmd = ARC_REG_IC_IVIL;
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@ -334,6 +336,8 @@ void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
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}
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}
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#ifndef USE_RGN_FLSH
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/*
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* In HS38x (MMU v4), I-cache is VIPT (can alias), D-cache is PIPT
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* Here's how cache ops are implemented
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@ -349,17 +353,16 @@ void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
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*/
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static inline
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void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
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unsigned long sz, const int cacheop)
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unsigned long sz, const int op, const int full_page)
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{
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unsigned int aux_cmd;
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int num_lines;
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const int full_page_op = __builtin_constant_p(sz) && sz == PAGE_SIZE;
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if (cacheop == OP_INV_IC) {
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if (op == OP_INV_IC) {
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aux_cmd = ARC_REG_IC_IVIL;
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} else {
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/* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
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aux_cmd = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
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aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
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}
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/* Ensure we properly floor/ceil the non-line aligned/sized requests
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@ -368,7 +371,7 @@ void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
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* -@paddr will be cache-line aligned already (being page aligned)
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* -@sz will be integral multiple of line size (being page sized).
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*/
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if (!full_page_op) {
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if (!full_page) {
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sz += paddr & ~CACHE_LINE_MASK;
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paddr &= CACHE_LINE_MASK;
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}
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@ -381,7 +384,7 @@ void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
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* - (and needs to be written before the lower 32 bits)
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*/
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if (is_pae40_enabled()) {
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if (cacheop == OP_INV_IC)
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if (op == OP_INV_IC)
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/*
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* Non aliasing I-cache in HS38,
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* aliasing I-cache handled in __cache_line_loop_v3()
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@ -397,6 +400,55 @@ void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
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}
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}
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#else
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/*
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* optimized flush operation which takes a region as opposed to iterating per line
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*/
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static inline
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void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
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unsigned long sz, const int op, const int full_page)
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{
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unsigned int s, e;
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/* Only for Non aliasing I-cache in HS38 */
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if (op == OP_INV_IC) {
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s = ARC_REG_IC_IVIR;
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e = ARC_REG_IC_ENDR;
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} else {
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s = ARC_REG_DC_STARTR;
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e = ARC_REG_DC_ENDR;
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}
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if (!full_page) {
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/* for any leading gap between @paddr and start of cache line */
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sz += paddr & ~CACHE_LINE_MASK;
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paddr &= CACHE_LINE_MASK;
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/*
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* account for any trailing gap to end of cache line
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* this is equivalent to DIV_ROUND_UP() in line ops above
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*/
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sz += L1_CACHE_BYTES - 1;
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}
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if (is_pae40_enabled()) {
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/* TBD: check if crossing 4TB boundary */
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if (op == OP_INV_IC)
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write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);
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else
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write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32);
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}
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/* ENDR needs to be set ahead of START */
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write_aux_reg(e, paddr + sz); /* ENDR is exclusive */
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write_aux_reg(s, paddr);
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/* caller waits on DC_CTRL.FS */
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}
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#endif
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#if (CONFIG_ARC_MMU_VER < 3)
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#define __cache_line_loop __cache_line_loop_v2
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#elif (CONFIG_ARC_MMU_VER == 3)
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@ -411,6 +463,11 @@ void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
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* Machine specific helpers for Entire D-Cache or Per Line ops
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*/
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#ifndef USE_RGN_FLSH
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||||
/*
|
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* this version avoids extra read/write of DC_CTRL for flush or invalid ops
|
||||
* in the non region flush regime (such as for ARCompact)
|
||||
*/
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static inline void __before_dc_op(const int op)
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{
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if (op == OP_FLUSH_N_INV) {
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|
|
@ -424,6 +481,32 @@ static inline void __before_dc_op(const int op)
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}
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||||
}
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#else
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static inline void __before_dc_op(const int op)
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||||
{
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||||
const unsigned int ctl = ARC_REG_DC_CTRL;
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unsigned int val = read_aux_reg(ctl);
|
||||
|
||||
if (op == OP_FLUSH_N_INV) {
|
||||
val |= DC_CTRL_INV_MODE_FLUSH;
|
||||
}
|
||||
|
||||
if (op != OP_INV_IC) {
|
||||
/*
|
||||
* Flush / Invalidate is provided by DC_CTRL.RNG_OP 0 or 1
|
||||
* combined Flush-n-invalidate uses DC_CTRL.IM = 1 set above
|
||||
*/
|
||||
val &= ~DC_CTRL_RGN_OP_MSK;
|
||||
if (op & OP_INV)
|
||||
val |= DC_CTRL_RGN_OP_INV;
|
||||
}
|
||||
write_aux_reg(ctl, val);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
static inline void __after_dc_op(const int op)
|
||||
{
|
||||
if (op & OP_FLUSH) {
|
||||
|
|
@ -486,13 +569,14 @@ static void __dc_enable(void)
|
|||
static inline void __dc_line_op(phys_addr_t paddr, unsigned long vaddr,
|
||||
unsigned long sz, const int op)
|
||||
{
|
||||
const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
__before_dc_op(op);
|
||||
|
||||
__cache_line_loop(paddr, vaddr, sz, op);
|
||||
__cache_line_loop(paddr, vaddr, sz, op, full_page);
|
||||
|
||||
__after_dc_op(op);
|
||||
|
||||
|
|
@ -521,10 +605,11 @@ static inline void
|
|||
__ic_line_inv_vaddr_local(phys_addr_t paddr, unsigned long vaddr,
|
||||
unsigned long sz)
|
||||
{
|
||||
const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
(*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC);
|
||||
(*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC, full_page);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -419,7 +419,7 @@ typedef struct elf64_shdr {
|
|||
#define NT_METAG_CBUF 0x500 /* Metag catch buffer registers */
|
||||
#define NT_METAG_RPIPE 0x501 /* Metag read pipeline state */
|
||||
#define NT_METAG_TLS 0x502 /* Metag TLS pointer */
|
||||
|
||||
#define NT_ARC_V2 0x600 /* ARCv2 accumulator/extra registers */
|
||||
|
||||
/* Note header in a PT_NOTE section */
|
||||
typedef struct elf32_note {
|
||||
|
|
|
|||
Loading…
Reference in New Issue