Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf fixes from Ingo Molnar:
"Tooling fixes, plus add missing interval sampling to certain x86 PEBS
events"
* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf tools: Add trace/beauty/generated/ into .gitignore
perf trace: Fix call-graph output
x86/events/intel/ds: Add PERF_SAMPLE_PERIOD into PEBS_FREERUNNING_FLAGS
perf record: Fix period option handling
perf evsel: Fix period/freq terms setup
tools headers: Synchoronize x86 features UAPI headers
tools headers: Synchronize uapi/linux/sched.h
tools headers: Sync {tools/,}arch/powerpc/include/uapi/asm/kvm.h
tooling headers: Synchronize updated s390 kvm UAPI headers
tools headers: Synchronize sound/asound.h
This commit is contained in:
Linus Torvalds
commit
4b0dda4f86
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@ -93,7 +93,8 @@ struct amd_nb {
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PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
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PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
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PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \
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PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER)
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PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \
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PERF_SAMPLE_PERIOD)
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#define PEBS_REGS \
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(PERF_REG_X86_AX | \
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@ -443,6 +443,31 @@ struct kvm_ppc_rmmu_info {
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__u32 ap_encodings[8];
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};
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/* For KVM_PPC_GET_CPU_CHAR */
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struct kvm_ppc_cpu_char {
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__u64 character; /* characteristics of the CPU */
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__u64 behaviour; /* recommended software behaviour */
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__u64 character_mask; /* valid bits in character */
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__u64 behaviour_mask; /* valid bits in behaviour */
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};
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/*
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* Values for character and character_mask.
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* These are identical to the values used by H_GET_CPU_CHARACTERISTICS.
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*/
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#define KVM_PPC_CPU_CHAR_SPEC_BAR_ORI31 (1ULL << 63)
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#define KVM_PPC_CPU_CHAR_BCCTRL_SERIALISED (1ULL << 62)
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#define KVM_PPC_CPU_CHAR_L1D_FLUSH_ORI30 (1ULL << 61)
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#define KVM_PPC_CPU_CHAR_L1D_FLUSH_TRIG2 (1ULL << 60)
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#define KVM_PPC_CPU_CHAR_L1D_THREAD_PRIV (1ULL << 59)
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#define KVM_PPC_CPU_CHAR_BR_HINT_HONOURED (1ULL << 58)
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#define KVM_PPC_CPU_CHAR_MTTRIG_THR_RECONF (1ULL << 57)
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#define KVM_PPC_CPU_CHAR_COUNT_CACHE_DIS (1ULL << 56)
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#define KVM_PPC_CPU_BEHAV_FAVOUR_SECURITY (1ULL << 63)
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#define KVM_PPC_CPU_BEHAV_L1D_FLUSH_PR (1ULL << 62)
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#define KVM_PPC_CPU_BEHAV_BNDS_CHK_SPEC_BAR (1ULL << 61)
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/* Per-vcpu XICS interrupt controller state */
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#define KVM_REG_PPC_ICP_STATE (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c)
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@ -224,6 +224,7 @@ struct kvm_guest_debug_arch {
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#define KVM_SYNC_RICCB (1UL << 7)
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#define KVM_SYNC_FPRS (1UL << 8)
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#define KVM_SYNC_GSCB (1UL << 9)
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#define KVM_SYNC_BPBC (1UL << 10)
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/* length and alignment of the sdnx as a power of two */
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#define SDNXC 8
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#define SDNXL (1UL << SDNXC)
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@ -247,7 +248,9 @@ struct kvm_sync_regs {
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};
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__u8 reserved[512]; /* for future vector expansion */
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__u32 fpc; /* valid on KVM_SYNC_VRS or KVM_SYNC_FPRS */
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__u8 padding1[52]; /* riccb needs to be 64byte aligned */
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__u8 bpbc : 1; /* bp mode */
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__u8 reserved2 : 7;
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__u8 padding1[51]; /* riccb needs to be 64byte aligned */
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__u8 riccb[64]; /* runtime instrumentation controls block */
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__u8 padding2[192]; /* sdnx needs to be 256byte aligned */
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union {
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@ -13,7 +13,7 @@
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/*
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* Defines x86 CPU feature bits
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*/
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#define NCAPINTS 18 /* N 32-bit words worth of info */
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#define NCAPINTS 19 /* N 32-bit words worth of info */
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#define NBUGINTS 1 /* N 32-bit bug flags */
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/*
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@ -203,12 +203,15 @@
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#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
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#define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */
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#define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */
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#define X86_FEATURE_RETPOLINE ( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
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#define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */
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#define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */
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#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
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#define X86_FEATURE_AVX512_4VNNIW ( 7*32+16) /* AVX-512 Neural Network Instructions */
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#define X86_FEATURE_AVX512_4FMAPS ( 7*32+17) /* AVX-512 Multiply Accumulation Single precision */
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#define X86_FEATURE_CDP_L2 ( 7*32+15) /* Code and Data Prioritization L2 */
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#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */
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#define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* "" Fill RSB on context switches */
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#define X86_FEATURE_USE_IBPB ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
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/* Virtualization flags: Linux defined, word 8 */
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#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
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@ -243,6 +246,7 @@
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#define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */
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#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */
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#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */
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#define X86_FEATURE_INTEL_PT ( 9*32+25) /* Intel Processor Trace */
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#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */
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#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */
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#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */
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@ -268,6 +272,9 @@
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#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
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#define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */
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#define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */
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#define X86_FEATURE_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */
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#define X86_FEATURE_IBRS (13*32+14) /* Indirect Branch Restricted Speculation */
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#define X86_FEATURE_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors */
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/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
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#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
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@ -316,6 +323,13 @@
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#define X86_FEATURE_SUCCOR (17*32+ 1) /* Uncorrectable error containment and recovery */
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#define X86_FEATURE_SMCA (17*32+ 3) /* Scalable MCA */
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
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#define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */
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#define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
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#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
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#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
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#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
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/*
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* BUG word(s)
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*/
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@ -342,5 +356,7 @@
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#define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */
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#define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */
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#define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */
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#define X86_BUG_SPECTRE_V1 X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */
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#define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */
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#endif /* _ASM_X86_CPUFEATURES_H */
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@ -77,6 +77,7 @@
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#define DISABLED_MASK15 0
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#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP)
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#define DISABLED_MASK17 0
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#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
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#define DISABLED_MASK18 0
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#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
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#endif /* _ASM_X86_DISABLED_FEATURES_H */
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@ -106,6 +106,7 @@
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#define REQUIRED_MASK15 0
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#define REQUIRED_MASK16 (NEED_LA57)
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#define REQUIRED_MASK17 0
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#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
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#define REQUIRED_MASK18 0
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#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
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#endif /* _ASM_X86_REQUIRED_FEATURES_H */
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@ -932,6 +932,8 @@ struct kvm_ppc_resize_hpt {
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#define KVM_CAP_HYPERV_SYNIC2 148
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#define KVM_CAP_HYPERV_VP_INDEX 149
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#define KVM_CAP_S390_AIS_MIGRATION 150
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#define KVM_CAP_PPC_GET_CPU_CHAR 151
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#define KVM_CAP_S390_BPB 152
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#ifdef KVM_CAP_IRQ_ROUTING
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@ -1261,6 +1263,8 @@ struct kvm_s390_ucas_mapping {
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#define KVM_PPC_CONFIGURE_V3_MMU _IOW(KVMIO, 0xaf, struct kvm_ppc_mmuv3_cfg)
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/* Available with KVM_CAP_PPC_RADIX_MMU */
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#define KVM_PPC_GET_RMMU_INFO _IOW(KVMIO, 0xb0, struct kvm_ppc_rmmu_info)
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/* Available with KVM_CAP_PPC_GET_CPU_CHAR */
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#define KVM_PPC_GET_CPU_CHAR _IOR(KVMIO, 0xb1, struct kvm_ppc_cpu_char)
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/* ioctl for vm fd */
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#define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device)
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@ -49,5 +49,10 @@
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*/
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#define SCHED_FLAG_RESET_ON_FORK 0x01
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#define SCHED_FLAG_RECLAIM 0x02
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#define SCHED_FLAG_DL_OVERRUN 0x04
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#define SCHED_FLAG_ALL (SCHED_FLAG_RESET_ON_FORK | \
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SCHED_FLAG_RECLAIM | \
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SCHED_FLAG_DL_OVERRUN)
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#endif /* _UAPI_LINUX_SCHED_H */
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@ -214,6 +214,11 @@ typedef int __bitwise snd_pcm_format_t;
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#define SNDRV_PCM_FORMAT_IMA_ADPCM ((__force snd_pcm_format_t) 22)
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#define SNDRV_PCM_FORMAT_MPEG ((__force snd_pcm_format_t) 23)
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#define SNDRV_PCM_FORMAT_GSM ((__force snd_pcm_format_t) 24)
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#define SNDRV_PCM_FORMAT_S20_LE ((__force snd_pcm_format_t) 25) /* in four bytes, LSB justified */
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#define SNDRV_PCM_FORMAT_S20_BE ((__force snd_pcm_format_t) 26) /* in four bytes, LSB justified */
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#define SNDRV_PCM_FORMAT_U20_LE ((__force snd_pcm_format_t) 27) /* in four bytes, LSB justified */
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#define SNDRV_PCM_FORMAT_U20_BE ((__force snd_pcm_format_t) 28) /* in four bytes, LSB justified */
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/* gap in the numbering for a future standard linear format */
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#define SNDRV_PCM_FORMAT_SPECIAL ((__force snd_pcm_format_t) 31)
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#define SNDRV_PCM_FORMAT_S24_3LE ((__force snd_pcm_format_t) 32) /* in three bytes */
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#define SNDRV_PCM_FORMAT_S24_3BE ((__force snd_pcm_format_t) 33) /* in three bytes */
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@ -248,6 +253,8 @@ typedef int __bitwise snd_pcm_format_t;
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#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_LE
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#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_LE
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#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE
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#define SNDRV_PCM_FORMAT_S20 SNDRV_PCM_FORMAT_S20_LE
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#define SNDRV_PCM_FORMAT_U20 SNDRV_PCM_FORMAT_U20_LE
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#endif
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#ifdef SNDRV_BIG_ENDIAN
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#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_BE
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@ -259,6 +266,8 @@ typedef int __bitwise snd_pcm_format_t;
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#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_BE
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#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_BE
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#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE
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#define SNDRV_PCM_FORMAT_S20 SNDRV_PCM_FORMAT_S20_BE
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#define SNDRV_PCM_FORMAT_U20 SNDRV_PCM_FORMAT_U20_BE
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#endif
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typedef int __bitwise snd_pcm_subformat_t;
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1
tools/perf/.gitignore
vendored
1
tools/perf/.gitignore
vendored
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@ -31,5 +31,6 @@ config.mak.autogen
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.config-detected
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util/intel-pt-decoder/inat-tables.c
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arch/*/include/generated/
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trace/beauty/generated/
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pmu-events/pmu-events.c
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pmu-events/jevents
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@ -1566,7 +1566,8 @@ static struct option __record_options[] = {
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OPT_BOOLEAN_SET('T', "timestamp", &record.opts.sample_time,
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&record.opts.sample_time_set,
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"Record the sample timestamps"),
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OPT_BOOLEAN('P', "period", &record.opts.period, "Record the sample period"),
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OPT_BOOLEAN_SET('P', "period", &record.opts.period, &record.opts.period_set,
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"Record the sample period"),
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OPT_BOOLEAN('n', "no-samples", &record.opts.no_samples,
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"don't sample"),
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OPT_BOOLEAN_SET('N', "no-buildid-cache", &record.no_buildid_cache,
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@ -1661,9 +1661,12 @@ static int trace__resolve_callchain(struct trace *trace, struct perf_evsel *evse
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struct callchain_cursor *cursor)
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{
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struct addr_location al;
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int max_stack = evsel->attr.sample_max_stack ?
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evsel->attr.sample_max_stack :
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trace->max_stack;
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if (machine__resolve(trace->host, &al, sample) < 0 ||
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thread__resolve_callchain(al.thread, cursor, evsel, sample, NULL, NULL, evsel->attr.sample_max_stack))
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thread__resolve_callchain(al.thread, cursor, evsel, sample, NULL, NULL, max_stack))
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return -1;
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return 0;
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@ -50,6 +50,7 @@ struct record_opts {
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bool sample_time_set;
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bool sample_cpu;
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bool period;
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bool period_set;
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bool running_time;
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bool full_auxtrace;
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bool auxtrace_snapshot_mode;
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@ -745,12 +745,14 @@ static void apply_config_terms(struct perf_evsel *evsel,
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if (!(term->weak && opts->user_interval != ULLONG_MAX)) {
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attr->sample_period = term->val.period;
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attr->freq = 0;
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perf_evsel__reset_sample_bit(evsel, PERIOD);
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}
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break;
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case PERF_EVSEL__CONFIG_TERM_FREQ:
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if (!(term->weak && opts->user_freq != UINT_MAX)) {
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attr->sample_freq = term->val.freq;
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attr->freq = 1;
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perf_evsel__set_sample_bit(evsel, PERIOD);
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}
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break;
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case PERF_EVSEL__CONFIG_TERM_TIME:
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@ -969,9 +971,6 @@ void perf_evsel__config(struct perf_evsel *evsel, struct record_opts *opts,
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if (target__has_cpu(&opts->target) || opts->sample_cpu)
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perf_evsel__set_sample_bit(evsel, CPU);
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if (opts->period)
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perf_evsel__set_sample_bit(evsel, PERIOD);
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/*
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* When the user explicitly disabled time don't force it here.
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*/
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@ -1073,6 +1072,14 @@ void perf_evsel__config(struct perf_evsel *evsel, struct record_opts *opts,
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apply_config_terms(evsel, opts, track);
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evsel->ignore_missing_thread = opts->ignore_missing_thread;
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/* The --period option takes the precedence. */
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if (opts->period_set) {
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if (opts->period)
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perf_evsel__set_sample_bit(evsel, PERIOD);
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else
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perf_evsel__reset_sample_bit(evsel, PERIOD);
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}
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}
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static int perf_evsel__alloc_fd(struct perf_evsel *evsel, int ncpus, int nthreads)
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||||
|
|
|
|||
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