ARM: ensure initial page tables are setup for SMP systems
Mapping the same memory using two different attributes (memory type, shareability, cacheability) is unpredictable. During boot, we encounter a situation when we're updating the kernel's page tables which can lead to dirty cache lines existing in the cache which are subsequently missed. This causes stack corruption, and therefore a crash. Therefore, ensure that the shared and cacheability settings matches the configuration that will be used later; this together with the restriction in early_cachepolicy() ensures that we won't create a mismatch during boot. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -117,6 +117,13 @@ static void __init early_cachepolicy(char **p)
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}
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}
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if (i == ARRAY_SIZE(cache_policies))
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if (i == ARRAY_SIZE(cache_policies))
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printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
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printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
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/*
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* This restriction is partly to do with the way we boot; it is
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* unpredictable to have memory mapped using two different sets of
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* memory attributes (shared, type, and cache attribs). We can not
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* change these attributes once the initial assembly has setup the
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* page tables.
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*/
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if (cpu_architecture() >= CPU_ARCH_ARMv6) {
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if (cpu_architecture() >= CPU_ARCH_ARMv6) {
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printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
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printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
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cachepolicy = CPOLICY_WRITEBACK;
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cachepolicy = CPOLICY_WRITEBACK;
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@ -32,8 +32,10 @@
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#ifndef CONFIG_SMP
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#ifndef CONFIG_SMP
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#define TTB_FLAGS TTB_RGN_WBWA
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#define TTB_FLAGS TTB_RGN_WBWA
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#define PMD_FLAGS PMD_SECT_WB
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#else
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#else
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#define TTB_FLAGS TTB_RGN_WBWA|TTB_S
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#define TTB_FLAGS TTB_RGN_WBWA|TTB_S
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#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S
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#endif
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#endif
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ENTRY(cpu_v6_proc_init)
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ENTRY(cpu_v6_proc_init)
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@ -222,10 +224,9 @@ __v6_proc_info:
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.long 0x0007b000
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.long 0x0007b000
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.long 0x0007f000
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.long 0x0007f000
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.long PMD_TYPE_SECT | \
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.long PMD_TYPE_SECT | \
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PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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PMD_SECT_AP_READ | \
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PMD_FLAGS
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.long PMD_TYPE_SECT | \
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.long PMD_TYPE_SECT | \
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PMD_SECT_XN | \
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PMD_SECT_XN | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_WRITE | \
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@ -33,9 +33,11 @@
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#ifndef CONFIG_SMP
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#ifndef CONFIG_SMP
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/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
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/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
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#define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB
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#define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB
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#define PMD_FLAGS PMD_SECT_WB
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#else
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#else
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/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
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/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
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#define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
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#define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
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#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S
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#endif
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#endif
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ENTRY(cpu_v7_proc_init)
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ENTRY(cpu_v7_proc_init)
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@ -326,10 +328,9 @@ __v7_proc_info:
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.long 0x000f0000 @ Required ID value
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.long 0x000f0000 @ Required ID value
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.long 0x000f0000 @ Mask for ID
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.long 0x000f0000 @ Mask for ID
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.long PMD_TYPE_SECT | \
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.long PMD_TYPE_SECT | \
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PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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PMD_SECT_AP_READ | \
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PMD_FLAGS
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.long PMD_TYPE_SECT | \
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.long PMD_TYPE_SECT | \
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PMD_SECT_XN | \
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PMD_SECT_XN | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_WRITE | \
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