Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: PCI: AMD 813x B2 devices do not need boot interrupt quirk PCI: Enable PCIe AER only after checking firmware support PCI: pciehp: Handle interrupts that happen during initialization. PCI: don't enable too many HT MSI mappings PCI: add some sysfs ABI docs PCI quirk: enable MSI on 8132
This commit is contained in:
commit
4bdc1b9650
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@ -1,3 +1,46 @@
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What: /sys/bus/pci/drivers/.../bind
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Date: December 2003
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Contact: linux-pci@vger.kernel.org
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Description:
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Writing a device location to this file will cause
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the driver to attempt to bind to the device found at
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this location. This is useful for overriding default
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bindings. The format for the location is: DDDD:BB:DD.F.
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That is Domain:Bus:Device.Function and is the same as
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found in /sys/bus/pci/devices/. For example:
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# echo 0000:00:19.0 > /sys/bus/pci/drivers/foo/bind
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(Note: kernels before 2.6.28 may require echo -n).
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What: /sys/bus/pci/drivers/.../unbind
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Date: December 2003
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Contact: linux-pci@vger.kernel.org
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Description:
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Writing a device location to this file will cause the
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driver to attempt to unbind from the device found at
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this location. This may be useful when overriding default
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bindings. The format for the location is: DDDD:BB:DD.F.
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That is Domain:Bus:Device.Function and is the same as
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found in /sys/bus/pci/devices/. For example:
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# echo 0000:00:19.0 > /sys/bus/pci/drivers/foo/unbind
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(Note: kernels before 2.6.28 may require echo -n).
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What: /sys/bus/pci/drivers/.../new_id
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Date: December 2003
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Contact: linux-pci@vger.kernel.org
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Description:
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Writing a device ID to this file will attempt to
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dynamically add a new device ID to a PCI device driver.
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This may allow the driver to support more hardware than
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was included in the driver's static device ID support
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table at compile time. The format for the device ID is:
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VVVV DDDD SVVV SDDD CCCC MMMM PPPP. That is Vendor ID,
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Device ID, Subsystem Vendor ID, Subsystem Device ID,
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Class, Class Mask, and Private Driver Data. The Vendor ID
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and Device ID fields are required, the rest are optional.
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Upon successfully adding an ID, the driver will probe
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for the device and attempt to bind to it. For example:
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# echo "8086 10f5" > /sys/bus/pci/drivers/foo/new_id
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What: /sys/bus/pci/devices/.../vpd
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Date: February 2008
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Contact: Ben Hutchings <bhutchings@solarflare.com>
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@ -111,6 +111,7 @@ struct controller {
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int cmd_busy;
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unsigned int no_cmd_complete:1;
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unsigned int link_active_reporting:1;
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unsigned int notification_enabled:1;
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};
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#define INT_BUTTON_IGNORE 0
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@ -170,6 +171,7 @@ extern int pciehp_configure_device(struct slot *p_slot);
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extern int pciehp_unconfigure_device(struct slot *p_slot);
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extern void pciehp_queue_pushbutton_work(struct work_struct *work);
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struct controller *pcie_init(struct pcie_device *dev);
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int pcie_init_notification(struct controller *ctrl);
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int pciehp_enable_slot(struct slot *p_slot);
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int pciehp_disable_slot(struct slot *p_slot);
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int pcie_enable_notification(struct controller *ctrl);
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@ -434,6 +434,13 @@ static int pciehp_probe(struct pcie_device *dev, const struct pcie_port_service_
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goto err_out_release_ctlr;
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}
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/* Enable events after we have setup the data structures */
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rc = pcie_init_notification(ctrl);
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if (rc) {
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ctrl_err(ctrl, "Notification initialization failed\n");
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goto err_out_release_ctlr;
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}
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/* Check if slot is occupied */
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t_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset);
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t_slot->hpc_ops->get_adapter_status(t_slot, &value);
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@ -934,7 +934,7 @@ static void pcie_disable_notification(struct controller *ctrl)
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ctrl_warn(ctrl, "Cannot disable software notification\n");
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}
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static int pcie_init_notification(struct controller *ctrl)
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int pcie_init_notification(struct controller *ctrl)
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{
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if (pciehp_request_irq(ctrl))
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return -1;
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@ -942,13 +942,17 @@ static int pcie_init_notification(struct controller *ctrl)
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pciehp_free_irq(ctrl);
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return -1;
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}
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ctrl->notification_enabled = 1;
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return 0;
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}
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static void pcie_shutdown_notification(struct controller *ctrl)
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{
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pcie_disable_notification(ctrl);
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pciehp_free_irq(ctrl);
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if (ctrl->notification_enabled) {
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pcie_disable_notification(ctrl);
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pciehp_free_irq(ctrl);
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ctrl->notification_enabled = 0;
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}
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}
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static int pcie_init_slot(struct controller *ctrl)
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if (pcie_init_slot(ctrl))
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goto abort_ctrl;
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if (pcie_init_notification(ctrl))
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goto abort_slot;
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return ctrl;
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abort_slot:
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pcie_cleanup_slot(ctrl);
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abort_ctrl:
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kfree(ctrl);
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abort:
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@ -108,6 +108,34 @@ int pci_cleanup_aer_correct_error_status(struct pci_dev *dev)
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}
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#endif /* 0 */
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static void set_device_error_reporting(struct pci_dev *dev, void *data)
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{
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bool enable = *((bool *)data);
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if (dev->pcie_type != PCIE_RC_PORT &&
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dev->pcie_type != PCIE_SW_UPSTREAM_PORT &&
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dev->pcie_type != PCIE_SW_DOWNSTREAM_PORT)
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return;
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if (enable)
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pci_enable_pcie_error_reporting(dev);
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else
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pci_disable_pcie_error_reporting(dev);
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}
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/**
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* set_downstream_devices_error_reporting - enable/disable the error reporting bits on the root port and its downstream ports.
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* @dev: pointer to root port's pci_dev data structure
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* @enable: true = enable error reporting, false = disable error reporting.
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*/
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static void set_downstream_devices_error_reporting(struct pci_dev *dev,
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bool enable)
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{
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set_device_error_reporting(dev, &enable);
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pci_walk_bus(dev->subordinate, set_device_error_reporting, &enable);
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}
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static int find_device_iter(struct device *device, void *data)
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{
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struct pci_dev *dev;
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pci_read_config_dword(pdev, aer_pos + PCI_ERR_UNCOR_STATUS, ®32);
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pci_write_config_dword(pdev, aer_pos + PCI_ERR_UNCOR_STATUS, reg32);
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/* Enable Root Port device reporting error itself */
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pci_read_config_word(pdev, pos+PCI_EXP_DEVCTL, ®16);
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reg16 = reg16 |
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PCI_EXP_DEVCTL_CERE |
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PCI_EXP_DEVCTL_NFERE |
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PCI_EXP_DEVCTL_FERE |
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PCI_EXP_DEVCTL_URRE;
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pci_write_config_word(pdev, pos+PCI_EXP_DEVCTL,
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reg16);
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/*
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* Enable error reporting for the root port device and downstream port
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* devices.
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*/
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set_downstream_devices_error_reporting(pdev, true);
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/* Enable Root Port's interrupt in response to error messages */
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pci_write_config_dword(pdev,
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u32 reg32;
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int pos;
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/*
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* Disable error reporting for the root port device and downstream port
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* devices.
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*/
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set_downstream_devices_error_reporting(pdev, false);
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
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/* Disable Root's interrupt in response to error messages */
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pci_write_config_dword(pdev, pos + PCI_ERR_ROOT_COMMAND, 0);
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@ -97,8 +97,6 @@ static int __devinit pcie_portdrv_probe (struct pci_dev *dev,
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pcie_portdrv_save_config(dev);
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pci_enable_pcie_error_reporting(dev);
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return 0;
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}
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@ -1584,6 +1584,7 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_
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*/
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#define AMD_813X_MISC 0x40
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#define AMD_813X_NOIOAMODE (1<<0)
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#define AMD_813X_REV_B2 0x13
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static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
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{
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if (noioapicquirk)
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return;
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if (dev->revision == AMD_813X_REV_B2)
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return;
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pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
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pci_config_dword &= ~AMD_813X_NOIOAMODE;
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@ -1981,7 +1984,6 @@ static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
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quirk_msi_ht_cap);
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/* The nVidia CK804 chipset may have 2 HT MSI mappings.
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* MSI are supported if the MSI capability set in any of these mappings.
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*/
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PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
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ht_enable_msi_mapping);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
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ht_enable_msi_mapping);
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/* The P5N32-SLI Premium motherboard from Asus has a problem with msi
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* for the MCP55 NIC. It is not yet determined whether the msi problem
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* also affects other devices. As for now, turn off msi for this device.
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@ -2048,10 +2053,100 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
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PCI_DEVICE_ID_NVIDIA_NVENET_15,
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nvenet_msi_disable);
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static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
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{
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struct pci_dev *host_bridge;
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int pos;
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int i, dev_no;
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int found = 0;
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dev_no = dev->devfn >> 3;
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for (i = dev_no; i >= 0; i--) {
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host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
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if (!host_bridge)
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continue;
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pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
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if (pos != 0) {
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found = 1;
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break;
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}
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pci_dev_put(host_bridge);
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}
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if (!found)
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return;
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/* root did that ! */
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if (msi_ht_cap_enabled(host_bridge))
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goto out;
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ht_enable_msi_mapping(dev);
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out:
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pci_dev_put(host_bridge);
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}
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static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
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{
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int pos, ttl = 48;
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pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
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while (pos && ttl--) {
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u8 flags;
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if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
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&flags) == 0) {
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dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
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pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
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flags & ~HT_MSI_FLAGS_ENABLE);
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}
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pos = pci_find_next_ht_capability(dev, pos,
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HT_CAPTYPE_MSI_MAPPING);
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}
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}
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static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
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{
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int pos, ttl = 48;
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int found = 0;
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/* check if there is HT MSI cap or enabled on this device */
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pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
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while (pos && ttl--) {
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u8 flags;
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if (found < 1)
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found = 1;
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if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
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&flags) == 0) {
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if (flags & HT_MSI_FLAGS_ENABLE) {
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if (found < 2) {
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found = 2;
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break;
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}
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}
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}
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pos = pci_find_next_ht_capability(dev, pos,
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HT_CAPTYPE_MSI_MAPPING);
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}
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return found;
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}
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static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
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{
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struct pci_dev *host_bridge;
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int pos, ttl = 48;
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int pos;
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int found;
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/* check if there is HT MSI cap or enabled on this device */
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found = ht_check_msi_mapping(dev);
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/* no HT MSI CAP */
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if (found == 0)
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return;
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/*
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* HT MSI mapping should be disabled on devices that are below
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@ -2067,24 +2162,19 @@ static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
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pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
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if (pos != 0) {
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/* Host bridge is to HT */
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ht_enable_msi_mapping(dev);
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if (found == 1) {
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/* it is not enabled, try to enable it */
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nv_ht_enable_msi_mapping(dev);
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}
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return;
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}
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/* Host bridge is not to HT, disable HT MSI mapping on this device */
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pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
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while (pos && ttl--) {
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u8 flags;
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/* HT MSI is not enabled */
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if (found == 1)
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return;
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if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
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&flags) == 0) {
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dev_info(&dev->dev, "Disabling HT MSI mapping");
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pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
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flags & ~HT_MSI_FLAGS_ENABLE);
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}
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pos = pci_find_next_ht_capability(dev, pos,
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HT_CAPTYPE_MSI_MAPPING);
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}
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/* Host bridge is not to HT, disable HT MSI mapping on this device */
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ht_disable_msi_mapping(dev);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk);
|
||||
|
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Loading…
Reference in a new issue