MIPS: perf: Add XLP support for hardware perf.
Add support for XLP performance counters register in perf. Update mips/Kconfig so that perf events can be selected for XLP. Signed-off-by: Zi Shen Lim <zlim@netlogicmicro.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4457 Signed-off-by: John Crispin <blogic@openwrt.org>
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@ -2186,7 +2186,7 @@ config NODES_SHIFT
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config HW_PERF_EVENTS
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bool "Enable hardware performance counter support for perf events"
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depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON)
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depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP)
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default y
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help
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Enable hardware performance counter support for perf events. If
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@ -840,6 +840,16 @@ static const struct mips_perf_event bmips5000_event_map
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[PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
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};
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static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = {
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[PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
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[PERF_COUNT_HW_INSTRUCTIONS] = { 0x18, CNTR_ALL }, /* PAPI_TOT_INS */
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[PERF_COUNT_HW_CACHE_REFERENCES] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
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[PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */
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[PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */
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[PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
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};
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/* 24K/34K/1004K cores can share the same cache event map. */
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static const struct mips_perf_event mipsxxcore_cache_map
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[PERF_COUNT_HW_CACHE_MAX]
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@ -1092,6 +1102,100 @@ static const struct mips_perf_event octeon_cache_map
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},
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};
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static const struct mips_perf_event xlp_cache_map
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
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[C(L1D)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { 0x31, CNTR_ALL }, /* PAPI_L1_DCR */
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[C(RESULT_MISS)] = { 0x30, CNTR_ALL }, /* PAPI_L1_LDM */
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */
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[C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(L1I)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
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[C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(LL)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { 0x35, CNTR_ALL }, /* PAPI_L2_DCR */
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[C(RESULT_MISS)] = { 0x37, CNTR_ALL }, /* PAPI_L2_LDM */
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */
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[C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(DTLB)] = {
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/*
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* Only general DTLB misses are counted use the same event for
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* read and write.
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*/
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(ITLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(BPU)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { 0x25, CNTR_ALL },
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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};
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#ifdef CONFIG_MIPS_MT_SMP
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static void check_and_calc_range(struct perf_event *event,
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const struct mips_perf_event *pev)
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@ -1444,6 +1548,20 @@ static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config)
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return &raw_event;
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}
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static const struct mips_perf_event *xlp_pmu_map_raw_event(u64 config)
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{
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unsigned int raw_id = config & 0xff;
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/* Only 1-63 are defined */
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if ((raw_id < 0x01) || (raw_id > 0x3f))
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return ERR_PTR(-EOPNOTSUPP);
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raw_event.cntr_mask = CNTR_ALL;
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raw_event.event_id = raw_id;
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return &raw_event;
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}
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static int __init
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init_hw_perf_events(void)
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{
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@ -1522,6 +1640,12 @@ init_hw_perf_events(void)
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mipspmu.general_event_map = &bmips5000_event_map;
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mipspmu.cache_event_map = &bmips5000_cache_map;
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break;
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case CPU_XLP:
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mipspmu.name = "xlp";
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mipspmu.general_event_map = &xlp_event_map;
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mipspmu.cache_event_map = &xlp_cache_map;
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mipspmu.map_raw_event = xlp_pmu_map_raw_event;
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break;
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default:
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pr_cont("Either hardware does not support performance "
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"counters, or not yet implemented.\n");
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