r8152: change the EEE definition
Replace the EEE definitions with the ones which is declared in "mdio.h". Chage some definitions to make them readable. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -22,6 +22,8 @@
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#include <linux/ip.h>
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#include <linux/ipv6.h>
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#include <net/ip6_checksum.h>
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#include <uapi/linux/mdio.h>
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#include <linux/mdio.h>
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/* Version Information */
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#define DRIVER_VERSION "v1.06.0 (2014/03/03)"
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@ -129,7 +131,7 @@
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#define OCP_SRAM_ADDR 0xa436
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#define OCP_SRAM_DATA 0xa438
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#define OCP_DOWN_SPEED 0xa442
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#define OCP_EEE_CFG2 0xa5d0
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#define OCP_EEE_ADV 0xa5d0
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#define OCP_ADC_CFG 0xbc06
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/* SRAM Register */
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@ -361,7 +363,7 @@
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#define EEE_NWAY_EN 0x1000
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#define TX_QUIET_EN 0x0200
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#define RX_QUIET_EN 0x0100
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#define SDRISETIME 0x0010 /* bit 4 ~ 6 */
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#define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
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#define RG_RXLPI_MSK_HFDUP 0x0008
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#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
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@ -373,7 +375,7 @@
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#define RG_EEEPRG_EN 0x0010
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/* OCP_EEE_CONFIG3 */
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#define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */
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#define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
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#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
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#define MSK_PH 0x0006 /* bit 0 ~ 3 */
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@ -382,11 +384,6 @@
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#define FUN_ADDR 0x0000
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#define FUN_DATA 0x4000
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/* bit[4:0] device addr */
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#define DEVICE_ADDR 0x0007
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/* OCP_EEE_DATA */
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#define EEE_ADDR 0x003C
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#define EEE_DATA 0x0002
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/* OCP_EEE_CFG */
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#define CTAP_SHORT_EN 0x0040
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@ -395,10 +392,6 @@
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/* OCP_DOWN_SPEED */
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#define EN_10M_BGOFF 0x0080
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/* OCP_EEE_CFG2 */
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#define MY1000_EEE 0x0004
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#define MY100_EEE 0x0002
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/* OCP_ADC_CFG */
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#define CKADSEL_L 0x0100
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#define ADC_EN 0x0080
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@ -2967,16 +2960,16 @@ static void r8152b_enable_eee(struct r8152 *tp)
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ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
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EEE_10_CAP | EEE_NWAY_EN |
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TX_QUIET_EN | RX_QUIET_EN |
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SDRISETIME | RG_RXLPI_MSK_HFDUP |
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sd_rise_time(1) | RG_RXLPI_MSK_HFDUP |
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SDFALLTIME);
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ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
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RG_LDVQUIET_EN | RG_CKRSEL |
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RG_EEEPRG_EN);
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ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
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ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
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ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
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ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
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ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
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ocp_reg_write(tp, OCP_EEE_CONFIG3, fast_snr(42) | RG_LFS_SEL | MSK_PH);
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ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | MDIO_MMD_AN);
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ocp_reg_write(tp, OCP_EEE_DATA, MDIO_AN_EEE_ADV);
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ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | MDIO_MMD_AN);
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ocp_reg_write(tp, OCP_EEE_DATA, MDIO_EEE_100TX);
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ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
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}
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@ -2991,9 +2984,9 @@ static void r8153_enable_eee(struct r8152 *tp)
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data = ocp_reg_read(tp, OCP_EEE_CFG);
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data |= EEE10_EN;
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ocp_reg_write(tp, OCP_EEE_CFG, data);
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data = ocp_reg_read(tp, OCP_EEE_CFG2);
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data |= MY1000_EEE | MY100_EEE;
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ocp_reg_write(tp, OCP_EEE_CFG2, data);
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data = ocp_reg_read(tp, OCP_EEE_ADV);
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data |= MDIO_EEE_1000T | MDIO_EEE_100TX;
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ocp_reg_write(tp, OCP_EEE_ADV, data);
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}
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static void r8152b_enable_fc(struct r8152 *tp)
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