Merge branches 'clk-remove-asm-clkdev', 'clk-debugfs-fixes', 'clk-renesas' and 'clk-meson' into clk-next
* clk-remove-asm-clkdev: clk: Move __clk_{get,put}() into private clk.h API clk: sunxi: Use CLK_IS_CRITICAL flag for critical clks arch: Remove clkdev.h asm-generic from Kbuild clk: Prepare to remove asm-generic/clkdev.h blackfin: Use generic clkdev.h header * clk-debugfs-fixes: clk: Simplify debugfs registration clk: Fix debugfs_create_*() usage clk: Show symbolic clock flags in debugfs clk: Improve flags doc for of_clk_detect_critical() * clk-renesas: clk: renesas: r8a7796: Add FDP clock clk: renesas: cpg-mssr: Keep wakeup sources active during system suspend clk: renesas: mstp: Keep wakeup sources active during system suspend clk: renesas: r8a77970: Add LVDS clock * clk-meson: clk: meson-axg: fix potential NULL dereference in axg_clkc_probe() clk: meson-axg: make local symbol axg_gp0_params_table static clk: meson-axg: fix return value check in axg_clkc_probe() clk: meson: mpll: use 64-bit maths in params_from_rate clk: meson-axg: add clock controller drivers clk: meson-axg: add clocks dt-bindings required header dt-bindings: clock: add compatible variant for the Meson-AXG clk: meson: make the spinlock naming more specific clk: meson: gxbb: remove IGNORE_UNUSED from mmc clocks clk: meson: gxbb: fix wrong clock for SARADC/SANA
This commit is contained in:
commit
4d1d13a5ae
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@ -5,8 +5,11 @@ controllers within the SoC.
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Required Properties:
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- compatible: should be "amlogic,gxbb-clkc" for GXBB SoC,
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or "amlogic,gxl-clkc" for GXL and GXM SoC.
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- compatible: should be:
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"amlogic,gxbb-clkc" for GXBB SoC,
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"amlogic,gxl-clkc" for GXL and GXM SoC,
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"amlogic,axg-clkc" for AXG SoC.
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- reg: physical base address of the clock controller and length of memory
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mapped region.
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@ -1,7 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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generic-y += clkdev.h
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generic-y += exec.h
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generic-y += export.h
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generic-y += fb.h
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|
|
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@ -1,6 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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generic-y += bugs.h
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generic-y += clkdev.h
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generic-y += device.h
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generic-y += div64.h
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generic-y += emergency-restart.h
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|
|
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@ -1,4 +1,3 @@
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generic-y += clkdev.h
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generic-y += current.h
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generic-y += early_ioremap.h
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generic-y += emergency-restart.h
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|
|
|
@ -105,6 +105,7 @@ config ARCH_MESON
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select PINCTRL_MESON
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select COMMON_CLK_AMLOGIC
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select COMMON_CLK_GXBB
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select COMMON_CLK_AXG
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select MESON_IRQ_GPIO
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help
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This enables support for the Amlogic S905 SoCs.
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|
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@ -1,5 +1,4 @@
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generic-y += bugs.h
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generic-y += clkdev.h
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generic-y += delay.h
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generic-y += div64.h
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generic-y += dma.h
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|
|
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@ -1,17 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_CLKDEV__H_
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#define __ASM_CLKDEV__H_
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#include <linux/slab.h>
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static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
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{
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return kzalloc(size, GFP_KERNEL);
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}
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#ifndef CONFIG_COMMON_CLK
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#define __clk_put(clk)
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#define __clk_get(clk) ({ 1; })
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#endif
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#endif
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@ -1,7 +1,6 @@
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generic-y += atomic.h
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generic-y += barrier.h
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generic-y += bugs.h
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generic-y += clkdev.h
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generic-y += current.h
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generic-y += device.h
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generic-y += div64.h
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|
|
|
@ -1,6 +1,5 @@
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generic-y += atomic.h
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generic-y += barrier.h
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generic-y += clkdev.h
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generic-y += cmpxchg.h
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generic-y += current.h
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generic-y += device.h
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|
|
|
@ -1,5 +1,4 @@
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generic-y += clkdev.h
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generic-y += device.h
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generic-y += exec.h
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generic-y += extable.h
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|
|
|
@ -3,7 +3,6 @@ generic-y += barrier.h
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generic-y += bugs.h
|
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generic-y += cacheflush.h
|
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generic-y += checksum.h
|
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generic-y += clkdev.h
|
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generic-y += current.h
|
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generic-y += delay.h
|
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generic-y += device.h
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|
|
|
@ -2,7 +2,6 @@
|
|||
generic-y += barrier.h
|
||||
generic-y += bug.h
|
||||
generic-y += bugs.h
|
||||
generic-y += clkdev.h
|
||||
generic-y += current.h
|
||||
generic-y += device.h
|
||||
generic-y += div64.h
|
||||
|
|
|
@ -1,4 +1,3 @@
|
|||
generic-y += clkdev.h
|
||||
generic-y += exec.h
|
||||
generic-y += irq_work.h
|
||||
generic-y += mcs_spinlock.h
|
||||
|
|
|
@ -1,4 +1,3 @@
|
|||
generic-y += clkdev.h
|
||||
generic-y += current.h
|
||||
generic-y += exec.h
|
||||
generic-y += extable.h
|
||||
|
|
|
@ -1,5 +1,4 @@
|
|||
generic-y += barrier.h
|
||||
generic-y += clkdev.h
|
||||
generic-y += device.h
|
||||
generic-y += emergency-restart.h
|
||||
generic-y += exec.h
|
||||
|
|
|
@ -1,5 +1,4 @@
|
|||
generic-y += bugs.h
|
||||
generic-y += clkdev.h
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||||
generic-y += current.h
|
||||
generic-y += device.h
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||||
generic-y += dma.h
|
||||
|
|
|
@ -2,7 +2,6 @@ generic-y += barrier.h
|
|||
generic-y += bitops.h
|
||||
generic-y += bug.h
|
||||
generic-y += bugs.h
|
||||
generic-y += clkdev.h
|
||||
generic-y += device.h
|
||||
generic-y += div64.h
|
||||
generic-y += emergency-restart.h
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||||
|
|
|
@ -1,6 +1,5 @@
|
|||
# MIPS headers
|
||||
generic-(CONFIG_GENERIC_CSUM) += checksum.h
|
||||
generic-y += clkdev.h
|
||||
generic-y += current.h
|
||||
generic-y += dma-contiguous.h
|
||||
generic-y += emergency-restart.h
|
||||
|
|
|
@ -1,6 +1,5 @@
|
|||
|
||||
generic-y += barrier.h
|
||||
generic-y += clkdev.h
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||||
generic-y += device.h
|
||||
generic-y += exec.h
|
||||
generic-y += extable.h
|
||||
|
|
|
@ -3,7 +3,6 @@ generic-y += barrier.h
|
|||
generic-y += bitops.h
|
||||
generic-y += bug.h
|
||||
generic-y += bugs.h
|
||||
generic-y += clkdev.h
|
||||
generic-y += cmpxchg.h
|
||||
generic-y += current.h
|
||||
generic-y += device.h
|
||||
|
|
|
@ -2,7 +2,6 @@ generic-y += barrier.h
|
|||
generic-y += bug.h
|
||||
generic-y += bugs.h
|
||||
generic-y += checksum.h
|
||||
generic-y += clkdev.h
|
||||
generic-y += current.h
|
||||
generic-y += device.h
|
||||
generic-y += div64.h
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||||
|
|
|
@ -1,5 +1,4 @@
|
|||
generic-y += barrier.h
|
||||
generic-y += clkdev.h
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||||
generic-y += current.h
|
||||
generic-y += device.h
|
||||
generic-y += div64.h
|
||||
|
|
|
@ -1,4 +1,3 @@
|
|||
generic-y += clkdev.h
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||||
generic-y += div64.h
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||||
generic-y += export.h
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||||
generic-y += irq_regs.h
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||||
|
|
|
@ -1,7 +1,6 @@
|
|||
generic-y += bugs.h
|
||||
generic-y += cacheflush.h
|
||||
generic-y += checksum.h
|
||||
generic-y += clkdev.h
|
||||
generic-y += cputime.h
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||||
generic-y += device.h
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||||
generic-y += div64.h
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||||
|
|
|
@ -1,6 +1,5 @@
|
|||
generic-y += asm-offsets.h
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||||
generic-y += cacheflush.h
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||||
generic-y += clkdev.h
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||||
generic-y += device.h
|
||||
generic-y += dma-contiguous.h
|
||||
generic-y += div64.h
|
||||
|
|
|
@ -1,5 +1,4 @@
|
|||
generic-y += barrier.h
|
||||
generic-y += clkdev.h
|
||||
generic-y += current.h
|
||||
generic-y += extable.h
|
||||
generic-y += irq_work.h
|
||||
|
|
|
@ -1,4 +1,3 @@
|
|||
generic-y += clkdev.h
|
||||
generic-y += current.h
|
||||
generic-y += delay.h
|
||||
generic-y += div64.h
|
||||
|
|
|
@ -1,7 +1,6 @@
|
|||
# User exported sparc header files
|
||||
|
||||
|
||||
generic-y += clkdev.h
|
||||
generic-y += div64.h
|
||||
generic-y += emergency-restart.h
|
||||
generic-y += exec.h
|
||||
|
|
|
@ -1,6 +1,5 @@
|
|||
generic-y += bug.h
|
||||
generic-y += bugs.h
|
||||
generic-y += clkdev.h
|
||||
generic-y += emergency-restart.h
|
||||
generic-y += exec.h
|
||||
generic-y += extable.h
|
||||
|
|
|
@ -1,6 +1,5 @@
|
|||
generic-y += barrier.h
|
||||
generic-y += bug.h
|
||||
generic-y += clkdev.h
|
||||
generic-y += current.h
|
||||
generic-y += delay.h
|
||||
generic-y += device.h
|
||||
|
|
|
@ -1,6 +1,5 @@
|
|||
generic-y += atomic.h
|
||||
generic-y += bugs.h
|
||||
generic-y += clkdev.h
|
||||
generic-y += current.h
|
||||
generic-y += device.h
|
||||
generic-y += div64.h
|
||||
|
|
|
@ -6,7 +6,6 @@ generated-y += unistd_32_ia32.h
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|||
generated-y += unistd_64_x32.h
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||||
generated-y += xen-hypercalls.h
|
||||
|
||||
generic-y += clkdev.h
|
||||
generic-y += dma-contiguous.h
|
||||
generic-y += early_ioremap.h
|
||||
generic-y += mcs_spinlock.h
|
||||
|
|
|
@ -1,5 +1,4 @@
|
|||
generic-y += bug.h
|
||||
generic-y += clkdev.h
|
||||
generic-y += device.h
|
||||
generic-y += div64.h
|
||||
generic-y += dma-contiguous.h
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
#include <linux/pm_runtime.h>
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#include <linux/sched.h>
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||||
#include <linux/clkdev.h>
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||||
#include <linux/stringify.h>
|
||||
|
||||
#include "clk.h"
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||||
|
||||
|
@ -2559,6 +2560,58 @@ static const struct file_operations clk_dump_fops = {
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|||
.release = single_release,
|
||||
};
|
||||
|
||||
static const struct {
|
||||
unsigned long flag;
|
||||
const char *name;
|
||||
} clk_flags[] = {
|
||||
#define ENTRY(f) { f, __stringify(f) }
|
||||
ENTRY(CLK_SET_RATE_GATE),
|
||||
ENTRY(CLK_SET_PARENT_GATE),
|
||||
ENTRY(CLK_SET_RATE_PARENT),
|
||||
ENTRY(CLK_IGNORE_UNUSED),
|
||||
ENTRY(CLK_IS_BASIC),
|
||||
ENTRY(CLK_GET_RATE_NOCACHE),
|
||||
ENTRY(CLK_SET_RATE_NO_REPARENT),
|
||||
ENTRY(CLK_GET_ACCURACY_NOCACHE),
|
||||
ENTRY(CLK_RECALC_NEW_RATES),
|
||||
ENTRY(CLK_SET_RATE_UNGATE),
|
||||
ENTRY(CLK_IS_CRITICAL),
|
||||
ENTRY(CLK_OPS_PARENT_ENABLE),
|
||||
#undef ENTRY
|
||||
};
|
||||
|
||||
static int clk_flags_dump(struct seq_file *s, void *data)
|
||||
{
|
||||
struct clk_core *core = s->private;
|
||||
unsigned long flags = core->flags;
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; flags && i < ARRAY_SIZE(clk_flags); i++) {
|
||||
if (flags & clk_flags[i].flag) {
|
||||
seq_printf(s, "%s\n", clk_flags[i].name);
|
||||
flags &= ~clk_flags[i].flag;
|
||||
}
|
||||
}
|
||||
if (flags) {
|
||||
/* Unknown flags */
|
||||
seq_printf(s, "0x%lx\n", flags);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clk_flags_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, clk_flags_dump, inode->i_private);
|
||||
}
|
||||
|
||||
static const struct file_operations clk_flags_fops = {
|
||||
.open = clk_flags_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static int possible_parents_dump(struct seq_file *s, void *data)
|
||||
{
|
||||
struct clk_core *core = s->private;
|
||||
|
@ -2600,48 +2653,46 @@ static int clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
|
|||
|
||||
core->dentry = d;
|
||||
|
||||
d = debugfs_create_u32("clk_rate", S_IRUGO, core->dentry,
|
||||
(u32 *)&core->rate);
|
||||
d = debugfs_create_ulong("clk_rate", 0444, core->dentry, &core->rate);
|
||||
if (!d)
|
||||
goto err_out;
|
||||
|
||||
d = debugfs_create_u32("clk_accuracy", S_IRUGO, core->dentry,
|
||||
(u32 *)&core->accuracy);
|
||||
d = debugfs_create_ulong("clk_accuracy", 0444, core->dentry,
|
||||
&core->accuracy);
|
||||
if (!d)
|
||||
goto err_out;
|
||||
|
||||
d = debugfs_create_u32("clk_phase", S_IRUGO, core->dentry,
|
||||
(u32 *)&core->phase);
|
||||
d = debugfs_create_u32("clk_phase", 0444, core->dentry, &core->phase);
|
||||
if (!d)
|
||||
goto err_out;
|
||||
|
||||
d = debugfs_create_x32("clk_flags", S_IRUGO, core->dentry,
|
||||
(u32 *)&core->flags);
|
||||
d = debugfs_create_file("clk_flags", 0444, core->dentry, core,
|
||||
&clk_flags_fops);
|
||||
if (!d)
|
||||
goto err_out;
|
||||
|
||||
d = debugfs_create_u32("clk_prepare_count", S_IRUGO, core->dentry,
|
||||
(u32 *)&core->prepare_count);
|
||||
d = debugfs_create_u32("clk_prepare_count", 0444, core->dentry,
|
||||
&core->prepare_count);
|
||||
if (!d)
|
||||
goto err_out;
|
||||
|
||||
d = debugfs_create_u32("clk_enable_count", S_IRUGO, core->dentry,
|
||||
(u32 *)&core->enable_count);
|
||||
d = debugfs_create_u32("clk_enable_count", 0444, core->dentry,
|
||||
&core->enable_count);
|
||||
if (!d)
|
||||
goto err_out;
|
||||
|
||||
d = debugfs_create_u32("clk_protect_count", S_IRUGO, core->dentry,
|
||||
(u32 *)&core->protect_count);
|
||||
d = debugfs_create_u32("clk_protect_count", 0444, core->dentry,
|
||||
&core->protect_count);
|
||||
if (!d)
|
||||
goto err_out;
|
||||
|
||||
d = debugfs_create_u32("clk_notifier_count", S_IRUGO, core->dentry,
|
||||
(u32 *)&core->notifier_count);
|
||||
d = debugfs_create_u32("clk_notifier_count", 0444, core->dentry,
|
||||
&core->notifier_count);
|
||||
if (!d)
|
||||
goto err_out;
|
||||
|
||||
if (core->num_parents > 1) {
|
||||
d = debugfs_create_file("clk_possible_parents", S_IRUGO,
|
||||
d = debugfs_create_file("clk_possible_parents", 0444,
|
||||
core->dentry, core, &possible_parents_fops);
|
||||
if (!d)
|
||||
goto err_out;
|
||||
|
@ -2677,12 +2728,8 @@ static int clk_debug_register(struct clk_core *core)
|
|||
|
||||
mutex_lock(&clk_debug_lock);
|
||||
hlist_add_head(&core->debug_node, &clk_debug_list);
|
||||
|
||||
if (!inited)
|
||||
goto unlock;
|
||||
|
||||
ret = clk_debug_create_one(core, rootdir);
|
||||
unlock:
|
||||
if (inited)
|
||||
ret = clk_debug_create_one(core, rootdir);
|
||||
mutex_unlock(&clk_debug_lock);
|
||||
|
||||
return ret;
|
||||
|
@ -2737,22 +2784,22 @@ static int __init clk_debug_init(void)
|
|||
if (!rootdir)
|
||||
return -ENOMEM;
|
||||
|
||||
d = debugfs_create_file("clk_summary", S_IRUGO, rootdir, &all_lists,
|
||||
d = debugfs_create_file("clk_summary", 0444, rootdir, &all_lists,
|
||||
&clk_summary_fops);
|
||||
if (!d)
|
||||
return -ENOMEM;
|
||||
|
||||
d = debugfs_create_file("clk_dump", S_IRUGO, rootdir, &all_lists,
|
||||
d = debugfs_create_file("clk_dump", 0444, rootdir, &all_lists,
|
||||
&clk_dump_fops);
|
||||
if (!d)
|
||||
return -ENOMEM;
|
||||
|
||||
d = debugfs_create_file("clk_orphan_summary", S_IRUGO, rootdir,
|
||||
d = debugfs_create_file("clk_orphan_summary", 0444, rootdir,
|
||||
&orphan_list, &clk_summary_fops);
|
||||
if (!d)
|
||||
return -ENOMEM;
|
||||
|
||||
d = debugfs_create_file("clk_orphan_dump", S_IRUGO, rootdir,
|
||||
d = debugfs_create_file("clk_orphan_dump", 0444, rootdir,
|
||||
&orphan_list, &clk_dump_fops);
|
||||
if (!d)
|
||||
return -ENOMEM;
|
||||
|
@ -3927,7 +3974,7 @@ static int parent_ready(struct device_node *np)
|
|||
* of_clk_detect_critical() - set CLK_IS_CRITICAL flag from Device Tree
|
||||
* @np: Device node pointer associated with clock provider
|
||||
* @index: clock index
|
||||
* @flags: pointer to clk_core->flags
|
||||
* @flags: pointer to top-level framework flags
|
||||
*
|
||||
* Detects if the clock-critical property exists and, if so, sets the
|
||||
* corresponding CLK_IS_CRITICAL flag.
|
||||
|
|
|
@ -20,6 +20,8 @@ struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
|
|||
struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
|
||||
const char *con_id);
|
||||
void __clk_free_clk(struct clk *clk);
|
||||
int __clk_get(struct clk *clk);
|
||||
void __clk_put(struct clk *clk);
|
||||
#else
|
||||
/* All these casts to avoid ifdefs in clkdev... */
|
||||
static inline struct clk *
|
||||
|
@ -32,5 +34,7 @@ static struct clk_hw *__clk_get_hw(struct clk *clk)
|
|||
{
|
||||
return (struct clk_hw *)clk;
|
||||
}
|
||||
static inline int __clk_get(struct clk *clk) { return 1; }
|
||||
static inline void __clk_put(struct clk *clk) { }
|
||||
|
||||
#endif
|
||||
|
|
|
@ -256,7 +256,7 @@ vclkdev_alloc(struct clk_hw *hw, const char *con_id, const char *dev_fmt,
|
|||
{
|
||||
struct clk_lookup_alloc *cla;
|
||||
|
||||
cla = __clkdev_alloc(sizeof(*cla));
|
||||
cla = kzalloc(sizeof(*cla), GFP_KERNEL);
|
||||
if (!cla)
|
||||
return NULL;
|
||||
|
||||
|
|
|
@ -19,3 +19,11 @@ config COMMON_CLK_GXBB
|
|||
help
|
||||
Support for the clock controller on AmLogic S905 devices, aka gxbb.
|
||||
Say Y if you want peripherals and CPU frequency scaling to work.
|
||||
|
||||
config COMMON_CLK_AXG
|
||||
bool
|
||||
depends on COMMON_CLK_AMLOGIC
|
||||
select RESET_CONTROLLER
|
||||
help
|
||||
Support for the clock controller on AmLogic A113D devices, aka axg.
|
||||
Say Y if you want peripherals and CPU frequency scaling to work.
|
||||
|
|
|
@ -5,3 +5,4 @@
|
|||
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o
|
||||
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
|
||||
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-regmap.o gxbb-aoclk-32k.o
|
||||
obj-$(CONFIG_COMMON_CLK_AXG) += axg.o
|
||||
|
|
938
drivers/clk/meson/axg.c
Normal file
938
drivers/clk/meson/axg.c
Normal file
|
@ -0,0 +1,938 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* AmLogic Meson-AXG Clock Controller Driver
|
||||
*
|
||||
* Copyright (c) 2016 Baylibre SAS.
|
||||
* Author: Michael Turquette <mturquette@baylibre.com>
|
||||
*
|
||||
* Copyright (c) 2017 Amlogic, inc.
|
||||
* Author: Qiufang Dai <qiufang.dai@amlogic.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include "clkc.h"
|
||||
#include "axg.h"
|
||||
|
||||
static DEFINE_SPINLOCK(meson_clk_lock);
|
||||
|
||||
static const struct pll_rate_table sys_pll_rate_table[] = {
|
||||
PLL_RATE(24000000, 56, 1, 2),
|
||||
PLL_RATE(48000000, 64, 1, 2),
|
||||
PLL_RATE(72000000, 72, 1, 2),
|
||||
PLL_RATE(96000000, 64, 1, 2),
|
||||
PLL_RATE(120000000, 80, 1, 2),
|
||||
PLL_RATE(144000000, 96, 1, 2),
|
||||
PLL_RATE(168000000, 56, 1, 1),
|
||||
PLL_RATE(192000000, 64, 1, 1),
|
||||
PLL_RATE(216000000, 72, 1, 1),
|
||||
PLL_RATE(240000000, 80, 1, 1),
|
||||
PLL_RATE(264000000, 88, 1, 1),
|
||||
PLL_RATE(288000000, 96, 1, 1),
|
||||
PLL_RATE(312000000, 52, 1, 2),
|
||||
PLL_RATE(336000000, 56, 1, 2),
|
||||
PLL_RATE(360000000, 60, 1, 2),
|
||||
PLL_RATE(384000000, 64, 1, 2),
|
||||
PLL_RATE(408000000, 68, 1, 2),
|
||||
PLL_RATE(432000000, 72, 1, 2),
|
||||
PLL_RATE(456000000, 76, 1, 2),
|
||||
PLL_RATE(480000000, 80, 1, 2),
|
||||
PLL_RATE(504000000, 84, 1, 2),
|
||||
PLL_RATE(528000000, 88, 1, 2),
|
||||
PLL_RATE(552000000, 92, 1, 2),
|
||||
PLL_RATE(576000000, 96, 1, 2),
|
||||
PLL_RATE(600000000, 50, 1, 1),
|
||||
PLL_RATE(624000000, 52, 1, 1),
|
||||
PLL_RATE(648000000, 54, 1, 1),
|
||||
PLL_RATE(672000000, 56, 1, 1),
|
||||
PLL_RATE(696000000, 58, 1, 1),
|
||||
PLL_RATE(720000000, 60, 1, 1),
|
||||
PLL_RATE(744000000, 62, 1, 1),
|
||||
PLL_RATE(768000000, 64, 1, 1),
|
||||
PLL_RATE(792000000, 66, 1, 1),
|
||||
PLL_RATE(816000000, 68, 1, 1),
|
||||
PLL_RATE(840000000, 70, 1, 1),
|
||||
PLL_RATE(864000000, 72, 1, 1),
|
||||
PLL_RATE(888000000, 74, 1, 1),
|
||||
PLL_RATE(912000000, 76, 1, 1),
|
||||
PLL_RATE(936000000, 78, 1, 1),
|
||||
PLL_RATE(960000000, 80, 1, 1),
|
||||
PLL_RATE(984000000, 82, 1, 1),
|
||||
PLL_RATE(1008000000, 84, 1, 1),
|
||||
PLL_RATE(1032000000, 86, 1, 1),
|
||||
PLL_RATE(1056000000, 88, 1, 1),
|
||||
PLL_RATE(1080000000, 90, 1, 1),
|
||||
PLL_RATE(1104000000, 92, 1, 1),
|
||||
PLL_RATE(1128000000, 94, 1, 1),
|
||||
PLL_RATE(1152000000, 96, 1, 1),
|
||||
PLL_RATE(1176000000, 98, 1, 1),
|
||||
PLL_RATE(1200000000, 50, 1, 0),
|
||||
PLL_RATE(1224000000, 51, 1, 0),
|
||||
PLL_RATE(1248000000, 52, 1, 0),
|
||||
PLL_RATE(1272000000, 53, 1, 0),
|
||||
PLL_RATE(1296000000, 54, 1, 0),
|
||||
PLL_RATE(1320000000, 55, 1, 0),
|
||||
PLL_RATE(1344000000, 56, 1, 0),
|
||||
PLL_RATE(1368000000, 57, 1, 0),
|
||||
PLL_RATE(1392000000, 58, 1, 0),
|
||||
PLL_RATE(1416000000, 59, 1, 0),
|
||||
PLL_RATE(1440000000, 60, 1, 0),
|
||||
PLL_RATE(1464000000, 61, 1, 0),
|
||||
PLL_RATE(1488000000, 62, 1, 0),
|
||||
PLL_RATE(1512000000, 63, 1, 0),
|
||||
PLL_RATE(1536000000, 64, 1, 0),
|
||||
PLL_RATE(1560000000, 65, 1, 0),
|
||||
PLL_RATE(1584000000, 66, 1, 0),
|
||||
PLL_RATE(1608000000, 67, 1, 0),
|
||||
PLL_RATE(1632000000, 68, 1, 0),
|
||||
PLL_RATE(1656000000, 68, 1, 0),
|
||||
PLL_RATE(1680000000, 68, 1, 0),
|
||||
PLL_RATE(1704000000, 68, 1, 0),
|
||||
PLL_RATE(1728000000, 69, 1, 0),
|
||||
PLL_RATE(1752000000, 69, 1, 0),
|
||||
PLL_RATE(1776000000, 69, 1, 0),
|
||||
PLL_RATE(1800000000, 69, 1, 0),
|
||||
PLL_RATE(1824000000, 70, 1, 0),
|
||||
PLL_RATE(1848000000, 70, 1, 0),
|
||||
PLL_RATE(1872000000, 70, 1, 0),
|
||||
PLL_RATE(1896000000, 70, 1, 0),
|
||||
PLL_RATE(1920000000, 71, 1, 0),
|
||||
PLL_RATE(1944000000, 71, 1, 0),
|
||||
PLL_RATE(1968000000, 71, 1, 0),
|
||||
PLL_RATE(1992000000, 71, 1, 0),
|
||||
PLL_RATE(2016000000, 72, 1, 0),
|
||||
PLL_RATE(2040000000, 72, 1, 0),
|
||||
PLL_RATE(2064000000, 72, 1, 0),
|
||||
PLL_RATE(2088000000, 72, 1, 0),
|
||||
PLL_RATE(2112000000, 73, 1, 0),
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct meson_clk_pll axg_fixed_pll = {
|
||||
.m = {
|
||||
.reg_off = HHI_MPLL_CNTL,
|
||||
.shift = 0,
|
||||
.width = 9,
|
||||
},
|
||||
.n = {
|
||||
.reg_off = HHI_MPLL_CNTL,
|
||||
.shift = 9,
|
||||
.width = 5,
|
||||
},
|
||||
.od = {
|
||||
.reg_off = HHI_MPLL_CNTL,
|
||||
.shift = 16,
|
||||
.width = 2,
|
||||
},
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "fixed_pll",
|
||||
.ops = &meson_clk_pll_ro_ops,
|
||||
.parent_names = (const char *[]){ "xtal" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct meson_clk_pll axg_sys_pll = {
|
||||
.m = {
|
||||
.reg_off = HHI_SYS_PLL_CNTL,
|
||||
.shift = 0,
|
||||
.width = 9,
|
||||
},
|
||||
.n = {
|
||||
.reg_off = HHI_SYS_PLL_CNTL,
|
||||
.shift = 9,
|
||||
.width = 5,
|
||||
},
|
||||
.od = {
|
||||
.reg_off = HHI_SYS_PLL_CNTL,
|
||||
.shift = 10,
|
||||
.width = 2,
|
||||
},
|
||||
.rate_table = sys_pll_rate_table,
|
||||
.rate_count = ARRAY_SIZE(sys_pll_rate_table),
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sys_pll",
|
||||
.ops = &meson_clk_pll_ro_ops,
|
||||
.parent_names = (const char *[]){ "xtal" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
|
||||
PLL_RATE(240000000, 40, 1, 2),
|
||||
PLL_RATE(246000000, 41, 1, 2),
|
||||
PLL_RATE(252000000, 42, 1, 2),
|
||||
PLL_RATE(258000000, 43, 1, 2),
|
||||
PLL_RATE(264000000, 44, 1, 2),
|
||||
PLL_RATE(270000000, 45, 1, 2),
|
||||
PLL_RATE(276000000, 46, 1, 2),
|
||||
PLL_RATE(282000000, 47, 1, 2),
|
||||
PLL_RATE(288000000, 48, 1, 2),
|
||||
PLL_RATE(294000000, 49, 1, 2),
|
||||
PLL_RATE(300000000, 50, 1, 2),
|
||||
PLL_RATE(306000000, 51, 1, 2),
|
||||
PLL_RATE(312000000, 52, 1, 2),
|
||||
PLL_RATE(318000000, 53, 1, 2),
|
||||
PLL_RATE(324000000, 54, 1, 2),
|
||||
PLL_RATE(330000000, 55, 1, 2),
|
||||
PLL_RATE(336000000, 56, 1, 2),
|
||||
PLL_RATE(342000000, 57, 1, 2),
|
||||
PLL_RATE(348000000, 58, 1, 2),
|
||||
PLL_RATE(354000000, 59, 1, 2),
|
||||
PLL_RATE(360000000, 60, 1, 2),
|
||||
PLL_RATE(366000000, 61, 1, 2),
|
||||
PLL_RATE(372000000, 62, 1, 2),
|
||||
PLL_RATE(378000000, 63, 1, 2),
|
||||
PLL_RATE(384000000, 64, 1, 2),
|
||||
PLL_RATE(390000000, 65, 1, 3),
|
||||
PLL_RATE(396000000, 66, 1, 3),
|
||||
PLL_RATE(402000000, 67, 1, 3),
|
||||
PLL_RATE(408000000, 68, 1, 3),
|
||||
PLL_RATE(480000000, 40, 1, 1),
|
||||
PLL_RATE(492000000, 41, 1, 1),
|
||||
PLL_RATE(504000000, 42, 1, 1),
|
||||
PLL_RATE(516000000, 43, 1, 1),
|
||||
PLL_RATE(528000000, 44, 1, 1),
|
||||
PLL_RATE(540000000, 45, 1, 1),
|
||||
PLL_RATE(552000000, 46, 1, 1),
|
||||
PLL_RATE(564000000, 47, 1, 1),
|
||||
PLL_RATE(576000000, 48, 1, 1),
|
||||
PLL_RATE(588000000, 49, 1, 1),
|
||||
PLL_RATE(600000000, 50, 1, 1),
|
||||
PLL_RATE(612000000, 51, 1, 1),
|
||||
PLL_RATE(624000000, 52, 1, 1),
|
||||
PLL_RATE(636000000, 53, 1, 1),
|
||||
PLL_RATE(648000000, 54, 1, 1),
|
||||
PLL_RATE(660000000, 55, 1, 1),
|
||||
PLL_RATE(672000000, 56, 1, 1),
|
||||
PLL_RATE(684000000, 57, 1, 1),
|
||||
PLL_RATE(696000000, 58, 1, 1),
|
||||
PLL_RATE(708000000, 59, 1, 1),
|
||||
PLL_RATE(720000000, 60, 1, 1),
|
||||
PLL_RATE(732000000, 61, 1, 1),
|
||||
PLL_RATE(744000000, 62, 1, 1),
|
||||
PLL_RATE(756000000, 63, 1, 1),
|
||||
PLL_RATE(768000000, 64, 1, 1),
|
||||
PLL_RATE(780000000, 65, 1, 1),
|
||||
PLL_RATE(792000000, 66, 1, 1),
|
||||
PLL_RATE(804000000, 67, 1, 1),
|
||||
PLL_RATE(816000000, 68, 1, 1),
|
||||
PLL_RATE(960000000, 40, 1, 0),
|
||||
PLL_RATE(984000000, 41, 1, 0),
|
||||
PLL_RATE(1008000000, 42, 1, 0),
|
||||
PLL_RATE(1032000000, 43, 1, 0),
|
||||
PLL_RATE(1056000000, 44, 1, 0),
|
||||
PLL_RATE(1080000000, 45, 1, 0),
|
||||
PLL_RATE(1104000000, 46, 1, 0),
|
||||
PLL_RATE(1128000000, 47, 1, 0),
|
||||
PLL_RATE(1152000000, 48, 1, 0),
|
||||
PLL_RATE(1176000000, 49, 1, 0),
|
||||
PLL_RATE(1200000000, 50, 1, 0),
|
||||
PLL_RATE(1224000000, 51, 1, 0),
|
||||
PLL_RATE(1248000000, 52, 1, 0),
|
||||
PLL_RATE(1272000000, 53, 1, 0),
|
||||
PLL_RATE(1296000000, 54, 1, 0),
|
||||
PLL_RATE(1320000000, 55, 1, 0),
|
||||
PLL_RATE(1344000000, 56, 1, 0),
|
||||
PLL_RATE(1368000000, 57, 1, 0),
|
||||
PLL_RATE(1392000000, 58, 1, 0),
|
||||
PLL_RATE(1416000000, 59, 1, 0),
|
||||
PLL_RATE(1440000000, 60, 1, 0),
|
||||
PLL_RATE(1464000000, 61, 1, 0),
|
||||
PLL_RATE(1488000000, 62, 1, 0),
|
||||
PLL_RATE(1512000000, 63, 1, 0),
|
||||
PLL_RATE(1536000000, 64, 1, 0),
|
||||
PLL_RATE(1560000000, 65, 1, 0),
|
||||
PLL_RATE(1584000000, 66, 1, 0),
|
||||
PLL_RATE(1608000000, 67, 1, 0),
|
||||
PLL_RATE(1632000000, 68, 1, 0),
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct pll_params_table axg_gp0_params_table[] = {
|
||||
PLL_PARAM(HHI_GP0_PLL_CNTL, 0x40010250),
|
||||
PLL_PARAM(HHI_GP0_PLL_CNTL1, 0xc084a000),
|
||||
PLL_PARAM(HHI_GP0_PLL_CNTL2, 0xb75020be),
|
||||
PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a59a288),
|
||||
PLL_PARAM(HHI_GP0_PLL_CNTL4, 0xc000004d),
|
||||
PLL_PARAM(HHI_GP0_PLL_CNTL5, 0x00078000),
|
||||
};
|
||||
|
||||
static struct meson_clk_pll axg_gp0_pll = {
|
||||
.m = {
|
||||
.reg_off = HHI_GP0_PLL_CNTL,
|
||||
.shift = 0,
|
||||
.width = 9,
|
||||
},
|
||||
.n = {
|
||||
.reg_off = HHI_GP0_PLL_CNTL,
|
||||
.shift = 9,
|
||||
.width = 5,
|
||||
},
|
||||
.od = {
|
||||
.reg_off = HHI_GP0_PLL_CNTL,
|
||||
.shift = 16,
|
||||
.width = 2,
|
||||
},
|
||||
.params = {
|
||||
.params_table = axg_gp0_params_table,
|
||||
.params_count = ARRAY_SIZE(axg_gp0_params_table),
|
||||
.no_init_reset = true,
|
||||
.reset_lock_loop = true,
|
||||
},
|
||||
.rate_table = axg_gp0_pll_rate_table,
|
||||
.rate_count = ARRAY_SIZE(axg_gp0_pll_rate_table),
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gp0_pll",
|
||||
.ops = &meson_clk_pll_ops,
|
||||
.parent_names = (const char *[]){ "xtal" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
static struct clk_fixed_factor axg_fclk_div2 = {
|
||||
.mult = 1,
|
||||
.div = 2,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "fclk_div2",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "fixed_pll" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor axg_fclk_div3 = {
|
||||
.mult = 1,
|
||||
.div = 3,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "fclk_div3",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "fixed_pll" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor axg_fclk_div4 = {
|
||||
.mult = 1,
|
||||
.div = 4,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "fclk_div4",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "fixed_pll" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor axg_fclk_div5 = {
|
||||
.mult = 1,
|
||||
.div = 5,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "fclk_div5",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "fixed_pll" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor axg_fclk_div7 = {
|
||||
.mult = 1,
|
||||
.div = 7,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "fclk_div7",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "fixed_pll" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct meson_clk_mpll axg_mpll0 = {
|
||||
.sdm = {
|
||||
.reg_off = HHI_MPLL_CNTL7,
|
||||
.shift = 0,
|
||||
.width = 14,
|
||||
},
|
||||
.sdm_en = {
|
||||
.reg_off = HHI_MPLL_CNTL7,
|
||||
.shift = 15,
|
||||
.width = 1,
|
||||
},
|
||||
.n2 = {
|
||||
.reg_off = HHI_MPLL_CNTL7,
|
||||
.shift = 16,
|
||||
.width = 9,
|
||||
},
|
||||
.en = {
|
||||
.reg_off = HHI_MPLL_CNTL7,
|
||||
.shift = 14,
|
||||
.width = 1,
|
||||
},
|
||||
.ssen = {
|
||||
.reg_off = HHI_MPLL_CNTL,
|
||||
.shift = 25,
|
||||
.width = 1,
|
||||
},
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpll0",
|
||||
.ops = &meson_clk_mpll_ops,
|
||||
.parent_names = (const char *[]){ "fixed_pll" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct meson_clk_mpll axg_mpll1 = {
|
||||
.sdm = {
|
||||
.reg_off = HHI_MPLL_CNTL8,
|
||||
.shift = 0,
|
||||
.width = 14,
|
||||
},
|
||||
.sdm_en = {
|
||||
.reg_off = HHI_MPLL_CNTL8,
|
||||
.shift = 15,
|
||||
.width = 1,
|
||||
},
|
||||
.n2 = {
|
||||
.reg_off = HHI_MPLL_CNTL8,
|
||||
.shift = 16,
|
||||
.width = 9,
|
||||
},
|
||||
.en = {
|
||||
.reg_off = HHI_MPLL_CNTL8,
|
||||
.shift = 14,
|
||||
.width = 1,
|
||||
},
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpll1",
|
||||
.ops = &meson_clk_mpll_ops,
|
||||
.parent_names = (const char *[]){ "fixed_pll" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct meson_clk_mpll axg_mpll2 = {
|
||||
.sdm = {
|
||||
.reg_off = HHI_MPLL_CNTL9,
|
||||
.shift = 0,
|
||||
.width = 14,
|
||||
},
|
||||
.sdm_en = {
|
||||
.reg_off = HHI_MPLL_CNTL9,
|
||||
.shift = 15,
|
||||
.width = 1,
|
||||
},
|
||||
.n2 = {
|
||||
.reg_off = HHI_MPLL_CNTL9,
|
||||
.shift = 16,
|
||||
.width = 9,
|
||||
},
|
||||
.en = {
|
||||
.reg_off = HHI_MPLL_CNTL9,
|
||||
.shift = 14,
|
||||
.width = 1,
|
||||
},
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpll2",
|
||||
.ops = &meson_clk_mpll_ops,
|
||||
.parent_names = (const char *[]){ "fixed_pll" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct meson_clk_mpll axg_mpll3 = {
|
||||
.sdm = {
|
||||
.reg_off = HHI_MPLL3_CNTL0,
|
||||
.shift = 12,
|
||||
.width = 14,
|
||||
},
|
||||
.sdm_en = {
|
||||
.reg_off = HHI_MPLL3_CNTL0,
|
||||
.shift = 11,
|
||||
.width = 1,
|
||||
},
|
||||
.n2 = {
|
||||
.reg_off = HHI_MPLL3_CNTL0,
|
||||
.shift = 2,
|
||||
.width = 9,
|
||||
},
|
||||
.en = {
|
||||
.reg_off = HHI_MPLL3_CNTL0,
|
||||
.shift = 0,
|
||||
.width = 1,
|
||||
},
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpll3",
|
||||
.ops = &meson_clk_mpll_ops,
|
||||
.parent_names = (const char *[]){ "fixed_pll" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers
|
||||
* and should be modeled with their respective PLLs via the forthcoming
|
||||
* coordinated clock rates feature
|
||||
*/
|
||||
static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
|
||||
static const char * const clk81_parent_names[] = {
|
||||
"xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
|
||||
"fclk_div3", "fclk_div5"
|
||||
};
|
||||
|
||||
static struct clk_mux axg_mpeg_clk_sel = {
|
||||
.reg = (void *)HHI_MPEG_CLK_CNTL,
|
||||
.mask = 0x7,
|
||||
.shift = 12,
|
||||
.flags = CLK_MUX_READ_ONLY,
|
||||
.table = mux_table_clk81,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpeg_clk_sel",
|
||||
.ops = &clk_mux_ro_ops,
|
||||
.parent_names = clk81_parent_names,
|
||||
.num_parents = ARRAY_SIZE(clk81_parent_names),
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_divider axg_mpeg_clk_div = {
|
||||
.reg = (void *)HHI_MPEG_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpeg_clk_div",
|
||||
.ops = &clk_divider_ops,
|
||||
.parent_names = (const char *[]){ "mpeg_clk_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_gate axg_clk81 = {
|
||||
.reg = (void *)HHI_MPEG_CLK_CNTL,
|
||||
.bit_idx = 7,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "clk81",
|
||||
.ops = &clk_gate_ops,
|
||||
.parent_names = (const char *[]){ "mpeg_clk_div" },
|
||||
.num_parents = 1,
|
||||
.flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
|
||||
},
|
||||
};
|
||||
|
||||
static const char * const axg_sd_emmc_clk0_parent_names[] = {
|
||||
"xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
|
||||
|
||||
/*
|
||||
* Following these parent clocks, we should also have had mpll2, mpll3
|
||||
* and gp0_pll but these clocks are too precious to be used here. All
|
||||
* the necessary rates for MMC and NAND operation can be acheived using
|
||||
* xtal or fclk_div clocks
|
||||
*/
|
||||
};
|
||||
|
||||
/* SDcard clock */
|
||||
static struct clk_mux axg_sd_emmc_b_clk0_sel = {
|
||||
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
|
||||
.mask = 0x7,
|
||||
.shift = 25,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sd_emmc_b_clk0_sel",
|
||||
.ops = &clk_mux_ops,
|
||||
.parent_names = axg_sd_emmc_clk0_parent_names,
|
||||
.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_divider axg_sd_emmc_b_clk0_div = {
|
||||
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
|
||||
.shift = 16,
|
||||
.width = 7,
|
||||
.lock = &meson_clk_lock,
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sd_emmc_b_clk0_div",
|
||||
.ops = &clk_divider_ops,
|
||||
.parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_gate axg_sd_emmc_b_clk0 = {
|
||||
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
|
||||
.bit_idx = 23,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sd_emmc_b_clk0",
|
||||
.ops = &clk_gate_ops,
|
||||
.parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
/* EMMC/NAND clock */
|
||||
static struct clk_mux axg_sd_emmc_c_clk0_sel = {
|
||||
.reg = (void *)HHI_NAND_CLK_CNTL,
|
||||
.mask = 0x7,
|
||||
.shift = 9,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sd_emmc_c_clk0_sel",
|
||||
.ops = &clk_mux_ops,
|
||||
.parent_names = axg_sd_emmc_clk0_parent_names,
|
||||
.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_divider axg_sd_emmc_c_clk0_div = {
|
||||
.reg = (void *)HHI_NAND_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
.lock = &meson_clk_lock,
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sd_emmc_c_clk0_div",
|
||||
.ops = &clk_divider_ops,
|
||||
.parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_gate axg_sd_emmc_c_clk0 = {
|
||||
.reg = (void *)HHI_NAND_CLK_CNTL,
|
||||
.bit_idx = 7,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sd_emmc_c_clk0",
|
||||
.ops = &clk_gate_ops,
|
||||
.parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
/* Everything Else (EE) domain gates */
|
||||
static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
|
||||
static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
|
||||
static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
|
||||
static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
|
||||
static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
|
||||
static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
|
||||
static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
|
||||
static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
|
||||
static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
|
||||
static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
|
||||
static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
|
||||
static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
|
||||
static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
|
||||
static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
|
||||
static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);
|
||||
static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23);
|
||||
static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25);
|
||||
static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26);
|
||||
static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27);
|
||||
static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30);
|
||||
|
||||
static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0);
|
||||
static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3);
|
||||
static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16);
|
||||
static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20);
|
||||
static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21);
|
||||
static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22);
|
||||
static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23);
|
||||
static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26);
|
||||
static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29);
|
||||
static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30);
|
||||
static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31);
|
||||
|
||||
static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1);
|
||||
static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
|
||||
static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
|
||||
static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9);
|
||||
static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
|
||||
static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
|
||||
static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
|
||||
static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
|
||||
|
||||
/* Always On (AO) domain gates */
|
||||
|
||||
static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0);
|
||||
static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1);
|
||||
static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2);
|
||||
static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3);
|
||||
static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
|
||||
|
||||
/* Array of all clocks provided by this provider */
|
||||
|
||||
static struct clk_hw_onecell_data axg_hw_onecell_data = {
|
||||
.hws = {
|
||||
[CLKID_SYS_PLL] = &axg_sys_pll.hw,
|
||||
[CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
|
||||
[CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
|
||||
[CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
|
||||
[CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
|
||||
[CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
|
||||
[CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
|
||||
[CLKID_GP0_PLL] = &axg_gp0_pll.hw,
|
||||
[CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
|
||||
[CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
|
||||
[CLKID_CLK81] = &axg_clk81.hw,
|
||||
[CLKID_MPLL0] = &axg_mpll0.hw,
|
||||
[CLKID_MPLL1] = &axg_mpll1.hw,
|
||||
[CLKID_MPLL2] = &axg_mpll2.hw,
|
||||
[CLKID_MPLL3] = &axg_mpll3.hw,
|
||||
[CLKID_DDR] = &axg_ddr.hw,
|
||||
[CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
|
||||
[CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
|
||||
[CLKID_ISA] = &axg_isa.hw,
|
||||
[CLKID_PL301] = &axg_pl301.hw,
|
||||
[CLKID_PERIPHS] = &axg_periphs.hw,
|
||||
[CLKID_SPICC0] = &axg_spicc_0.hw,
|
||||
[CLKID_I2C] = &axg_i2c.hw,
|
||||
[CLKID_RNG0] = &axg_rng0.hw,
|
||||
[CLKID_UART0] = &axg_uart0.hw,
|
||||
[CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
|
||||
[CLKID_SPICC1] = &axg_spicc_1.hw,
|
||||
[CLKID_PCIE_A] = &axg_pcie_a.hw,
|
||||
[CLKID_PCIE_B] = &axg_pcie_b.hw,
|
||||
[CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
|
||||
[CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
|
||||
[CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
|
||||
[CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
|
||||
[CLKID_DMA] = &axg_dma.hw,
|
||||
[CLKID_SPI] = &axg_spi.hw,
|
||||
[CLKID_AUDIO] = &axg_audio.hw,
|
||||
[CLKID_ETH] = &axg_eth_core.hw,
|
||||
[CLKID_UART1] = &axg_uart1.hw,
|
||||
[CLKID_G2D] = &axg_g2d.hw,
|
||||
[CLKID_USB0] = &axg_usb0.hw,
|
||||
[CLKID_USB1] = &axg_usb1.hw,
|
||||
[CLKID_RESET] = &axg_reset.hw,
|
||||
[CLKID_USB] = &axg_usb_general.hw,
|
||||
[CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
|
||||
[CLKID_EFUSE] = &axg_efuse.hw,
|
||||
[CLKID_BOOT_ROM] = &axg_boot_rom.hw,
|
||||
[CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
|
||||
[CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
|
||||
[CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
|
||||
[CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
|
||||
[CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
|
||||
[CLKID_VPU_INTR] = &axg_vpu_intr.hw,
|
||||
[CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
|
||||
[CLKID_GIC] = &axg_gic.hw,
|
||||
[CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
|
||||
[CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
|
||||
[CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
|
||||
[CLKID_AO_IFACE] = &axg_ao_iface.hw,
|
||||
[CLKID_AO_I2C] = &axg_ao_i2c.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
|
||||
[NR_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
};
|
||||
|
||||
/* Convenience tables to populate base addresses in .probe */
|
||||
|
||||
static struct meson_clk_pll *const axg_clk_plls[] = {
|
||||
&axg_fixed_pll,
|
||||
&axg_sys_pll,
|
||||
&axg_gp0_pll,
|
||||
};
|
||||
|
||||
static struct meson_clk_mpll *const axg_clk_mplls[] = {
|
||||
&axg_mpll0,
|
||||
&axg_mpll1,
|
||||
&axg_mpll2,
|
||||
&axg_mpll3,
|
||||
};
|
||||
|
||||
static struct clk_gate *const axg_clk_gates[] = {
|
||||
&axg_clk81,
|
||||
&axg_ddr,
|
||||
&axg_audio_locker,
|
||||
&axg_mipi_dsi_host,
|
||||
&axg_isa,
|
||||
&axg_pl301,
|
||||
&axg_periphs,
|
||||
&axg_spicc_0,
|
||||
&axg_i2c,
|
||||
&axg_rng0,
|
||||
&axg_uart0,
|
||||
&axg_mipi_dsi_phy,
|
||||
&axg_spicc_1,
|
||||
&axg_pcie_a,
|
||||
&axg_pcie_b,
|
||||
&axg_hiu_reg,
|
||||
&axg_assist_misc,
|
||||
&axg_emmc_b,
|
||||
&axg_emmc_c,
|
||||
&axg_dma,
|
||||
&axg_spi,
|
||||
&axg_audio,
|
||||
&axg_eth_core,
|
||||
&axg_uart1,
|
||||
&axg_g2d,
|
||||
&axg_usb0,
|
||||
&axg_usb1,
|
||||
&axg_reset,
|
||||
&axg_usb_general,
|
||||
&axg_ahb_arb0,
|
||||
&axg_efuse,
|
||||
&axg_boot_rom,
|
||||
&axg_ahb_data_bus,
|
||||
&axg_ahb_ctrl_bus,
|
||||
&axg_usb1_to_ddr,
|
||||
&axg_usb0_to_ddr,
|
||||
&axg_mmc_pclk,
|
||||
&axg_vpu_intr,
|
||||
&axg_sec_ahb_ahb3_bridge,
|
||||
&axg_gic,
|
||||
&axg_ao_media_cpu,
|
||||
&axg_ao_ahb_sram,
|
||||
&axg_ao_ahb_bus,
|
||||
&axg_ao_iface,
|
||||
&axg_ao_i2c,
|
||||
&axg_sd_emmc_b_clk0,
|
||||
&axg_sd_emmc_c_clk0,
|
||||
};
|
||||
|
||||
static struct clk_mux *const axg_clk_muxes[] = {
|
||||
&axg_mpeg_clk_sel,
|
||||
&axg_sd_emmc_b_clk0_sel,
|
||||
&axg_sd_emmc_c_clk0_sel,
|
||||
};
|
||||
|
||||
static struct clk_divider *const axg_clk_dividers[] = {
|
||||
&axg_mpeg_clk_div,
|
||||
&axg_sd_emmc_b_clk0_div,
|
||||
&axg_sd_emmc_c_clk0_div,
|
||||
};
|
||||
|
||||
struct clkc_data {
|
||||
struct clk_gate *const *clk_gates;
|
||||
unsigned int clk_gates_count;
|
||||
struct meson_clk_mpll *const *clk_mplls;
|
||||
unsigned int clk_mplls_count;
|
||||
struct meson_clk_pll *const *clk_plls;
|
||||
unsigned int clk_plls_count;
|
||||
struct clk_mux *const *clk_muxes;
|
||||
unsigned int clk_muxes_count;
|
||||
struct clk_divider *const *clk_dividers;
|
||||
unsigned int clk_dividers_count;
|
||||
struct clk_hw_onecell_data *hw_onecell_data;
|
||||
};
|
||||
|
||||
static const struct clkc_data axg_clkc_data = {
|
||||
.clk_gates = axg_clk_gates,
|
||||
.clk_gates_count = ARRAY_SIZE(axg_clk_gates),
|
||||
.clk_mplls = axg_clk_mplls,
|
||||
.clk_mplls_count = ARRAY_SIZE(axg_clk_mplls),
|
||||
.clk_plls = axg_clk_plls,
|
||||
.clk_plls_count = ARRAY_SIZE(axg_clk_plls),
|
||||
.clk_muxes = axg_clk_muxes,
|
||||
.clk_muxes_count = ARRAY_SIZE(axg_clk_muxes),
|
||||
.clk_dividers = axg_clk_dividers,
|
||||
.clk_dividers_count = ARRAY_SIZE(axg_clk_dividers),
|
||||
.hw_onecell_data = &axg_hw_onecell_data,
|
||||
};
|
||||
|
||||
static const struct of_device_id clkc_match_table[] = {
|
||||
{ .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
|
||||
{}
|
||||
};
|
||||
|
||||
static int axg_clkc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
const struct clkc_data *clkc_data;
|
||||
struct resource *res;
|
||||
void __iomem *clk_base;
|
||||
int ret, clkid, i;
|
||||
|
||||
clkc_data = of_device_get_match_data(&pdev->dev);
|
||||
if (!clkc_data)
|
||||
return -EINVAL;
|
||||
|
||||
/* Generic clocks and PLLs */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res)
|
||||
return -EINVAL;
|
||||
clk_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
|
||||
if (!clk_base) {
|
||||
dev_err(&pdev->dev, "Unable to map clk base\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
/* Populate base address for PLLs */
|
||||
for (i = 0; i < clkc_data->clk_plls_count; i++)
|
||||
clkc_data->clk_plls[i]->base = clk_base;
|
||||
|
||||
/* Populate base address for MPLLs */
|
||||
for (i = 0; i < clkc_data->clk_mplls_count; i++)
|
||||
clkc_data->clk_mplls[i]->base = clk_base;
|
||||
|
||||
/* Populate base address for gates */
|
||||
for (i = 0; i < clkc_data->clk_gates_count; i++)
|
||||
clkc_data->clk_gates[i]->reg = clk_base +
|
||||
(u64)clkc_data->clk_gates[i]->reg;
|
||||
|
||||
/* Populate base address for muxes */
|
||||
for (i = 0; i < clkc_data->clk_muxes_count; i++)
|
||||
clkc_data->clk_muxes[i]->reg = clk_base +
|
||||
(u64)clkc_data->clk_muxes[i]->reg;
|
||||
|
||||
/* Populate base address for dividers */
|
||||
for (i = 0; i < clkc_data->clk_dividers_count; i++)
|
||||
clkc_data->clk_dividers[i]->reg = clk_base +
|
||||
(u64)clkc_data->clk_dividers[i]->reg;
|
||||
|
||||
for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) {
|
||||
/* array might be sparse */
|
||||
if (!clkc_data->hw_onecell_data->hws[clkid])
|
||||
continue;
|
||||
|
||||
ret = devm_clk_hw_register(dev,
|
||||
clkc_data->hw_onecell_data->hws[clkid]);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Clock registration failed\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
|
||||
clkc_data->hw_onecell_data);
|
||||
}
|
||||
|
||||
static struct platform_driver axg_driver = {
|
||||
.probe = axg_clkc_probe,
|
||||
.driver = {
|
||||
.name = "axg-clkc",
|
||||
.of_match_table = clkc_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(axg_driver);
|
126
drivers/clk/meson/axg.h
Normal file
126
drivers/clk/meson/axg.h
Normal file
|
@ -0,0 +1,126 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2016 AmLogic, Inc.
|
||||
* Author: Michael Turquette <mturquette@baylibre.com>
|
||||
*
|
||||
* Copyright (c) 2017 Amlogic, inc.
|
||||
* Author: Qiufang Dai <qiufang.dai@amlogic.com>
|
||||
*
|
||||
*/
|
||||
#ifndef __AXG_H
|
||||
#define __AXG_H
|
||||
|
||||
/*
|
||||
* Clock controller register offsets
|
||||
*
|
||||
* Register offsets from the data sheet must be multiplied by 4 before
|
||||
* adding them to the base address to get the right value.
|
||||
*/
|
||||
#define HHI_GP0_PLL_CNTL 0x40
|
||||
#define HHI_GP0_PLL_CNTL2 0x44
|
||||
#define HHI_GP0_PLL_CNTL3 0x48
|
||||
#define HHI_GP0_PLL_CNTL4 0x4c
|
||||
#define HHI_GP0_PLL_CNTL5 0x50
|
||||
#define HHI_GP0_PLL_STS 0x54
|
||||
#define HHI_GP0_PLL_CNTL1 0x58
|
||||
#define HHI_HIFI_PLL_CNTL 0x80
|
||||
#define HHI_HIFI_PLL_CNTL2 0x84
|
||||
#define HHI_HIFI_PLL_CNTL3 0x88
|
||||
#define HHI_HIFI_PLL_CNTL4 0x8C
|
||||
#define HHI_HIFI_PLL_CNTL5 0x90
|
||||
#define HHI_HIFI_PLL_STS 0x94
|
||||
#define HHI_HIFI_PLL_CNTL1 0x98
|
||||
|
||||
#define HHI_XTAL_DIVN_CNTL 0xbc
|
||||
#define HHI_GCLK2_MPEG0 0xc0
|
||||
#define HHI_GCLK2_MPEG1 0xc4
|
||||
#define HHI_GCLK2_MPEG2 0xc8
|
||||
#define HHI_GCLK2_OTHER 0xd0
|
||||
#define HHI_GCLK2_AO 0xd4
|
||||
#define HHI_PCIE_PLL_CNTL 0xd8
|
||||
#define HHI_PCIE_PLL_CNTL1 0xdC
|
||||
#define HHI_PCIE_PLL_CNTL2 0xe0
|
||||
#define HHI_PCIE_PLL_CNTL3 0xe4
|
||||
#define HHI_PCIE_PLL_CNTL4 0xe8
|
||||
#define HHI_PCIE_PLL_CNTL5 0xec
|
||||
#define HHI_PCIE_PLL_CNTL6 0xf0
|
||||
#define HHI_PCIE_PLL_STS 0xf4
|
||||
|
||||
#define HHI_MEM_PD_REG0 0x100
|
||||
#define HHI_VPU_MEM_PD_REG0 0x104
|
||||
#define HHI_VIID_CLK_DIV 0x128
|
||||
#define HHI_VIID_CLK_CNTL 0x12c
|
||||
|
||||
#define HHI_GCLK_MPEG0 0x140
|
||||
#define HHI_GCLK_MPEG1 0x144
|
||||
#define HHI_GCLK_MPEG2 0x148
|
||||
#define HHI_GCLK_OTHER 0x150
|
||||
#define HHI_GCLK_AO 0x154
|
||||
#define HHI_SYS_CPU_CLK_CNTL1 0x15c
|
||||
#define HHI_SYS_CPU_RESET_CNTL 0x160
|
||||
#define HHI_VID_CLK_DIV 0x164
|
||||
#define HHI_SPICC_HCLK_CNTL 0x168
|
||||
|
||||
#define HHI_MPEG_CLK_CNTL 0x174
|
||||
#define HHI_VID_CLK_CNTL 0x17c
|
||||
#define HHI_TS_CLK_CNTL 0x190
|
||||
#define HHI_VID_CLK_CNTL2 0x194
|
||||
#define HHI_SYS_CPU_CLK_CNTL0 0x19c
|
||||
#define HHI_VID_PLL_CLK_DIV 0x1a0
|
||||
#define HHI_VPU_CLK_CNTL 0x1bC
|
||||
|
||||
#define HHI_VAPBCLK_CNTL 0x1F4
|
||||
|
||||
#define HHI_GEN_CLK_CNTL 0x228
|
||||
|
||||
#define HHI_VDIN_MEAS_CLK_CNTL 0x250
|
||||
#define HHI_NAND_CLK_CNTL 0x25C
|
||||
#define HHI_SD_EMMC_CLK_CNTL 0x264
|
||||
|
||||
#define HHI_MPLL_CNTL 0x280
|
||||
#define HHI_MPLL_CNTL2 0x284
|
||||
#define HHI_MPLL_CNTL3 0x288
|
||||
#define HHI_MPLL_CNTL4 0x28C
|
||||
#define HHI_MPLL_CNTL5 0x290
|
||||
#define HHI_MPLL_CNTL6 0x294
|
||||
#define HHI_MPLL_CNTL7 0x298
|
||||
#define HHI_MPLL_CNTL8 0x29C
|
||||
#define HHI_MPLL_CNTL9 0x2A0
|
||||
#define HHI_MPLL_CNTL10 0x2A4
|
||||
|
||||
#define HHI_MPLL3_CNTL0 0x2E0
|
||||
#define HHI_MPLL3_CNTL1 0x2E4
|
||||
#define HHI_PLL_TOP_MISC 0x2E8
|
||||
|
||||
#define HHI_SYS_PLL_CNTL1 0x2FC
|
||||
#define HHI_SYS_PLL_CNTL 0x300
|
||||
#define HHI_SYS_PLL_CNTL2 0x304
|
||||
#define HHI_SYS_PLL_CNTL3 0x308
|
||||
#define HHI_SYS_PLL_CNTL4 0x30c
|
||||
#define HHI_SYS_PLL_CNTL5 0x310
|
||||
#define HHI_SYS_PLL_STS 0x314
|
||||
#define HHI_DPLL_TOP_I 0x318
|
||||
#define HHI_DPLL_TOP2_I 0x31C
|
||||
|
||||
/*
|
||||
* CLKID index values
|
||||
*
|
||||
* These indices are entirely contrived and do not map onto the hardware.
|
||||
* It has now been decided to expose everything by default in the DT header:
|
||||
* include/dt-bindings/clock/axg-clkc.h. Only the clocks ids we don't want
|
||||
* to expose, such as the internal muxes and dividers of composite clocks,
|
||||
* will remain defined here.
|
||||
*/
|
||||
#define CLKID_MPEG_SEL 8
|
||||
#define CLKID_MPEG_DIV 9
|
||||
#define CLKID_SD_EMMC_B_CLK0_SEL 61
|
||||
#define CLKID_SD_EMMC_B_CLK0_DIV 62
|
||||
#define CLKID_SD_EMMC_C_CLK0_SEL 63
|
||||
#define CLKID_SD_EMMC_C_CLK0_DIV 64
|
||||
|
||||
#define NR_CLKS 65
|
||||
|
||||
/* include the CLKIDs that have been made part of the DT binding */
|
||||
#include <dt-bindings/clock/axg-clkc.h>
|
||||
|
||||
#endif /* __AXG_H */
|
|
@ -98,7 +98,7 @@ static void params_from_rate(unsigned long requested_rate,
|
|||
*sdm = SDM_DEN - 1;
|
||||
} else {
|
||||
*n2 = div;
|
||||
*sdm = DIV_ROUND_UP(rem * SDM_DEN, requested_rate);
|
||||
*sdm = DIV_ROUND_UP_ULL((u64)rem * SDM_DEN, requested_rate);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -134,7 +134,7 @@ struct meson_clk_audio_divider {
|
|||
struct clk_gate _name = { \
|
||||
.reg = (void __iomem *) _reg, \
|
||||
.bit_idx = (_bit), \
|
||||
.lock = &clk_lock, \
|
||||
.lock = &meson_clk_lock, \
|
||||
.hw.init = &(struct clk_init_data) { \
|
||||
.name = #_name, \
|
||||
.ops = &clk_gate_ops, \
|
||||
|
|
|
@ -27,7 +27,7 @@
|
|||
#include "clkc.h"
|
||||
#include "gxbb.h"
|
||||
|
||||
static DEFINE_SPINLOCK(clk_lock);
|
||||
static DEFINE_SPINLOCK(meson_clk_lock);
|
||||
|
||||
static const struct pll_rate_table sys_pll_rate_table[] = {
|
||||
PLL_RATE(24000000, 56, 1, 2),
|
||||
|
@ -294,7 +294,7 @@ static struct meson_clk_pll gxbb_fixed_pll = {
|
|||
.shift = 16,
|
||||
.width = 2,
|
||||
},
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "fixed_pll",
|
||||
.ops = &meson_clk_pll_ro_ops,
|
||||
|
@ -330,7 +330,7 @@ static struct meson_clk_pll gxbb_hdmi_pll = {
|
|||
.shift = 22,
|
||||
.width = 2,
|
||||
},
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "hdmi_pll",
|
||||
.ops = &meson_clk_pll_ro_ops,
|
||||
|
@ -358,7 +358,7 @@ static struct meson_clk_pll gxbb_sys_pll = {
|
|||
},
|
||||
.rate_table = sys_pll_rate_table,
|
||||
.rate_count = ARRAY_SIZE(sys_pll_rate_table),
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sys_pll",
|
||||
.ops = &meson_clk_pll_ro_ops,
|
||||
|
@ -399,7 +399,7 @@ static struct meson_clk_pll gxbb_gp0_pll = {
|
|||
},
|
||||
.rate_table = gxbb_gp0_pll_rate_table,
|
||||
.rate_count = ARRAY_SIZE(gxbb_gp0_pll_rate_table),
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gp0_pll",
|
||||
.ops = &meson_clk_pll_ops,
|
||||
|
@ -442,7 +442,7 @@ static struct meson_clk_pll gxl_gp0_pll = {
|
|||
},
|
||||
.rate_table = gxl_gp0_pll_rate_table,
|
||||
.rate_count = ARRAY_SIZE(gxl_gp0_pll_rate_table),
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gp0_pll",
|
||||
.ops = &meson_clk_pll_ops,
|
||||
|
@ -533,7 +533,7 @@ static struct meson_clk_mpll gxbb_mpll0 = {
|
|||
.shift = 25,
|
||||
.width = 1,
|
||||
},
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpll0",
|
||||
.ops = &meson_clk_mpll_ops,
|
||||
|
@ -563,7 +563,7 @@ static struct meson_clk_mpll gxbb_mpll1 = {
|
|||
.shift = 14,
|
||||
.width = 1,
|
||||
},
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpll1",
|
||||
.ops = &meson_clk_mpll_ops,
|
||||
|
@ -593,7 +593,7 @@ static struct meson_clk_mpll gxbb_mpll2 = {
|
|||
.shift = 14,
|
||||
.width = 1,
|
||||
},
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpll2",
|
||||
.ops = &meson_clk_mpll_ops,
|
||||
|
@ -620,7 +620,7 @@ static struct clk_mux gxbb_mpeg_clk_sel = {
|
|||
.shift = 12,
|
||||
.flags = CLK_MUX_READ_ONLY,
|
||||
.table = mux_table_clk81,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpeg_clk_sel",
|
||||
.ops = &clk_mux_ro_ops,
|
||||
|
@ -639,7 +639,7 @@ static struct clk_divider gxbb_mpeg_clk_div = {
|
|||
.reg = (void *)HHI_MPEG_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpeg_clk_div",
|
||||
.ops = &clk_divider_ops,
|
||||
|
@ -653,7 +653,7 @@ static struct clk_divider gxbb_mpeg_clk_div = {
|
|||
static struct clk_gate gxbb_clk81 = {
|
||||
.reg = (void *)HHI_MPEG_CLK_CNTL,
|
||||
.bit_idx = 7,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "clk81",
|
||||
.ops = &clk_gate_ops,
|
||||
|
@ -667,7 +667,7 @@ static struct clk_mux gxbb_sar_adc_clk_sel = {
|
|||
.reg = (void *)HHI_SAR_CLK_CNTL,
|
||||
.mask = 0x3,
|
||||
.shift = 9,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sar_adc_clk_sel",
|
||||
.ops = &clk_mux_ops,
|
||||
|
@ -681,7 +681,7 @@ static struct clk_divider gxbb_sar_adc_clk_div = {
|
|||
.reg = (void *)HHI_SAR_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 8,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sar_adc_clk_div",
|
||||
.ops = &clk_divider_ops,
|
||||
|
@ -693,7 +693,7 @@ static struct clk_divider gxbb_sar_adc_clk_div = {
|
|||
static struct clk_gate gxbb_sar_adc_clk = {
|
||||
.reg = (void *)HHI_SAR_CLK_CNTL,
|
||||
.bit_idx = 8,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sar_adc_clk",
|
||||
.ops = &clk_gate_ops,
|
||||
|
@ -719,7 +719,7 @@ static struct clk_mux gxbb_mali_0_sel = {
|
|||
.mask = 0x7,
|
||||
.shift = 9,
|
||||
.table = mux_table_mali_0_1,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mali_0_sel",
|
||||
.ops = &clk_mux_ops,
|
||||
|
@ -738,7 +738,7 @@ static struct clk_divider gxbb_mali_0_div = {
|
|||
.reg = (void *)HHI_MALI_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mali_0_div",
|
||||
.ops = &clk_divider_ops,
|
||||
|
@ -751,7 +751,7 @@ static struct clk_divider gxbb_mali_0_div = {
|
|||
static struct clk_gate gxbb_mali_0 = {
|
||||
.reg = (void *)HHI_MALI_CLK_CNTL,
|
||||
.bit_idx = 8,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mali_0",
|
||||
.ops = &clk_gate_ops,
|
||||
|
@ -766,7 +766,7 @@ static struct clk_mux gxbb_mali_1_sel = {
|
|||
.mask = 0x7,
|
||||
.shift = 25,
|
||||
.table = mux_table_mali_0_1,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mali_1_sel",
|
||||
.ops = &clk_mux_ops,
|
||||
|
@ -785,7 +785,7 @@ static struct clk_divider gxbb_mali_1_div = {
|
|||
.reg = (void *)HHI_MALI_CLK_CNTL,
|
||||
.shift = 16,
|
||||
.width = 7,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mali_1_div",
|
||||
.ops = &clk_divider_ops,
|
||||
|
@ -798,7 +798,7 @@ static struct clk_divider gxbb_mali_1_div = {
|
|||
static struct clk_gate gxbb_mali_1 = {
|
||||
.reg = (void *)HHI_MALI_CLK_CNTL,
|
||||
.bit_idx = 24,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mali_1",
|
||||
.ops = &clk_gate_ops,
|
||||
|
@ -818,7 +818,7 @@ static struct clk_mux gxbb_mali = {
|
|||
.mask = 1,
|
||||
.shift = 31,
|
||||
.table = mux_table_mali,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mali",
|
||||
.ops = &clk_mux_ops,
|
||||
|
@ -834,7 +834,7 @@ static struct clk_mux gxbb_cts_amclk_sel = {
|
|||
.shift = 9,
|
||||
/* Default parent unknown (register reset value: 0) */
|
||||
.table = (u32[]){ 1, 2, 3 },
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_amclk_sel",
|
||||
.ops = &clk_mux_ops,
|
||||
|
@ -851,7 +851,7 @@ static struct meson_clk_audio_divider gxbb_cts_amclk_div = {
|
|||
.width = 8,
|
||||
},
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_amclk_div",
|
||||
.ops = &meson_clk_audio_divider_ops,
|
||||
|
@ -864,7 +864,7 @@ static struct meson_clk_audio_divider gxbb_cts_amclk_div = {
|
|||
static struct clk_gate gxbb_cts_amclk = {
|
||||
.reg = (void *) HHI_AUD_CLK_CNTL,
|
||||
.bit_idx = 8,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_amclk",
|
||||
.ops = &clk_gate_ops,
|
||||
|
@ -880,7 +880,7 @@ static struct clk_mux gxbb_cts_mclk_i958_sel = {
|
|||
.shift = 25,
|
||||
/* Default parent unknown (register reset value: 0) */
|
||||
.table = (u32[]){ 1, 2, 3 },
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cts_mclk_i958_sel",
|
||||
.ops = &clk_mux_ops,
|
||||
|
@ -894,7 +894,7 @@ static struct clk_divider gxbb_cts_mclk_i958_div = {
|
|||
.reg = (void *)HHI_AUD_CLK_CNTL2,
|
||||
.shift = 16,
|
||||
.width = 8,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cts_mclk_i958_div",
|
||||
|
@ -908,7 +908,7 @@ static struct clk_divider gxbb_cts_mclk_i958_div = {
|
|||
static struct clk_gate gxbb_cts_mclk_i958 = {
|
||||
.reg = (void *)HHI_AUD_CLK_CNTL2,
|
||||
.bit_idx = 24,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_mclk_i958",
|
||||
.ops = &clk_gate_ops,
|
||||
|
@ -922,7 +922,7 @@ static struct clk_mux gxbb_cts_i958 = {
|
|||
.reg = (void *)HHI_AUD_CLK_CNTL2,
|
||||
.mask = 0x1,
|
||||
.shift = 27,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_i958",
|
||||
.ops = &clk_mux_ops,
|
||||
|
@ -940,7 +940,7 @@ static struct clk_divider gxbb_32k_clk_div = {
|
|||
.reg = (void *)HHI_32K_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 14,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "32k_clk_div",
|
||||
.ops = &clk_divider_ops,
|
||||
|
@ -953,7 +953,7 @@ static struct clk_divider gxbb_32k_clk_div = {
|
|||
static struct clk_gate gxbb_32k_clk = {
|
||||
.reg = (void *)HHI_32K_CLK_CNTL,
|
||||
.bit_idx = 15,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "32k_clk",
|
||||
.ops = &clk_gate_ops,
|
||||
|
@ -971,7 +971,7 @@ static struct clk_mux gxbb_32k_clk_sel = {
|
|||
.reg = (void *)HHI_32K_CLK_CNTL,
|
||||
.mask = 0x3,
|
||||
.shift = 16,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "32k_clk_sel",
|
||||
.ops = &clk_mux_ops,
|
||||
|
@ -997,7 +997,7 @@ static struct clk_mux gxbb_sd_emmc_a_clk0_sel = {
|
|||
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
|
||||
.mask = 0x7,
|
||||
.shift = 9,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sd_emmc_a_clk0_sel",
|
||||
.ops = &clk_mux_ops,
|
||||
|
@ -1011,7 +1011,7 @@ static struct clk_divider gxbb_sd_emmc_a_clk0_div = {
|
|||
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sd_emmc_a_clk0_div",
|
||||
|
@ -1025,23 +1025,13 @@ static struct clk_divider gxbb_sd_emmc_a_clk0_div = {
|
|||
static struct clk_gate gxbb_sd_emmc_a_clk0 = {
|
||||
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
|
||||
.bit_idx = 7,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sd_emmc_a_clk0",
|
||||
.ops = &clk_gate_ops,
|
||||
.parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
|
||||
.num_parents = 1,
|
||||
|
||||
/*
|
||||
* FIXME:
|
||||
* We need CLK_IGNORE_UNUSED because mmc DT node point to xtal
|
||||
* instead of this clock. CCF would gate this on boot, killing
|
||||
* the mmc controller. Please remove this flag once DT properly
|
||||
* point to this clock instead of xtal
|
||||
*
|
||||
* Same goes for emmc B and C clocks
|
||||
*/
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -1050,7 +1040,7 @@ static struct clk_mux gxbb_sd_emmc_b_clk0_sel = {
|
|||
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
|
||||
.mask = 0x7,
|
||||
.shift = 25,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sd_emmc_b_clk0_sel",
|
||||
.ops = &clk_mux_ops,
|
||||
|
@ -1064,7 +1054,7 @@ static struct clk_divider gxbb_sd_emmc_b_clk0_div = {
|
|||
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
|
||||
.shift = 16,
|
||||
.width = 7,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sd_emmc_b_clk0_div",
|
||||
|
@ -1078,13 +1068,13 @@ static struct clk_divider gxbb_sd_emmc_b_clk0_div = {
|
|||
static struct clk_gate gxbb_sd_emmc_b_clk0 = {
|
||||
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
|
||||
.bit_idx = 23,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sd_emmc_b_clk0",
|
||||
.ops = &clk_gate_ops,
|
||||
.parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -1093,7 +1083,7 @@ static struct clk_mux gxbb_sd_emmc_c_clk0_sel = {
|
|||
.reg = (void *)HHI_NAND_CLK_CNTL,
|
||||
.mask = 0x7,
|
||||
.shift = 9,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sd_emmc_c_clk0_sel",
|
||||
.ops = &clk_mux_ops,
|
||||
|
@ -1107,7 +1097,7 @@ static struct clk_divider gxbb_sd_emmc_c_clk0_div = {
|
|||
.reg = (void *)HHI_NAND_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sd_emmc_c_clk0_div",
|
||||
|
@ -1121,13 +1111,13 @@ static struct clk_divider gxbb_sd_emmc_c_clk0_div = {
|
|||
static struct clk_gate gxbb_sd_emmc_c_clk0 = {
|
||||
.reg = (void *)HHI_NAND_CLK_CNTL,
|
||||
.bit_idx = 7,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sd_emmc_c_clk0",
|
||||
.ops = &clk_gate_ops,
|
||||
.parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -1142,7 +1132,7 @@ static struct clk_mux gxbb_vpu_0_sel = {
|
|||
.reg = (void *)HHI_VPU_CLK_CNTL,
|
||||
.mask = 0x3,
|
||||
.shift = 9,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.table = mux_table_vpu,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vpu_0_sel",
|
||||
|
@ -1161,7 +1151,7 @@ static struct clk_divider gxbb_vpu_0_div = {
|
|||
.reg = (void *)HHI_VPU_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vpu_0_div",
|
||||
.ops = &clk_divider_ops,
|
||||
|
@ -1174,7 +1164,7 @@ static struct clk_divider gxbb_vpu_0_div = {
|
|||
static struct clk_gate gxbb_vpu_0 = {
|
||||
.reg = (void *)HHI_VPU_CLK_CNTL,
|
||||
.bit_idx = 8,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vpu_0",
|
||||
.ops = &clk_gate_ops,
|
||||
|
@ -1188,7 +1178,7 @@ static struct clk_mux gxbb_vpu_1_sel = {
|
|||
.reg = (void *)HHI_VPU_CLK_CNTL,
|
||||
.mask = 0x3,
|
||||
.shift = 25,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.table = mux_table_vpu,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vpu_1_sel",
|
||||
|
@ -1207,7 +1197,7 @@ static struct clk_divider gxbb_vpu_1_div = {
|
|||
.reg = (void *)HHI_VPU_CLK_CNTL,
|
||||
.shift = 16,
|
||||
.width = 7,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vpu_1_div",
|
||||
.ops = &clk_divider_ops,
|
||||
|
@ -1220,7 +1210,7 @@ static struct clk_divider gxbb_vpu_1_div = {
|
|||
static struct clk_gate gxbb_vpu_1 = {
|
||||
.reg = (void *)HHI_VPU_CLK_CNTL,
|
||||
.bit_idx = 24,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vpu_1",
|
||||
.ops = &clk_gate_ops,
|
||||
|
@ -1234,7 +1224,7 @@ static struct clk_mux gxbb_vpu = {
|
|||
.reg = (void *)HHI_VPU_CLK_CNTL,
|
||||
.mask = 1,
|
||||
.shift = 31,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vpu",
|
||||
.ops = &clk_mux_ops,
|
||||
|
@ -1259,7 +1249,7 @@ static struct clk_mux gxbb_vapb_0_sel = {
|
|||
.reg = (void *)HHI_VAPBCLK_CNTL,
|
||||
.mask = 0x3,
|
||||
.shift = 9,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.table = mux_table_vapb,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vapb_0_sel",
|
||||
|
@ -1278,7 +1268,7 @@ static struct clk_divider gxbb_vapb_0_div = {
|
|||
.reg = (void *)HHI_VAPBCLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vapb_0_div",
|
||||
.ops = &clk_divider_ops,
|
||||
|
@ -1291,7 +1281,7 @@ static struct clk_divider gxbb_vapb_0_div = {
|
|||
static struct clk_gate gxbb_vapb_0 = {
|
||||
.reg = (void *)HHI_VAPBCLK_CNTL,
|
||||
.bit_idx = 8,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vapb_0",
|
||||
.ops = &clk_gate_ops,
|
||||
|
@ -1305,7 +1295,7 @@ static struct clk_mux gxbb_vapb_1_sel = {
|
|||
.reg = (void *)HHI_VAPBCLK_CNTL,
|
||||
.mask = 0x3,
|
||||
.shift = 25,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.table = mux_table_vapb,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vapb_1_sel",
|
||||
|
@ -1324,7 +1314,7 @@ static struct clk_divider gxbb_vapb_1_div = {
|
|||
.reg = (void *)HHI_VAPBCLK_CNTL,
|
||||
.shift = 16,
|
||||
.width = 7,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vapb_1_div",
|
||||
.ops = &clk_divider_ops,
|
||||
|
@ -1337,7 +1327,7 @@ static struct clk_divider gxbb_vapb_1_div = {
|
|||
static struct clk_gate gxbb_vapb_1 = {
|
||||
.reg = (void *)HHI_VAPBCLK_CNTL,
|
||||
.bit_idx = 24,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vapb_1",
|
||||
.ops = &clk_gate_ops,
|
||||
|
@ -1351,7 +1341,7 @@ static struct clk_mux gxbb_vapb_sel = {
|
|||
.reg = (void *)HHI_VAPBCLK_CNTL,
|
||||
.mask = 1,
|
||||
.shift = 31,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vapb_sel",
|
||||
.ops = &clk_mux_ops,
|
||||
|
@ -1368,7 +1358,7 @@ static struct clk_mux gxbb_vapb_sel = {
|
|||
static struct clk_gate gxbb_vapb = {
|
||||
.reg = (void *)HHI_VAPBCLK_CNTL,
|
||||
.bit_idx = 30,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vapb",
|
||||
.ops = &clk_gate_ops,
|
||||
|
@ -1386,7 +1376,7 @@ static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
|
|||
static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
|
||||
static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
|
||||
static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
|
||||
static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 10);
|
||||
static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
|
||||
static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
|
||||
static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
|
||||
static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
|
||||
|
@ -1437,7 +1427,7 @@ static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
|
|||
static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
|
||||
static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
|
||||
static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
|
||||
static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG2, 22);
|
||||
static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
|
||||
static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
|
||||
static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
|
||||
static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
|
||||
|
|
|
@ -32,7 +32,7 @@
|
|||
#include "clkc.h"
|
||||
#include "meson8b.h"
|
||||
|
||||
static DEFINE_SPINLOCK(clk_lock);
|
||||
static DEFINE_SPINLOCK(meson_clk_lock);
|
||||
|
||||
static void __iomem *clk_base;
|
||||
|
||||
|
@ -136,7 +136,7 @@ static struct meson_clk_pll meson8b_fixed_pll = {
|
|||
.shift = 16,
|
||||
.width = 2,
|
||||
},
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "fixed_pll",
|
||||
.ops = &meson_clk_pll_ro_ops,
|
||||
|
@ -162,7 +162,7 @@ static struct meson_clk_pll meson8b_vid_pll = {
|
|||
.shift = 16,
|
||||
.width = 2,
|
||||
},
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vid_pll",
|
||||
.ops = &meson_clk_pll_ro_ops,
|
||||
|
@ -190,7 +190,7 @@ static struct meson_clk_pll meson8b_sys_pll = {
|
|||
},
|
||||
.rate_table = sys_pll_rate_table,
|
||||
.rate_count = ARRAY_SIZE(sys_pll_rate_table),
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sys_pll",
|
||||
.ops = &meson_clk_pll_ops,
|
||||
|
@ -281,7 +281,7 @@ static struct meson_clk_mpll meson8b_mpll0 = {
|
|||
.shift = 25,
|
||||
.width = 1,
|
||||
},
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpll0",
|
||||
.ops = &meson_clk_mpll_ops,
|
||||
|
@ -311,7 +311,7 @@ static struct meson_clk_mpll meson8b_mpll1 = {
|
|||
.shift = 14,
|
||||
.width = 1,
|
||||
},
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpll1",
|
||||
.ops = &meson_clk_mpll_ops,
|
||||
|
@ -341,7 +341,7 @@ static struct meson_clk_mpll meson8b_mpll2 = {
|
|||
.shift = 14,
|
||||
.width = 1,
|
||||
},
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpll2",
|
||||
.ops = &meson_clk_mpll_ops,
|
||||
|
@ -375,7 +375,7 @@ struct clk_mux meson8b_mpeg_clk_sel = {
|
|||
.shift = 12,
|
||||
.flags = CLK_MUX_READ_ONLY,
|
||||
.table = mux_table_clk81,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpeg_clk_sel",
|
||||
.ops = &clk_mux_ro_ops,
|
||||
|
@ -395,7 +395,7 @@ struct clk_divider meson8b_mpeg_clk_div = {
|
|||
.reg = (void *)HHI_MPEG_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpeg_clk_div",
|
||||
.ops = &clk_divider_ops,
|
||||
|
@ -408,7 +408,7 @@ struct clk_divider meson8b_mpeg_clk_div = {
|
|||
struct clk_gate meson8b_clk81 = {
|
||||
.reg = (void *)HHI_MPEG_CLK_CNTL,
|
||||
.bit_idx = 7,
|
||||
.lock = &clk_lock,
|
||||
.lock = &meson_clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "clk81",
|
||||
.ops = &clk_gate_ops,
|
||||
|
@ -773,7 +773,7 @@ static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
|
|||
|
||||
reset = &meson8b_clk_reset_bits[id];
|
||||
|
||||
spin_lock_irqsave(&clk_lock, flags);
|
||||
spin_lock_irqsave(&meson_clk_lock, flags);
|
||||
|
||||
val = readl(meson8b_clk_reset->base + reset->reg);
|
||||
if (assert)
|
||||
|
@ -782,7 +782,7 @@ static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
|
|||
val &= ~BIT(reset->bit_idx);
|
||||
writel(val, meson8b_clk_reset->base + reset->reg);
|
||||
|
||||
spin_unlock_irqrestore(&clk_lock, flags);
|
||||
spin_unlock_irqrestore(&meson_clk_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -341,7 +341,7 @@ void __init cpg_mstp_add_clk_domain(struct device_node *np)
|
|||
return;
|
||||
|
||||
pd->name = np->name;
|
||||
pd->flags = GENPD_FLAG_PM_CLK;
|
||||
pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
|
||||
pd->attach_dev = cpg_mstp_attach_dev;
|
||||
pd->detach_dev = cpg_mstp_detach_dev;
|
||||
pm_genpd_init(pd, &pm_domain_always_on_gov, false);
|
||||
|
|
|
@ -115,6 +115,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
|
|||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
|
||||
DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
|
||||
DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("scif3", 204, R8A7796_CLK_S3D4),
|
||||
|
|
|
@ -105,6 +105,7 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
|
|||
DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("csi40", 716, R8A77970_CLK_CSI0),
|
||||
DEF_MOD("du0", 724, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("vin3", 808, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("vin2", 809, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
|
||||
|
|
|
@ -513,7 +513,7 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev,
|
|||
|
||||
genpd = &pd->genpd;
|
||||
genpd->name = np->name;
|
||||
genpd->flags = GENPD_FLAG_PM_CLK;
|
||||
genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
|
||||
genpd->attach_dev = cpg_mssr_attach_dev;
|
||||
genpd->detach_dev = cpg_mssr_detach_dev;
|
||||
pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
|
||||
|
|
|
@ -176,10 +176,10 @@ static const struct clk_ops clk_factors_ops = {
|
|||
.set_rate = clk_factors_set_rate,
|
||||
};
|
||||
|
||||
struct clk *sunxi_factors_register(struct device_node *node,
|
||||
const struct factors_data *data,
|
||||
spinlock_t *lock,
|
||||
void __iomem *reg)
|
||||
static struct clk *__sunxi_factors_register(struct device_node *node,
|
||||
const struct factors_data *data,
|
||||
spinlock_t *lock, void __iomem *reg,
|
||||
unsigned long flags)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_factors *factors;
|
||||
|
@ -249,7 +249,7 @@ struct clk *sunxi_factors_register(struct device_node *node,
|
|||
parents, i,
|
||||
mux_hw, &clk_mux_ops,
|
||||
&factors->hw, &clk_factors_ops,
|
||||
gate_hw, &clk_gate_ops, 0);
|
||||
gate_hw, &clk_gate_ops, CLK_IS_CRITICAL);
|
||||
if (IS_ERR(clk))
|
||||
goto err_register;
|
||||
|
||||
|
@ -272,6 +272,22 @@ err_factors:
|
|||
return NULL;
|
||||
}
|
||||
|
||||
struct clk *sunxi_factors_register(struct device_node *node,
|
||||
const struct factors_data *data,
|
||||
spinlock_t *lock,
|
||||
void __iomem *reg)
|
||||
{
|
||||
return __sunxi_factors_register(node, data, lock, reg, 0);
|
||||
}
|
||||
|
||||
struct clk *sunxi_factors_register_critical(struct device_node *node,
|
||||
const struct factors_data *data,
|
||||
spinlock_t *lock,
|
||||
void __iomem *reg)
|
||||
{
|
||||
return __sunxi_factors_register(node, data, lock, reg, CLK_IS_CRITICAL);
|
||||
}
|
||||
|
||||
void sunxi_factors_unregister(struct device_node *node, struct clk *clk)
|
||||
{
|
||||
struct clk_hw *hw = __clk_get_hw(clk);
|
||||
|
|
|
@ -55,6 +55,10 @@ struct clk *sunxi_factors_register(struct device_node *node,
|
|||
const struct factors_data *data,
|
||||
spinlock_t *lock,
|
||||
void __iomem *reg);
|
||||
struct clk *sunxi_factors_register_critical(struct device_node *node,
|
||||
const struct factors_data *data,
|
||||
spinlock_t *lock,
|
||||
void __iomem *reg);
|
||||
|
||||
void sunxi_factors_unregister(struct device_node *node, struct clk *clk);
|
||||
|
||||
|
|
|
@ -15,7 +15,6 @@
|
|||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
@ -155,7 +154,6 @@ static DEFINE_SPINLOCK(sun5i_a13_mbus_lock);
|
|||
|
||||
static void __init sun5i_a13_mbus_setup(struct device_node *node)
|
||||
{
|
||||
struct clk *mbus;
|
||||
void __iomem *reg;
|
||||
|
||||
reg = of_iomap(node, 0);
|
||||
|
@ -164,12 +162,9 @@ static void __init sun5i_a13_mbus_setup(struct device_node *node)
|
|||
return;
|
||||
}
|
||||
|
||||
mbus = sunxi_factors_register(node, &sun4i_a10_mod0_data,
|
||||
&sun5i_a13_mbus_lock, reg);
|
||||
|
||||
/* The MBUS clocks needs to be always enabled */
|
||||
__clk_get(mbus);
|
||||
clk_prepare_enable(mbus);
|
||||
sunxi_factors_register_critical(node, &sun4i_a10_mod0_data,
|
||||
&sun5i_a13_mbus_lock, reg);
|
||||
}
|
||||
CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup);
|
||||
|
||||
|
|
|
@ -15,7 +15,6 @@
|
|||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
@ -82,11 +81,12 @@ static void __init sun8i_a23_mbus_setup(struct device_node *node)
|
|||
mux->mask = SUN8I_MBUS_MUX_MASK;
|
||||
mux->lock = &sun8i_a23_mbus_lock;
|
||||
|
||||
/* The MBUS clocks needs to be always enabled */
|
||||
clk = clk_register_composite(NULL, clk_name, parents, num_parents,
|
||||
&mux->hw, &clk_mux_ops,
|
||||
&div->hw, &clk_divider_ops,
|
||||
&gate->hw, &clk_gate_ops,
|
||||
0);
|
||||
CLK_IS_CRITICAL);
|
||||
if (IS_ERR(clk))
|
||||
goto err_free_gate;
|
||||
|
||||
|
@ -95,9 +95,6 @@ static void __init sun8i_a23_mbus_setup(struct device_node *node)
|
|||
goto err_unregister_clk;
|
||||
|
||||
kfree(parents); /* parents is deep copied */
|
||||
/* The MBUS clocks needs to be always enabled */
|
||||
__clk_get(clk);
|
||||
clk_prepare_enable(clk);
|
||||
|
||||
return;
|
||||
|
||||
|
|
|
@ -15,7 +15,6 @@
|
|||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
@ -140,7 +139,6 @@ static DEFINE_SPINLOCK(sun9i_a80_gt_lock);
|
|||
static void __init sun9i_a80_gt_setup(struct device_node *node)
|
||||
{
|
||||
void __iomem *reg;
|
||||
struct clk *gt;
|
||||
|
||||
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
|
||||
if (IS_ERR(reg)) {
|
||||
|
@ -149,12 +147,9 @@ static void __init sun9i_a80_gt_setup(struct device_node *node)
|
|||
return;
|
||||
}
|
||||
|
||||
gt = sunxi_factors_register(node, &sun9i_a80_gt_data,
|
||||
&sun9i_a80_gt_lock, reg);
|
||||
|
||||
/* The GT bus clock needs to be always enabled */
|
||||
__clk_get(gt);
|
||||
clk_prepare_enable(gt);
|
||||
sunxi_factors_register_critical(node, &sun9i_a80_gt_data,
|
||||
&sun9i_a80_gt_lock, reg);
|
||||
}
|
||||
CLK_OF_DECLARE(sun9i_a80_gt, "allwinner,sun9i-a80-gt-clk", sun9i_a80_gt_setup);
|
||||
|
||||
|
|
|
@ -656,7 +656,8 @@ static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
|
|||
};
|
||||
|
||||
static struct clk * __init sunxi_mux_clk_setup(struct device_node *node,
|
||||
const struct mux_data *data)
|
||||
const struct mux_data *data,
|
||||
unsigned long flags)
|
||||
{
|
||||
struct clk *clk;
|
||||
const char *clk_name = node->name;
|
||||
|
@ -678,7 +679,7 @@ static struct clk * __init sunxi_mux_clk_setup(struct device_node *node,
|
|||
}
|
||||
|
||||
clk = clk_register_mux(NULL, clk_name, parents, i,
|
||||
CLK_SET_RATE_PARENT, reg,
|
||||
CLK_SET_RATE_PARENT | flags, reg,
|
||||
data->shift, SUNXI_MUX_GATE_WIDTH,
|
||||
0, &clk_lock);
|
||||
|
||||
|
@ -703,29 +704,22 @@ out_unmap:
|
|||
|
||||
static void __init sun4i_cpu_clk_setup(struct device_node *node)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
||||
clk = sunxi_mux_clk_setup(node, &sun4i_cpu_mux_data);
|
||||
if (!clk)
|
||||
return;
|
||||
|
||||
/* Protect CPU clock */
|
||||
__clk_get(clk);
|
||||
clk_prepare_enable(clk);
|
||||
sunxi_mux_clk_setup(node, &sun4i_cpu_mux_data, CLK_IS_CRITICAL);
|
||||
}
|
||||
CLK_OF_DECLARE(sun4i_cpu, "allwinner,sun4i-a10-cpu-clk",
|
||||
sun4i_cpu_clk_setup);
|
||||
|
||||
static void __init sun6i_ahb1_mux_clk_setup(struct device_node *node)
|
||||
{
|
||||
sunxi_mux_clk_setup(node, &sun6i_a31_ahb1_mux_data);
|
||||
sunxi_mux_clk_setup(node, &sun6i_a31_ahb1_mux_data, 0);
|
||||
}
|
||||
CLK_OF_DECLARE(sun6i_ahb1_mux, "allwinner,sun6i-a31-ahb1-mux-clk",
|
||||
sun6i_ahb1_mux_clk_setup);
|
||||
|
||||
static void __init sun8i_ahb2_clk_setup(struct device_node *node)
|
||||
{
|
||||
sunxi_mux_clk_setup(node, &sun8i_h3_ahb2_mux_data);
|
||||
sunxi_mux_clk_setup(node, &sun8i_h3_ahb2_mux_data, 0);
|
||||
}
|
||||
CLK_OF_DECLARE(sun8i_ahb2, "allwinner,sun8i-h3-ahb2-clk",
|
||||
sun8i_ahb2_clk_setup);
|
||||
|
@ -900,6 +894,7 @@ struct divs_data {
|
|||
u8 shift; /* otherwise it's a normal divisor with this shift */
|
||||
u8 pow; /* is it power-of-two based? */
|
||||
u8 gate; /* is it independently gateable? */
|
||||
bool critical;
|
||||
} div[SUNXI_DIVS_MAX_QTY];
|
||||
};
|
||||
|
||||
|
@ -915,7 +910,8 @@ static const struct divs_data pll5_divs_data __initconst = {
|
|||
.factors = &sun4i_pll5_data,
|
||||
.ndivs = 2,
|
||||
.div = {
|
||||
{ .shift = 0, .pow = 0, }, /* M, DDR */
|
||||
/* Protect PLL5_DDR */
|
||||
{ .shift = 0, .pow = 0, .critical = true }, /* M, DDR */
|
||||
{ .shift = 16, .pow = 1, }, /* P, other */
|
||||
/* No output for the base factor clock */
|
||||
}
|
||||
|
@ -1089,7 +1085,9 @@ static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
|
|||
NULL, NULL,
|
||||
rate_hw, rate_ops,
|
||||
gate_hw, &clk_gate_ops,
|
||||
clkflags);
|
||||
clkflags |
|
||||
data->div[i].critical ?
|
||||
CLK_IS_CRITICAL : 0);
|
||||
|
||||
WARN_ON(IS_ERR(clk_data->clks[i]));
|
||||
}
|
||||
|
@ -1117,15 +1115,7 @@ out_unmap:
|
|||
|
||||
static void __init sun4i_pll5_clk_setup(struct device_node *node)
|
||||
{
|
||||
struct clk **clks;
|
||||
|
||||
clks = sunxi_divs_clk_setup(node, &pll5_divs_data);
|
||||
if (!clks)
|
||||
return;
|
||||
|
||||
/* Protect PLL5_DDR */
|
||||
__clk_get(clks[0]);
|
||||
clk_prepare_enable(clks[0]);
|
||||
sunxi_divs_clk_setup(node, &pll5_divs_data);
|
||||
}
|
||||
CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
|
||||
sun4i_pll5_clk_setup);
|
||||
|
|
|
@ -1,30 +0,0 @@
|
|||
/*
|
||||
* include/asm-generic/clkdev.h
|
||||
*
|
||||
* Based on the ARM clkdev.h:
|
||||
* Copyright (C) 2008 Russell King.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Helper for the clk API to assist looking up a struct clk.
|
||||
*/
|
||||
#ifndef __ASM_CLKDEV_H
|
||||
#define __ASM_CLKDEV_H
|
||||
|
||||
#include <linux/slab.h>
|
||||
|
||||
#ifndef CONFIG_COMMON_CLK
|
||||
struct clk;
|
||||
|
||||
static inline int __clk_get(struct clk *clk) { return 1; }
|
||||
static inline void __clk_put(struct clk *clk) { }
|
||||
#endif
|
||||
|
||||
static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
|
||||
{
|
||||
return kzalloc(size, GFP_KERNEL);
|
||||
}
|
||||
|
||||
#endif
|
71
include/dt-bindings/clock/axg-clkc.h
Normal file
71
include/dt-bindings/clock/axg-clkc.h
Normal file
|
@ -0,0 +1,71 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/*
|
||||
* Meson-AXG clock tree IDs
|
||||
*
|
||||
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __AXG_CLKC_H
|
||||
#define __AXG_CLKC_H
|
||||
|
||||
#define CLKID_SYS_PLL 0
|
||||
#define CLKID_FIXED_PLL 1
|
||||
#define CLKID_FCLK_DIV2 2
|
||||
#define CLKID_FCLK_DIV3 3
|
||||
#define CLKID_FCLK_DIV4 4
|
||||
#define CLKID_FCLK_DIV5 5
|
||||
#define CLKID_FCLK_DIV7 6
|
||||
#define CLKID_GP0_PLL 7
|
||||
#define CLKID_CLK81 10
|
||||
#define CLKID_MPLL0 11
|
||||
#define CLKID_MPLL1 12
|
||||
#define CLKID_MPLL2 13
|
||||
#define CLKID_MPLL3 14
|
||||
#define CLKID_DDR 15
|
||||
#define CLKID_AUDIO_LOCKER 16
|
||||
#define CLKID_MIPI_DSI_HOST 17
|
||||
#define CLKID_ISA 18
|
||||
#define CLKID_PL301 19
|
||||
#define CLKID_PERIPHS 20
|
||||
#define CLKID_SPICC0 21
|
||||
#define CLKID_I2C 22
|
||||
#define CLKID_RNG0 23
|
||||
#define CLKID_UART0 24
|
||||
#define CLKID_MIPI_DSI_PHY 25
|
||||
#define CLKID_SPICC1 26
|
||||
#define CLKID_PCIE_A 27
|
||||
#define CLKID_PCIE_B 28
|
||||
#define CLKID_HIU_IFACE 29
|
||||
#define CLKID_ASSIST_MISC 30
|
||||
#define CLKID_SD_EMMC_B 31
|
||||
#define CLKID_SD_EMMC_C 32
|
||||
#define CLKID_DMA 33
|
||||
#define CLKID_SPI 34
|
||||
#define CLKID_AUDIO 35
|
||||
#define CLKID_ETH 36
|
||||
#define CLKID_UART1 37
|
||||
#define CLKID_G2D 38
|
||||
#define CLKID_USB0 39
|
||||
#define CLKID_USB1 40
|
||||
#define CLKID_RESET 41
|
||||
#define CLKID_USB 42
|
||||
#define CLKID_AHB_ARB0 43
|
||||
#define CLKID_EFUSE 44
|
||||
#define CLKID_BOOT_ROM 45
|
||||
#define CLKID_AHB_DATA_BUS 46
|
||||
#define CLKID_AHB_CTRL_BUS 47
|
||||
#define CLKID_USB1_DDR_BRIDGE 48
|
||||
#define CLKID_USB0_DDR_BRIDGE 49
|
||||
#define CLKID_MMC_PCLK 50
|
||||
#define CLKID_VPU_INTR 51
|
||||
#define CLKID_SEC_AHB_AHB3_BRIDGE 52
|
||||
#define CLKID_GIC 53
|
||||
#define CLKID_AO_MEDIA_CPU 54
|
||||
#define CLKID_AO_AHB_SRAM 55
|
||||
#define CLKID_AO_AHB_BUS 56
|
||||
#define CLKID_AO_IFACE 57
|
||||
#define CLKID_AO_I2C 58
|
||||
#define CLKID_SD_EMMC_B_CLK0 59
|
||||
#define CLKID_SD_EMMC_C_CLK0 60
|
||||
|
||||
#endif /* __AXG_CLKC_H */
|
|
@ -20,6 +20,8 @@
|
|||
* flags used across common struct clk. these flags should only affect the
|
||||
* top-level framework. custom flags for dealing with hardware specifics
|
||||
* belong in struct clk_foo
|
||||
*
|
||||
* Please update clk_flags[] in drivers/clk/clk.c when making changes here!
|
||||
*/
|
||||
#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
|
||||
#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
|
||||
|
|
|
@ -12,7 +12,7 @@
|
|||
#ifndef __CLKDEV_H
|
||||
#define __CLKDEV_H
|
||||
|
||||
#include <asm/clkdev.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
struct clk;
|
||||
struct clk_hw;
|
||||
|
@ -52,9 +52,4 @@ int clk_add_alias(const char *, const char *, const char *, struct device *);
|
|||
int clk_register_clkdev(struct clk *, const char *, const char *);
|
||||
int clk_hw_register_clkdev(struct clk_hw *, const char *, const char *);
|
||||
|
||||
#ifdef CONFIG_COMMON_CLK
|
||||
int __clk_get(struct clk *clk);
|
||||
void __clk_put(struct clk *clk);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
Loading…
Reference in a new issue