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MLK-13101 ARM: imx: correct the pll2's clock type on imx6sl 

On i,MX6SL, no NUM and DENUM register, so this PLL should not
be registered as IMX_PLLV3_GENERIC type PLL, it should be
registered as IMX_PLLV3_SYSV2.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
pull/10/head
Bai Ping 2016-08-24 10:27:58 +08:00 committed by Jason Liu
parent 8dd909b896
commit 4d5e3ec317
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/imx/clk-imx6sl.c
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@ -215,7 +215,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
/* type name parent_name base div_mask */
clks[IMX6SL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f);
clks[IMX6SL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_PLL2, "pll2", "osc", base + 0x30, 0x1);
clks[IMX6SL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
clks[IMX6SL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3);
clks[IMX6SL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f);
clks[IMX6SL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f);