irqchip fixes for v4.0 (round 2)
- GICv3 ITS
- Small batch of fixes discovered while writing the kvm ITS emulation
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Merge tag 'irqchip-fixes-4.0-2' of git://git.infradead.org/users/jcooper/linux
Pull irqchip fixes from Jason Cooper:
"This is the second round of fixes for irqchip. It contains some fixes
found while the arm64 guys were writing the kvm gicv3 its emulation.
GICv3 ITS:
- Small batch of fixes discovered while writing the kvm ITS emulation"
* tag 'irqchip-fixes-4.0-2' of git://git.infradead.org/users/jcooper/linux:
irqchip: gicv3-its: Use non-cacheable accesses when no shareability
irqchip: gicv3-its: Fix PROP/PEND and BASE/CBASE confusion
irqchip: gicv3-its: Fix device ID encoding
irqchip: gicv3-its: Fix encoding of collection's target redistributor
This commit is contained in:
Linus Torvalds
commit
4e8a4830dc
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@ -169,7 +169,7 @@ static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
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static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
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{
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cmd->raw_cmd[0] &= ~(0xffffUL << 32);
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cmd->raw_cmd[0] &= BIT_ULL(32) - 1;
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cmd->raw_cmd[0] |= ((u64)devid) << 32;
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}
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@ -802,6 +802,7 @@ static int its_alloc_tables(struct its_node *its)
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int i;
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int psz = SZ_64K;
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u64 shr = GITS_BASER_InnerShareable;
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u64 cache = GITS_BASER_WaWb;
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for (i = 0; i < GITS_BASER_NR_REGS; i++) {
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u64 val = readq_relaxed(its->base + GITS_BASER + i * 8);
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@ -848,7 +849,7 @@ retry_baser:
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val = (virt_to_phys(base) |
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(type << GITS_BASER_TYPE_SHIFT) |
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((entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
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GITS_BASER_WaWb |
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cache |
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shr |
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GITS_BASER_VALID);
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@ -874,9 +875,12 @@ retry_baser:
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* Shareability didn't stick. Just use
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* whatever the read reported, which is likely
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* to be the only thing this redistributor
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* supports.
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* supports. If that's zero, make it
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* non-cacheable as well.
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*/
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shr = tmp & GITS_BASER_SHAREABILITY_MASK;
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if (!shr)
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cache = GITS_BASER_nC;
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goto retry_baser;
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}
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@ -980,16 +984,39 @@ static void its_cpu_init_lpis(void)
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tmp = readq_relaxed(rbase + GICR_PROPBASER);
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if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
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if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
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/*
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* The HW reports non-shareable, we must
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* remove the cacheability attributes as
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* well.
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*/
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val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
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GICR_PROPBASER_CACHEABILITY_MASK);
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val |= GICR_PROPBASER_nC;
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writeq_relaxed(val, rbase + GICR_PROPBASER);
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}
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pr_info_once("GIC: using cache flushing for LPI property table\n");
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gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
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}
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/* set PENDBASE */
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val = (page_to_phys(pend_page) |
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GICR_PROPBASER_InnerShareable |
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GICR_PROPBASER_WaWb);
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GICR_PENDBASER_InnerShareable |
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GICR_PENDBASER_WaWb);
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writeq_relaxed(val, rbase + GICR_PENDBASER);
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tmp = readq_relaxed(rbase + GICR_PENDBASER);
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if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
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/*
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* The HW reports non-shareable, we must remove the
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* cacheability attributes as well.
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*/
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val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
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GICR_PENDBASER_CACHEABILITY_MASK);
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val |= GICR_PENDBASER_nC;
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writeq_relaxed(val, rbase + GICR_PENDBASER);
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}
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/* Enable LPIs */
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val = readl_relaxed(rbase + GICR_CTLR);
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@ -1026,7 +1053,7 @@ static void its_cpu_init_collection(void)
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* This ITS wants a linear CPU number.
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*/
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target = readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER);
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target = GICR_TYPER_CPU_NUMBER(target);
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target = GICR_TYPER_CPU_NUMBER(target) << 16;
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}
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/* Perform collection mapping */
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@ -1422,14 +1449,26 @@ static int its_probe(struct device_node *node, struct irq_domain *parent)
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writeq_relaxed(baser, its->base + GITS_CBASER);
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tmp = readq_relaxed(its->base + GITS_CBASER);
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writeq_relaxed(0, its->base + GITS_CWRITER);
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writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR);
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if ((tmp ^ baser) & GITS_BASER_SHAREABILITY_MASK) {
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if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
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if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
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/*
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* The HW reports non-shareable, we must
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* remove the cacheability attributes as
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* well.
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*/
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baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
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GITS_CBASER_CACHEABILITY_MASK);
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baser |= GITS_CBASER_nC;
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writeq_relaxed(baser, its->base + GITS_CBASER);
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}
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pr_info("ITS: using cache flushing for cmd queue\n");
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its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
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}
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writeq_relaxed(0, its->base + GITS_CWRITER);
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writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR);
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if (of_property_read_bool(its->msi_chip.of_node, "msi-controller")) {
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its->domain = irq_domain_add_tree(NULL, &its_domain_ops, its);
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if (!its->domain) {
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@ -126,8 +126,23 @@
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#define GICR_PROPBASER_WaWb (5U << 7)
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#define GICR_PROPBASER_RaWaWt (6U << 7)
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#define GICR_PROPBASER_RaWaWb (7U << 7)
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#define GICR_PROPBASER_CACHEABILITY_MASK (7U << 7)
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#define GICR_PROPBASER_IDBITS_MASK (0x1f)
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#define GICR_PENDBASER_NonShareable (0U << 10)
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#define GICR_PENDBASER_InnerShareable (1U << 10)
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#define GICR_PENDBASER_OuterShareable (2U << 10)
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#define GICR_PENDBASER_SHAREABILITY_MASK (3UL << 10)
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#define GICR_PENDBASER_nCnB (0U << 7)
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#define GICR_PENDBASER_nC (1U << 7)
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#define GICR_PENDBASER_RaWt (2U << 7)
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#define GICR_PENDBASER_RaWb (3U << 7)
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#define GICR_PENDBASER_WaWt (4U << 7)
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#define GICR_PENDBASER_WaWb (5U << 7)
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#define GICR_PENDBASER_RaWaWt (6U << 7)
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#define GICR_PENDBASER_RaWaWb (7U << 7)
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#define GICR_PENDBASER_CACHEABILITY_MASK (7U << 7)
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/*
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* Re-Distributor registers, offsets from SGI_base
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*/
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@ -182,6 +197,7 @@
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#define GITS_CBASER_WaWb (5UL << 59)
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#define GITS_CBASER_RaWaWt (6UL << 59)
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#define GITS_CBASER_RaWaWb (7UL << 59)
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#define GITS_CBASER_CACHEABILITY_MASK (7UL << 59)
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#define GITS_CBASER_NonShareable (0UL << 10)
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#define GITS_CBASER_InnerShareable (1UL << 10)
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#define GITS_CBASER_OuterShareable (2UL << 10)
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@ -198,6 +214,7 @@
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#define GITS_BASER_WaWb (5UL << 59)
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#define GITS_BASER_RaWaWt (6UL << 59)
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#define GITS_BASER_RaWaWb (7UL << 59)
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#define GITS_BASER_CACHEABILITY_MASK (7UL << 59)
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#define GITS_BASER_TYPE_SHIFT (56)
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#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
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#define GITS_BASER_ENTRY_SIZE_SHIFT (48)
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