tpm: drop 'iobase' from struct tpm_vendor_specific
Dropped the field 'iobase' from struct tpm_vendor_specific and migrated it to the private structures of tpm_atmel and tpm_tis. Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com> Reviewed-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Reviewed-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>steinar/wifi_calib_4_9_kernel
Christophe Ricard
Jarkko Sakkinen
parent
003d305d84
commit
4eea703caa
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@ -131,8 +131,6 @@ enum tpm2_startup_types {
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struct tpm_chip;
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struct tpm_vendor_specific {
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void __iomem *iobase; /* ioremapped address */
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int irq;
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int locality;
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@ -37,6 +37,7 @@ enum tpm_atmel_read_status {
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static int tpm_atml_recv(struct tpm_chip *chip, u8 *buf, size_t count)
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{
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struct tpm_atmel_priv *priv = chip->vendor.priv;
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u8 status, *hdr = buf;
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u32 size;
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int i;
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@ -47,12 +48,12 @@ static int tpm_atml_recv(struct tpm_chip *chip, u8 *buf, size_t count)
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return -EIO;
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for (i = 0; i < 6; i++) {
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status = ioread8(chip->vendor.iobase + 1);
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status = ioread8(priv->iobase + 1);
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if ((status & ATML_STATUS_DATA_AVAIL) == 0) {
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dev_err(&chip->dev, "error reading header\n");
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return -EIO;
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}
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*buf++ = ioread8(chip->vendor.iobase);
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*buf++ = ioread8(priv->iobase);
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}
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/* size of the data received */
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@ -63,7 +64,7 @@ static int tpm_atml_recv(struct tpm_chip *chip, u8 *buf, size_t count)
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dev_err(&chip->dev,
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"Recv size(%d) less than available space\n", size);
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for (; i < size; i++) { /* clear the waiting data anyway */
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status = ioread8(chip->vendor.iobase + 1);
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status = ioread8(priv->iobase + 1);
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if ((status & ATML_STATUS_DATA_AVAIL) == 0) {
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dev_err(&chip->dev, "error reading data\n");
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return -EIO;
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@ -74,16 +75,16 @@ static int tpm_atml_recv(struct tpm_chip *chip, u8 *buf, size_t count)
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/* read all the data available */
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for (; i < size; i++) {
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status = ioread8(chip->vendor.iobase + 1);
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status = ioread8(priv->iobase + 1);
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if ((status & ATML_STATUS_DATA_AVAIL) == 0) {
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dev_err(&chip->dev, "error reading data\n");
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return -EIO;
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}
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*buf++ = ioread8(chip->vendor.iobase);
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*buf++ = ioread8(priv->iobase);
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}
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/* make sure data available is gone */
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status = ioread8(chip->vendor.iobase + 1);
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status = ioread8(priv->iobase + 1);
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if (status & ATML_STATUS_DATA_AVAIL) {
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dev_err(&chip->dev, "data available is stuck\n");
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@ -95,12 +96,13 @@ static int tpm_atml_recv(struct tpm_chip *chip, u8 *buf, size_t count)
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static int tpm_atml_send(struct tpm_chip *chip, u8 *buf, size_t count)
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{
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struct tpm_atmel_priv *priv = chip->vendor.priv;
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int i;
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dev_dbg(&chip->dev, "tpm_atml_send:\n");
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for (i = 0; i < count; i++) {
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dev_dbg(&chip->dev, "%d 0x%x(%d)\n", i, buf[i], buf[i]);
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iowrite8(buf[i], chip->vendor.iobase);
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iowrite8(buf[i], priv->iobase);
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}
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return count;
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@ -108,12 +110,16 @@ static int tpm_atml_send(struct tpm_chip *chip, u8 *buf, size_t count)
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static void tpm_atml_cancel(struct tpm_chip *chip)
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{
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iowrite8(ATML_STATUS_ABORT, chip->vendor.iobase + 1);
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struct tpm_atmel_priv *priv = chip->vendor.priv;
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iowrite8(ATML_STATUS_ABORT, priv->iobase + 1);
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}
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static u8 tpm_atml_status(struct tpm_chip *chip)
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{
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return ioread8(chip->vendor.iobase + 1);
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struct tpm_atmel_priv *priv = chip->vendor.priv;
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return ioread8(priv->iobase + 1);
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}
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static bool tpm_atml_req_canceled(struct tpm_chip *chip, u8 status)
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@ -142,7 +148,7 @@ static void atml_plat_remove(void)
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tpm_chip_unregister(chip);
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if (priv->have_region)
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atmel_release_region(priv->base, priv->region_size);
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atmel_put_base_addr(chip->vendor.iobase);
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atmel_put_base_addr(priv->iobase);
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platform_device_unregister(pdev);
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}
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}
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@ -190,6 +196,7 @@ static int __init init_atmel(void)
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goto err_unreg_dev;
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}
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priv->iobase = iobase;
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priv->base = base;
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priv->have_region = have_region;
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priv->region_size = region_size;
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@ -200,7 +207,6 @@ static int __init init_atmel(void)
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goto err_unreg_dev;
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}
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chip->vendor.iobase = iobase;
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chip->vendor.priv = priv;
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rc = tpm_chip_register(chip);
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@ -26,6 +26,7 @@ struct tpm_atmel_priv {
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int region_size;
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int have_region;
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unsigned long base;
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void __iomem *iobase;
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};
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static inline struct tpm_atmel_priv *atmel_get_priv(struct tpm_chip *chip)
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@ -37,8 +38,8 @@ static inline struct tpm_atmel_priv *atmel_get_priv(struct tpm_chip *chip)
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#include <asm/prom.h>
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#define atmel_getb(chip, offset) readb(chip->vendor->iobase + offset);
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#define atmel_putb(val, chip, offset) writeb(val, chip->vendor->iobase + offset)
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#define atmel_getb(priv, offset) readb(priv->iobase + offset)
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#define atmel_putb(val, priv, offset) writeb(val, priv->iobase + offset)
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#define atmel_request_region request_mem_region
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#define atmel_release_region release_mem_region
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@ -94,6 +94,7 @@ struct tpm_info {
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#define TPM_RID(l) (0x0F04 | ((l) << 12))
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struct priv_data {
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void __iomem *iobase;
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u16 manufacturer_id;
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bool irq_tested;
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wait_queue_head_t int_queue;
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@ -128,9 +129,10 @@ static inline int is_itpm(struct acpi_device *dev)
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* correct values in the other bits.' */
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static int wait_startup(struct tpm_chip *chip, int l)
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{
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struct priv_data *priv = chip->vendor.priv;
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unsigned long stop = jiffies + chip->vendor.timeout_a;
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do {
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if (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
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if (ioread8(priv->iobase + TPM_ACCESS(l)) &
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TPM_ACCESS_VALID)
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return 0;
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msleep(TPM_TIMEOUT);
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@ -140,7 +142,9 @@ static int wait_startup(struct tpm_chip *chip, int l)
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static int check_locality(struct tpm_chip *chip, int l)
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{
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if ((ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
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struct priv_data *priv = chip->vendor.priv;
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if ((ioread8(priv->iobase + TPM_ACCESS(l)) &
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(TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) ==
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(TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID))
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return chip->vendor.locality = l;
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@ -150,11 +154,13 @@ static int check_locality(struct tpm_chip *chip, int l)
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static void release_locality(struct tpm_chip *chip, int l, int force)
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{
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if (force || (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
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struct priv_data *priv = chip->vendor.priv;
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if (force || (ioread8(priv->iobase + TPM_ACCESS(l)) &
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(TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) ==
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(TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID))
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iowrite8(TPM_ACCESS_ACTIVE_LOCALITY,
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chip->vendor.iobase + TPM_ACCESS(l));
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priv->iobase + TPM_ACCESS(l));
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}
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static int request_locality(struct tpm_chip *chip, int l)
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@ -167,7 +173,7 @@ static int request_locality(struct tpm_chip *chip, int l)
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return l;
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iowrite8(TPM_ACCESS_REQUEST_USE,
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chip->vendor.iobase + TPM_ACCESS(l));
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priv->iobase + TPM_ACCESS(l));
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stop = jiffies + chip->vendor.timeout_a;
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@ -200,19 +206,24 @@ again:
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static u8 tpm_tis_status(struct tpm_chip *chip)
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{
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return ioread8(chip->vendor.iobase +
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struct priv_data *priv = chip->vendor.priv;
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return ioread8(priv->iobase +
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TPM_STS(chip->vendor.locality));
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}
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static void tpm_tis_ready(struct tpm_chip *chip)
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{
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struct priv_data *priv = chip->vendor.priv;
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/* this causes the current command to be aborted */
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iowrite8(TPM_STS_COMMAND_READY,
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chip->vendor.iobase + TPM_STS(chip->vendor.locality));
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priv->iobase + TPM_STS(chip->vendor.locality));
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}
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static int get_burstcount(struct tpm_chip *chip)
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{
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struct priv_data *priv = chip->vendor.priv;
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unsigned long stop;
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int burstcnt;
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@ -220,9 +231,9 @@ static int get_burstcount(struct tpm_chip *chip)
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/* which timeout value, spec has 2 answers (c & d) */
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stop = jiffies + chip->vendor.timeout_d;
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do {
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burstcnt = ioread8(chip->vendor.iobase +
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burstcnt = ioread8(priv->iobase +
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TPM_STS(chip->vendor.locality) + 1);
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burstcnt += ioread8(chip->vendor.iobase +
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burstcnt += ioread8(priv->iobase +
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TPM_STS(chip->vendor.locality) +
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2) << 8;
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if (burstcnt)
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@ -234,6 +245,7 @@ static int get_burstcount(struct tpm_chip *chip)
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static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count)
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{
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struct priv_data *priv = chip->vendor.priv;
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int size = 0, burstcnt;
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while (size < count &&
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wait_for_tpm_stat(chip,
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@ -243,7 +255,7 @@ static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count)
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== 0) {
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burstcnt = get_burstcount(chip);
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for (; burstcnt > 0 && size < count; burstcnt--)
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buf[size++] = ioread8(chip->vendor.iobase +
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buf[size++] = ioread8(priv->iobase +
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TPM_DATA_FIFO(chip->vendor.
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locality));
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}
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@ -329,7 +341,7 @@ static int tpm_tis_send_data(struct tpm_chip *chip, u8 *buf, size_t len)
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while (count < len - 1) {
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burstcnt = get_burstcount(chip);
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for (; burstcnt > 0 && count < len - 1; burstcnt--) {
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iowrite8(buf[count], chip->vendor.iobase +
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iowrite8(buf[count], priv->iobase +
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TPM_DATA_FIFO(chip->vendor.locality));
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count++;
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}
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@ -345,7 +357,7 @@ static int tpm_tis_send_data(struct tpm_chip *chip, u8 *buf, size_t len)
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/* write last byte */
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iowrite8(buf[count],
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chip->vendor.iobase + TPM_DATA_FIFO(chip->vendor.locality));
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priv->iobase + TPM_DATA_FIFO(chip->vendor.locality));
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wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
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&priv->int_queue, false);
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status = tpm_tis_status(chip);
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@ -364,15 +376,15 @@ out_err:
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static void disable_interrupts(struct tpm_chip *chip)
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{
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struct priv_data *priv = chip->vendor.priv;
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u32 intmask;
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intmask =
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ioread32(chip->vendor.iobase +
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ioread32(priv->iobase +
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TPM_INT_ENABLE(chip->vendor.locality));
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intmask &= ~TPM_GLOBAL_INT_ENABLE;
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iowrite32(intmask,
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chip->vendor.iobase +
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TPM_INT_ENABLE(chip->vendor.locality));
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priv->iobase + TPM_INT_ENABLE(chip->vendor.locality));
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devm_free_irq(&chip->dev, chip->vendor.irq, chip);
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chip->vendor.irq = 0;
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}
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@ -384,6 +396,7 @@ static void disable_interrupts(struct tpm_chip *chip)
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*/
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static int tpm_tis_send_main(struct tpm_chip *chip, u8 *buf, size_t len)
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{
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struct priv_data *priv = chip->vendor.priv;
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int rc;
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u32 ordinal;
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unsigned long dur;
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@ -394,7 +407,7 @@ static int tpm_tis_send_main(struct tpm_chip *chip, u8 *buf, size_t len)
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/* go and do it */
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iowrite8(TPM_STS_GO,
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chip->vendor.iobase + TPM_STS(chip->vendor.locality));
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priv->iobase + TPM_STS(chip->vendor.locality));
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if (chip->vendor.irq) {
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ordinal = be32_to_cpu(*((__be32 *) (buf + 6)));
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@ -453,10 +466,11 @@ static const struct tis_vendor_timeout_override vendor_timeout_overrides[] = {
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static bool tpm_tis_update_timeouts(struct tpm_chip *chip,
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unsigned long *timeout_cap)
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{
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struct priv_data *priv = chip->vendor.priv;
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int i;
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u32 did_vid;
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did_vid = ioread32(chip->vendor.iobase + TPM_DID_VID(0));
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did_vid = ioread32(priv->iobase + TPM_DID_VID(0));
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for (i = 0; i != ARRAY_SIZE(vendor_timeout_overrides); i++) {
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if (vendor_timeout_overrides[i].did_vid != did_vid)
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@ -476,6 +490,7 @@ static bool tpm_tis_update_timeouts(struct tpm_chip *chip,
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*/
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static int probe_itpm(struct tpm_chip *chip)
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{
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struct priv_data *priv = chip->vendor.priv;
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int rc = 0;
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u8 cmd_getticks[] = {
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0x00, 0xc1, 0x00, 0x00, 0x00, 0x0a,
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@ -483,7 +498,7 @@ static int probe_itpm(struct tpm_chip *chip)
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};
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size_t len = sizeof(cmd_getticks);
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bool rem_itpm = itpm;
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u16 vendor = ioread16(chip->vendor.iobase + TPM_DID_VID(0));
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u16 vendor = ioread16(priv->iobase + TPM_DID_VID(0));
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/* probe only iTPMS */
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if (vendor != TPM_VID_INTEL)
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@ -548,7 +563,7 @@ static irqreturn_t tis_int_handler(int dummy, void *dev_id)
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u32 interrupt;
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int i;
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interrupt = ioread32(chip->vendor.iobase +
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interrupt = ioread32(priv->iobase +
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TPM_INT_STATUS(chip->vendor.locality));
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if (interrupt == 0)
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@ -568,9 +583,9 @@ static irqreturn_t tis_int_handler(int dummy, void *dev_id)
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/* Clear interrupts handled with TPM_EOI */
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iowrite32(interrupt,
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chip->vendor.iobase +
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priv->iobase +
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TPM_INT_STATUS(chip->vendor.locality));
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ioread32(chip->vendor.iobase + TPM_INT_STATUS(chip->vendor.locality));
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ioread32(priv->iobase + TPM_INT_STATUS(chip->vendor.locality));
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return IRQ_HANDLED;
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}
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@ -592,19 +607,19 @@ static int tpm_tis_probe_irq_single(struct tpm_chip *chip, u32 intmask,
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}
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chip->vendor.irq = irq;
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original_int_vec = ioread8(chip->vendor.iobase +
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original_int_vec = ioread8(priv->iobase +
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TPM_INT_VECTOR(chip->vendor.locality));
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iowrite8(irq,
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chip->vendor.iobase + TPM_INT_VECTOR(chip->vendor.locality));
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priv->iobase + TPM_INT_VECTOR(chip->vendor.locality));
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/* Clear all existing */
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iowrite32(ioread32(chip->vendor.iobase +
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iowrite32(ioread32(priv->iobase +
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TPM_INT_STATUS(chip->vendor.locality)),
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chip->vendor.iobase + TPM_INT_STATUS(chip->vendor.locality));
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priv->iobase + TPM_INT_STATUS(chip->vendor.locality));
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/* Turn on */
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iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
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chip->vendor.iobase + TPM_INT_ENABLE(chip->vendor.locality));
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priv->iobase + TPM_INT_ENABLE(chip->vendor.locality));
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priv->irq_tested = false;
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@ -621,8 +636,7 @@ static int tpm_tis_probe_irq_single(struct tpm_chip *chip, u32 intmask,
|
|||
*/
|
||||
if (!chip->vendor.irq) {
|
||||
iowrite8(original_int_vec,
|
||||
chip->vendor.iobase +
|
||||
TPM_INT_VECTOR(chip->vendor.locality));
|
||||
priv->iobase + TPM_INT_VECTOR(chip->vendor.locality));
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
|
@ -635,10 +649,11 @@ static int tpm_tis_probe_irq_single(struct tpm_chip *chip, u32 intmask,
|
|||
*/
|
||||
static void tpm_tis_probe_irq(struct tpm_chip *chip, u32 intmask)
|
||||
{
|
||||
struct priv_data *priv = chip->vendor.priv;
|
||||
u8 original_int_vec;
|
||||
int i;
|
||||
|
||||
original_int_vec = ioread8(chip->vendor.iobase +
|
||||
original_int_vec = ioread8(priv->iobase +
|
||||
TPM_INT_VECTOR(chip->vendor.locality));
|
||||
|
||||
if (!original_int_vec) {
|
||||
|
|
@ -658,7 +673,8 @@ MODULE_PARM_DESC(interrupts, "Enable interrupts");
|
|||
|
||||
static void tpm_tis_remove(struct tpm_chip *chip)
|
||||
{
|
||||
void __iomem *reg = chip->vendor.iobase +
|
||||
struct priv_data *priv = chip->vendor.priv;
|
||||
void __iomem *reg = priv->iobase +
|
||||
TPM_INT_ENABLE(chip->vendor.locality);
|
||||
|
||||
iowrite32(~TPM_GLOBAL_INT_ENABLE & ioread32(reg), reg);
|
||||
|
|
@ -686,9 +702,9 @@ static int tpm_tis_init(struct device *dev, struct tpm_info *tpm_info,
|
|||
chip->acpi_dev_handle = acpi_dev_handle;
|
||||
#endif
|
||||
|
||||
chip->vendor.iobase = devm_ioremap_resource(dev, &tpm_info->res);
|
||||
if (IS_ERR(chip->vendor.iobase))
|
||||
return PTR_ERR(chip->vendor.iobase);
|
||||
priv->iobase = devm_ioremap_resource(dev, &tpm_info->res);
|
||||
if (IS_ERR(priv->iobase))
|
||||
return PTR_ERR(priv->iobase);
|
||||
|
||||
/* Maximum timeouts */
|
||||
chip->vendor.timeout_a = TIS_TIMEOUT_A_MAX;
|
||||
|
|
@ -702,13 +718,13 @@ static int tpm_tis_init(struct device *dev, struct tpm_info *tpm_info,
|
|||
}
|
||||
|
||||
/* Take control of the TPM's interrupt hardware and shut it off */
|
||||
intmask = ioread32(chip->vendor.iobase +
|
||||
intmask = ioread32(priv->iobase +
|
||||
TPM_INT_ENABLE(chip->vendor.locality));
|
||||
intmask |= TPM_INTF_CMD_READY_INT | TPM_INTF_LOCALITY_CHANGE_INT |
|
||||
TPM_INTF_DATA_AVAIL_INT | TPM_INTF_STS_VALID_INT;
|
||||
intmask &= ~TPM_GLOBAL_INT_ENABLE;
|
||||
iowrite32(intmask,
|
||||
chip->vendor.iobase + TPM_INT_ENABLE(chip->vendor.locality));
|
||||
priv->iobase + TPM_INT_ENABLE(chip->vendor.locality));
|
||||
|
||||
if (request_locality(chip, 0) != 0) {
|
||||
rc = -ENODEV;
|
||||
|
|
@ -719,12 +735,12 @@ static int tpm_tis_init(struct device *dev, struct tpm_info *tpm_info,
|
|||
if (rc)
|
||||
goto out_err;
|
||||
|
||||
vendor = ioread32(chip->vendor.iobase + TPM_DID_VID(0));
|
||||
vendor = ioread32(priv->iobase + TPM_DID_VID(0));
|
||||
priv->manufacturer_id = vendor;
|
||||
|
||||
dev_info(dev, "%s TPM (device-id 0x%X, rev-id %d)\n",
|
||||
(chip->flags & TPM_CHIP_FLAG_TPM2) ? "2.0" : "1.2",
|
||||
vendor >> 16, ioread8(chip->vendor.iobase + TPM_RID(0)));
|
||||
vendor >> 16, ioread8(priv->iobase + TPM_RID(0)));
|
||||
|
||||
if (!itpm) {
|
||||
probe = probe_itpm(chip);
|
||||
|
|
@ -741,7 +757,7 @@ static int tpm_tis_init(struct device *dev, struct tpm_info *tpm_info,
|
|||
|
||||
/* Figure out the capabilities */
|
||||
intfcaps =
|
||||
ioread32(chip->vendor.iobase +
|
||||
ioread32(priv->iobase +
|
||||
TPM_INTF_CAPS(chip->vendor.locality));
|
||||
dev_dbg(dev, "TPM interface capabilities (0x%x):\n",
|
||||
intfcaps);
|
||||
|
|
@ -820,23 +836,23 @@ out_err:
|
|||
#ifdef CONFIG_PM_SLEEP
|
||||
static void tpm_tis_reenable_interrupts(struct tpm_chip *chip)
|
||||
{
|
||||
struct priv_data *priv = chip->vendor.priv;
|
||||
u32 intmask;
|
||||
|
||||
/* reenable interrupts that device may have lost or
|
||||
BIOS/firmware may have disabled */
|
||||
iowrite8(chip->vendor.irq, chip->vendor.iobase +
|
||||
iowrite8(chip->vendor.irq, priv->iobase +
|
||||
TPM_INT_VECTOR(chip->vendor.locality));
|
||||
|
||||
intmask =
|
||||
ioread32(chip->vendor.iobase +
|
||||
TPM_INT_ENABLE(chip->vendor.locality));
|
||||
ioread32(priv->iobase + TPM_INT_ENABLE(chip->vendor.locality));
|
||||
|
||||
intmask |= TPM_INTF_CMD_READY_INT
|
||||
| TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
|
||||
| TPM_INTF_STS_VALID_INT | TPM_GLOBAL_INT_ENABLE;
|
||||
|
||||
iowrite32(intmask,
|
||||
chip->vendor.iobase + TPM_INT_ENABLE(chip->vendor.locality));
|
||||
priv->iobase + TPM_INT_ENABLE(chip->vendor.locality));
|
||||
}
|
||||
|
||||
static int tpm_tis_resume(struct device *dev)
|
||||
|
|
|
|||
Loading…
Reference in New Issue