MIPS: cpu-probe: Set the write-combine CCA value on per core basis
Different cores use different CCA values to achieve write-combine memory writes. For cores that do not support write-combine we set the default value to CCA:2 (uncached, non-coherent) which is the default value as set by the kernel. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7402/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -79,6 +79,11 @@ struct cpuinfo_mips {
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#define NUM_WATCH_REGS 4
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u16 watch_reg_masks[NUM_WATCH_REGS];
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unsigned int kscratch_mask; /* Usable KScratch mask. */
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/*
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* Cache Coherency attribute for write-combine memory writes.
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* (shifted by _CACHE_SHIFT)
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*/
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unsigned int writecombine;
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} __attribute__((aligned(SMP_CACHE_BYTES)));
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extern struct cpuinfo_mips cpu_data[];
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@ -27,6 +27,7 @@
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#include <asm/msa.h>
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#include <asm/watch.h>
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#include <asm/elf.h>
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#include <asm/pgtable-bits.h>
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#include <asm/spram.h>
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#include <asm/uaccess.h>
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@ -764,6 +765,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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break;
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case PRID_REV_LOONGSON3A:
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c->cputype = CPU_LOONGSON3;
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c->writecombine = _CACHE_UNCACHED_ACCELERATED;
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__cpu_name[cpu] = "ICT Loongson-3";
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set_elf_platform(cpu, "loongson3a");
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break;
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@ -798,67 +800,83 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
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{
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c->writecombine = _CACHE_UNCACHED_ACCELERATED;
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switch (c->processor_id & PRID_IMP_MASK) {
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case PRID_IMP_4KC:
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c->cputype = CPU_4KC;
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c->writecombine = _CACHE_UNCACHED;
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__cpu_name[cpu] = "MIPS 4Kc";
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break;
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case PRID_IMP_4KEC:
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case PRID_IMP_4KECR2:
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c->cputype = CPU_4KEC;
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c->writecombine = _CACHE_UNCACHED;
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__cpu_name[cpu] = "MIPS 4KEc";
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break;
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case PRID_IMP_4KSC:
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case PRID_IMP_4KSD:
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c->cputype = CPU_4KSC;
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c->writecombine = _CACHE_UNCACHED;
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__cpu_name[cpu] = "MIPS 4KSc";
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break;
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case PRID_IMP_5KC:
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c->cputype = CPU_5KC;
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c->writecombine = _CACHE_UNCACHED;
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__cpu_name[cpu] = "MIPS 5Kc";
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break;
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case PRID_IMP_5KE:
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c->cputype = CPU_5KE;
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c->writecombine = _CACHE_UNCACHED;
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__cpu_name[cpu] = "MIPS 5KE";
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break;
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case PRID_IMP_20KC:
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c->cputype = CPU_20KC;
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c->writecombine = _CACHE_UNCACHED;
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__cpu_name[cpu] = "MIPS 20Kc";
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break;
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case PRID_IMP_24K:
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c->cputype = CPU_24K;
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c->writecombine = _CACHE_UNCACHED;
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__cpu_name[cpu] = "MIPS 24Kc";
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break;
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case PRID_IMP_24KE:
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c->cputype = CPU_24K;
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c->writecombine = _CACHE_UNCACHED;
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__cpu_name[cpu] = "MIPS 24KEc";
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break;
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case PRID_IMP_25KF:
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c->cputype = CPU_25KF;
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c->writecombine = _CACHE_UNCACHED;
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__cpu_name[cpu] = "MIPS 25Kc";
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break;
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case PRID_IMP_34K:
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c->cputype = CPU_34K;
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c->writecombine = _CACHE_UNCACHED;
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__cpu_name[cpu] = "MIPS 34Kc";
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break;
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case PRID_IMP_74K:
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c->cputype = CPU_74K;
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c->writecombine = _CACHE_UNCACHED;
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__cpu_name[cpu] = "MIPS 74Kc";
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break;
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case PRID_IMP_M14KC:
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c->cputype = CPU_M14KC;
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c->writecombine = _CACHE_UNCACHED;
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__cpu_name[cpu] = "MIPS M14Kc";
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break;
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case PRID_IMP_M14KEC:
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c->cputype = CPU_M14KEC;
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c->writecombine = _CACHE_UNCACHED;
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__cpu_name[cpu] = "MIPS M14KEc";
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break;
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case PRID_IMP_1004K:
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c->cputype = CPU_1004K;
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c->writecombine = _CACHE_UNCACHED;
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__cpu_name[cpu] = "MIPS 1004Kc";
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break;
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case PRID_IMP_1074K:
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c->cputype = CPU_1074K;
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c->writecombine = _CACHE_UNCACHED;
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__cpu_name[cpu] = "MIPS 1074Kc";
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break;
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case PRID_IMP_INTERAPTIV_UP:
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@ -932,6 +950,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
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{
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decode_configs(c);
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c->writecombine = _CACHE_UNCACHED_ACCELERATED;
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switch (c->processor_id & PRID_IMP_MASK) {
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case PRID_IMP_SB1:
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c->cputype = CPU_SB1;
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@ -1063,6 +1082,7 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
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switch (c->processor_id & PRID_IMP_MASK) {
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case PRID_IMP_JZRISC:
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c->cputype = CPU_JZRISC;
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c->writecombine = _CACHE_UNCACHED_ACCELERATED;
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__cpu_name[cpu] = "Ingenic JZRISC";
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break;
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default:
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@ -1169,6 +1189,7 @@ void cpu_probe(void)
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c->processor_id = PRID_IMP_UNKNOWN;
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c->fpu_id = FPIR_IMP_NONE;
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c->cputype = CPU_UNKNOWN;
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c->writecombine = _CACHE_UNCACHED;
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c->processor_id = read_c0_prid();
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switch (c->processor_id & PRID_COMP_MASK) {
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