gpu: ipu-v3: Add ipu_idmac_lock_enable()
Adds ipu_idmac_lock_enable(), which enables or disables channel burst locking. Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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@ -305,6 +305,75 @@ void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
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}
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}
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EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
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EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
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static const struct {
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int chnum;
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u32 reg;
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int shift;
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} idmac_lock_en_info[] = {
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{ .chnum = 5, .reg = IDMAC_CH_LOCK_EN_1, .shift = 0, },
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{ .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift = 2, },
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{ .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift = 4, },
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{ .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift = 6, },
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{ .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift = 8, },
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{ .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, },
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{ .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, },
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{ .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, },
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{ .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, },
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{ .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, },
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{ .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, },
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{ .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift = 0, },
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{ .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift = 2, },
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{ .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift = 4, },
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{ .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift = 6, },
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{ .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift = 8, },
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{ .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, },
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};
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int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
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{
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struct ipu_soc *ipu = channel->ipu;
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unsigned long flags;
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u32 bursts, regval;
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int i;
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switch (num_bursts) {
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case 0:
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case 1:
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bursts = 0x00; /* locking disabled */
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break;
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case 2:
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bursts = 0x01;
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break;
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case 4:
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bursts = 0x02;
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break;
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case 8:
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bursts = 0x03;
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break;
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default:
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return -EINVAL;
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}
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for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
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if (channel->num == idmac_lock_en_info[i].chnum)
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break;
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}
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if (i >= ARRAY_SIZE(idmac_lock_en_info))
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return -EINVAL;
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spin_lock_irqsave(&ipu->lock, flags);
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regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg);
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regval &= ~(0x03 << idmac_lock_en_info[i].shift);
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regval |= (bursts << idmac_lock_en_info[i].shift);
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ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg);
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spin_unlock_irqrestore(&ipu->lock, flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable);
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int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
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int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
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{
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{
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unsigned long lock_flags;
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unsigned long lock_flags;
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@ -161,6 +161,7 @@ void ipu_idmac_put(struct ipuv3_channel *);
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int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
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int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
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int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
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int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
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void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
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void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
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int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
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int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
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int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
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void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
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void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
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