MLK-19413-24 gpu: imx: dpu: common: Add store9 support for sync mode fixup

Bit16 of store9's PIXENGCFG_STATIC register is used to control
the sync mode fixup logic implemented in store9.  So, let's
add store9 support in the DPU core driver and export a function
for users to enable/disable the fixup logic.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

drivers/gpu/imx/dpu/Makefile

@@ -4,4 +4,4 @@ imx-dpu-core-objs := dpu-common.o dpu-constframe.o dpu-disengcfg.o \
 		     dpu-extdst.o dpu-fetchdecode.o dpu-fetcheco.o \
 		     dpu-fetchlayer.o dpu-fetchwarp.o dpu-fetchunit.o \
 		     dpu-framegen.o dpu-hscaler.o dpu-layerblend.o \
-		     dpu-tcon.o dpu-vscaler.o
+		     dpu-store.o dpu-tcon.o dpu-vscaler.o

drivers/gpu/imx/dpu/dpu-common.c

@@ -201,6 +201,12 @@ static const unsigned long lb_pec_ofss_v1[] = {0xd00, 0xd20, 0xd40, 0xd60,
 					       0xd80, 0xda0, 0xdc0};
 static const unsigned long lb_pec_ofss_v2[] = {0xba0, 0xbc0, 0xbe0, 0xc00};
 
+/* Store Unit */
+static const unsigned long st_ofss_v1[] = {0x4000};
+static const unsigned long st_ofss_v2[] = {0x4000};
+static const unsigned long st_pec_ofss_v1[] = {0x960};
+static const unsigned long st_pec_ofss_v2[] = {0x940};
+
 /* Timing Controller Unit */
 static const unsigned long tcon_ofss_v1[] = {0x12000, 0x13c00};
 static const unsigned long tcon_ofss_v2[] = {0xcc00, 0xe800};
@@ -374,6 +380,22 @@ static const struct dpu_unit lbs_v2 = {
 	.ofss = lb_ofss_v2,
 };
 
+static const struct dpu_unit sts_v1 = {
+	.name = "Store",
+	.num = ARRAY_SIZE(st_ids),
+	.ids = st_ids,
+	.pec_ofss = st_pec_ofss_v1,
+	.ofss = st_ofss_v1,
+};
+
+static const struct dpu_unit sts_v2 = {
+	.name = "Store",
+	.num = ARRAY_SIZE(st_ids),
+	.ids = st_ids,
+	.pec_ofss = st_pec_ofss_v2,
+	.ofss = st_ofss_v2,
+};
+
 static const struct dpu_unit tcons_v1 = {
 	.name = "TCon",
 	.num = ARRAY_SIZE(tcon_ids),
@@ -534,6 +556,7 @@ static const struct dpu_devtype dpu_type_v1 = {
 	.fws = &fws_v1,
 	.hss = &hss_v1,
 	.lbs = &lbs_v1,
+	.sts = &sts_v1,
 	.tcons = &tcons_v1,
 	.vss = &vss_v1,
 	.cm_reg_ofs = &cm_reg_ofs_v1,
@@ -564,6 +587,7 @@ static const struct dpu_devtype dpu_type_v2_qm = {
 	.fws = &fws_v2,
 	.hss = &hss_v2,
 	.lbs = &lbs_v2,
+	.sts = &sts_v2,
 	.tcons = &tcons_v2,
 	.vss = &vss_v2,
 	.cm_reg_ofs = &cm_reg_ofs_v2,
@@ -598,6 +622,7 @@ static const struct dpu_devtype dpu_type_v2_qxp = {
 	.fws = &fws_v2,
 	.hss = &hss_v2,
 	.lbs = &lbs_v2,
+	.sts = &sts_v2,
 	.tcons = &tcons_v2,
 	.vss = &vss_v2,
 	.cm_reg_ofs = &cm_reg_ofs_v2,
@@ -838,6 +863,7 @@ static int dpu_submodules_init(struct dpu_soc *dpu,
 	DPU_UNITS_INIT(fw);
 	DPU_UNITS_INIT(hs);
 	DPU_UNITS_INIT(lb);
+	DPU_UNITS_INIT(st);
 	DPU_UNITS_INIT(tcon);
 	DPU_UNITS_INIT(vs);
 
@@ -1766,6 +1792,7 @@ static int dpu_probe(struct platform_device *pdev)
 	DPU_UNITS_ADDR_DBG(fw);
 	DPU_UNITS_ADDR_DBG(hs);
 	DPU_UNITS_ADDR_DBG(lb);
+	DPU_UNITS_ADDR_DBG(st);
 	DPU_UNITS_ADDR_DBG(tcon);
 	DPU_UNITS_ADDR_DBG(vs);
 

drivers/gpu/imx/dpu/dpu-prv.h

@@ -192,6 +192,7 @@ struct dpu_devtype {
 	const struct dpu_unit *fws;
 	const struct dpu_unit *hss;
 	const struct dpu_unit *lbs;
+	const struct dpu_unit *sts;
 	const struct dpu_unit *tcons;
 	const struct dpu_unit *vss;
 	const struct cm_reg_ofs *cm_reg_ofs;
@@ -253,6 +254,7 @@ struct dpu_soc {
 	struct dpu_fetchunit	*fw_priv[1];
 	struct dpu_hscaler	*hs_priv[3];
 	struct dpu_layerblend	*lb_priv[7];
+	struct dpu_store	*st_priv[1];
 	struct dpu_tcon		*tcon_priv[2];
 	struct dpu_vscaler	*vs_priv[3];
 };
@@ -293,6 +295,7 @@ DECLARE_DPU_UNIT_INIT_FUNC(fl);
 DECLARE_DPU_UNIT_INIT_FUNC(fw);
 DECLARE_DPU_UNIT_INIT_FUNC(hs);
 DECLARE_DPU_UNIT_INIT_FUNC(lb);
+DECLARE_DPU_UNIT_INIT_FUNC(st);
 DECLARE_DPU_UNIT_INIT_FUNC(tcon);
 DECLARE_DPU_UNIT_INIT_FUNC(vs);
 
@@ -340,6 +343,7 @@ static const unsigned int fl_ids[] = {0, 1};
 static const unsigned int fw_ids[] = {2};
 static const unsigned int hs_ids[] = {4, 5, 9};
 static const unsigned int lb_ids[] = {0, 1, 2, 3, 4, 5, 6};
+static const unsigned int st_ids[] = {9};
 static const unsigned int tcon_ids[] = {0, 1};
 static const unsigned int vs_ids[] = {4, 5, 9};
 

drivers/gpu/imx/dpu/dpu-store.c

@@ -0,0 +1,137 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include "dpu-prv.h"
+
+#define PIXENGCFG_STATIC		0x8
+
+struct dpu_store {
+	void __iomem *pec_base;
+	void __iomem *base;
+	struct mutex mutex;
+	int id;
+	bool inuse;
+	struct dpu_soc *dpu;
+};
+
+static inline u32 dpu_pec_st_read(struct dpu_store *st, unsigned int offset)
+{
+	return readl(st->pec_base + offset);
+}
+
+static inline void dpu_pec_st_write(struct dpu_store *st, u32 value,
+				    unsigned int offset)
+{
+	writel(value, st->pec_base + offset);
+}
+
+void store_pixengcfg_syncmode_fixup(struct dpu_store *st, bool enable)
+{
+	struct dpu_soc *dpu;
+	u32 val;
+
+	if (!st)
+		return;
+
+	dpu = st->dpu;
+
+	if (!dpu->devtype->has_syncmode_fixup)
+		return;
+
+	mutex_lock(&st->mutex);
+	val = dpu_pec_st_read(st, PIXENGCFG_STATIC);
+	if (enable)
+		val |= BIT(16);
+	else
+		val &= ~BIT(16);
+	dpu_pec_st_write(st, val, PIXENGCFG_STATIC);
+	mutex_unlock(&st->mutex);
+}
+EXPORT_SYMBOL_GPL(store_pixengcfg_syncmode_fixup);
+
+struct dpu_store *dpu_st_get(struct dpu_soc *dpu, int id)
+{
+	struct dpu_store *st;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(st_ids); i++)
+		if (st_ids[i] == id)
+			break;
+
+	if (i == ARRAY_SIZE(st_ids))
+		return ERR_PTR(-EINVAL);
+
+	st = dpu->st_priv[i];
+
+	mutex_lock(&st->mutex);
+
+	if (st->inuse) {
+		mutex_unlock(&st->mutex);
+		return ERR_PTR(-EBUSY);
+	}
+
+	st->inuse = true;
+
+	mutex_unlock(&st->mutex);
+
+	return st;
+}
+EXPORT_SYMBOL_GPL(dpu_st_get);
+
+void dpu_st_put(struct dpu_store *st)
+{
+	mutex_lock(&st->mutex);
+
+	st->inuse = false;
+
+	mutex_unlock(&st->mutex);
+}
+EXPORT_SYMBOL_GPL(dpu_st_put);
+
+int dpu_st_init(struct dpu_soc *dpu, unsigned int id,
+		unsigned long pec_base, unsigned long base)
+{
+	struct dpu_store *st;
+	int i;
+
+	st = devm_kzalloc(dpu->dev, sizeof(*st), GFP_KERNEL);
+	if (!st)
+		return -ENOMEM;
+
+	for (i = 0; i < ARRAY_SIZE(st_ids); i++)
+		if (st_ids[i] == id)
+			break;
+
+	dpu->st_priv[i] = st;
+
+	st->pec_base = devm_ioremap(dpu->dev, pec_base, SZ_32);
+	if (!st->pec_base)
+		return -ENOMEM;
+
+	st->base = devm_ioremap(dpu->dev, base, SZ_256);
+	if (!st->base)
+		return -ENOMEM;
+
+	st->dpu = dpu;
+	st->id = id;
+
+	mutex_init(&st->mutex);
+
+	return 0;
+}

include/video/dpu.h

@@ -667,6 +667,12 @@ u32 layerblend_perfresult(struct dpu_layerblend *lb);
 struct dpu_layerblend *dpu_lb_get(struct dpu_soc *dpu, int id);
 void dpu_lb_put(struct dpu_layerblend *lb);
 
+/* Store Unit */
+struct dpu_store;
+void store_pixengcfg_syncmode_fixup(struct dpu_store *st, bool enable);
+struct dpu_store *dpu_st_get(struct dpu_soc *dpu, int id);
+void dpu_st_put(struct dpu_store *st);
+
 /* Timing Controller Unit */
 struct dpu_tcon;
 int tcon_set_fmt(struct dpu_tcon *tcon, u32 bus_format);