powerpc: move debug registers in a structure
This way we can use same data type struct with KVM and also help in using other debug related function. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Acked-by: Michael Neuling <mikey@neuling.org> [scottwood@freescale.com: removed obvious debug_reg comment] Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
parent
660970fe97
commit
51ae8d4a2b
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@ -167,21 +167,7 @@ struct thread_vr_state {
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vector128 vscr __attribute__((aligned(16)));
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};
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struct thread_struct {
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unsigned long ksp; /* Kernel stack pointer */
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#ifdef CONFIG_PPC64
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unsigned long ksp_vsid;
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#endif
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struct pt_regs *regs; /* Pointer to saved register state */
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mm_segment_t fs; /* for get_fs() validation */
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#ifdef CONFIG_BOOKE
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/* BookE base exception scratch space; align on cacheline */
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unsigned long normsave[8] ____cacheline_aligned;
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#endif
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#ifdef CONFIG_PPC32
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void *pgdir; /* root of page-table tree */
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unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
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#endif
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struct debug_reg {
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#ifdef CONFIG_PPC_ADV_DEBUG_REGS
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/*
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* The following help to manage the use of Debug Control Registers
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@ -218,6 +204,24 @@ struct thread_struct {
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unsigned long dvc2;
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#endif
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#endif
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};
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struct thread_struct {
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unsigned long ksp; /* Kernel stack pointer */
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#ifdef CONFIG_PPC64
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unsigned long ksp_vsid;
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#endif
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struct pt_regs *regs; /* Pointer to saved register state */
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mm_segment_t fs; /* for get_fs() validation */
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#ifdef CONFIG_BOOKE
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/* BookE base exception scratch space; align on cacheline */
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unsigned long normsave[8] ____cacheline_aligned;
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#endif
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#ifdef CONFIG_PPC32
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void *pgdir; /* root of page-table tree */
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unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
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#endif
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struct debug_reg debug;
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struct thread_fp_state fp_state;
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struct thread_fp_state *fp_save_area;
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int fpexc_mode; /* floating-point exception mode */
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@ -381,7 +381,7 @@
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#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */
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#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
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#define dbcr_iac_range(task) ((task)->thread.dbcr0)
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#define dbcr_iac_range(task) ((task)->thread.debug.dbcr0)
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#define DBCR_IAC12I DBCR0_IA12 /* Range Inclusive */
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#define DBCR_IAC12X (DBCR0_IA12 | DBCR0_IA12X) /* Range Exclusive */
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#define DBCR_IAC12MODE (DBCR0_IA12 | DBCR0_IA12X) /* IAC 1-2 Mode Bits */
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@ -395,7 +395,7 @@
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#define DBCR1_DAC1W 0x20000000 /* DAC1 Write Debug Event */
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#define DBCR1_DAC2W 0x10000000 /* DAC2 Write Debug Event */
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#define dbcr_dac(task) ((task)->thread.dbcr1)
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#define dbcr_dac(task) ((task)->thread.debug.dbcr1)
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#define DBCR_DAC1R DBCR1_DAC1R
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#define DBCR_DAC1W DBCR1_DAC1W
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#define DBCR_DAC2R DBCR1_DAC2R
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@ -441,7 +441,7 @@
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#define DBCR0_CRET 0x00000020 /* Critical Return Debug Event */
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#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
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#define dbcr_dac(task) ((task)->thread.dbcr0)
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#define dbcr_dac(task) ((task)->thread.debug.dbcr0)
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#define DBCR_DAC1R DBCR0_DAC1R
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#define DBCR_DAC1W DBCR0_DAC1W
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#define DBCR_DAC2R DBCR0_DAC2R
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@ -475,7 +475,7 @@
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#define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */
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#define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */
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#define dbcr_iac_range(task) ((task)->thread.dbcr1)
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#define dbcr_iac_range(task) ((task)->thread.debug.dbcr1)
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#define DBCR_IAC12I DBCR1_IAC12M /* Range Inclusive */
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#define DBCR_IAC12X DBCR1_IAC12MX /* Range Exclusive */
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#define DBCR_IAC12MODE DBCR1_IAC12MX /* IAC 1-2 Mode Bits */
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@ -115,7 +115,7 @@ int main(void)
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#endif /* CONFIG_SPE */
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#endif /* CONFIG_PPC64 */
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#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
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DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, dbcr0));
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DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, debug.dbcr0));
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#endif
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#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
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DEFINE(THREAD_KVM_SVCPU, offsetof(struct thread_struct, kvm_shadow_vcpu));
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@ -314,28 +314,28 @@ static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
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*/
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static void set_debug_reg_defaults(struct thread_struct *thread)
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{
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thread->iac1 = thread->iac2 = 0;
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thread->debug.iac1 = thread->debug.iac2 = 0;
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#if CONFIG_PPC_ADV_DEBUG_IACS > 2
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thread->iac3 = thread->iac4 = 0;
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thread->debug.iac3 = thread->debug.iac4 = 0;
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#endif
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thread->dac1 = thread->dac2 = 0;
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thread->debug.dac1 = thread->debug.dac2 = 0;
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#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
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thread->dvc1 = thread->dvc2 = 0;
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thread->debug.dvc1 = thread->debug.dvc2 = 0;
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#endif
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thread->dbcr0 = 0;
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thread->debug.dbcr0 = 0;
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#ifdef CONFIG_BOOKE
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/*
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* Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
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*/
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thread->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
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thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
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DBCR1_IAC3US | DBCR1_IAC4US;
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/*
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* Force Data Address Compare User/Supervisor bits to be User-only
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* (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
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*/
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thread->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
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thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
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#else
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thread->dbcr1 = 0;
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thread->debug.dbcr1 = 0;
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#endif
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}
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@ -348,22 +348,22 @@ static void prime_debug_regs(struct thread_struct *thread)
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*/
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mtmsr(mfmsr() & ~MSR_DE);
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mtspr(SPRN_IAC1, thread->iac1);
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mtspr(SPRN_IAC2, thread->iac2);
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mtspr(SPRN_IAC1, thread->debug.iac1);
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mtspr(SPRN_IAC2, thread->debug.iac2);
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#if CONFIG_PPC_ADV_DEBUG_IACS > 2
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mtspr(SPRN_IAC3, thread->iac3);
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mtspr(SPRN_IAC4, thread->iac4);
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mtspr(SPRN_IAC3, thread->debug.iac3);
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mtspr(SPRN_IAC4, thread->debug.iac4);
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#endif
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mtspr(SPRN_DAC1, thread->dac1);
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mtspr(SPRN_DAC2, thread->dac2);
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mtspr(SPRN_DAC1, thread->debug.dac1);
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mtspr(SPRN_DAC2, thread->debug.dac2);
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#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
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mtspr(SPRN_DVC1, thread->dvc1);
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mtspr(SPRN_DVC2, thread->dvc2);
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mtspr(SPRN_DVC1, thread->debug.dvc1);
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mtspr(SPRN_DVC2, thread->debug.dvc2);
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#endif
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mtspr(SPRN_DBCR0, thread->dbcr0);
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mtspr(SPRN_DBCR1, thread->dbcr1);
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mtspr(SPRN_DBCR0, thread->debug.dbcr0);
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mtspr(SPRN_DBCR1, thread->debug.dbcr1);
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#ifdef CONFIG_BOOKE
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mtspr(SPRN_DBCR2, thread->dbcr2);
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mtspr(SPRN_DBCR2, thread->debug.dbcr2);
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#endif
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}
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/*
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@ -373,8 +373,8 @@ static void prime_debug_regs(struct thread_struct *thread)
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*/
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static void switch_booke_debug_regs(struct thread_struct *new_thread)
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{
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if ((current->thread.dbcr0 & DBCR0_IDM)
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|| (new_thread->dbcr0 & DBCR0_IDM))
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if ((current->thread.debug.dbcr0 & DBCR0_IDM)
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|| (new_thread->debug.dbcr0 & DBCR0_IDM))
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prime_debug_regs(new_thread);
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}
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#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
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@ -855,8 +855,8 @@ void user_enable_single_step(struct task_struct *task)
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if (regs != NULL) {
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#ifdef CONFIG_PPC_ADV_DEBUG_REGS
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task->thread.dbcr0 &= ~DBCR0_BT;
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task->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
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task->thread.debug.dbcr0 &= ~DBCR0_BT;
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task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
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regs->msr |= MSR_DE;
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#else
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regs->msr &= ~MSR_BE;
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@ -872,8 +872,8 @@ void user_enable_block_step(struct task_struct *task)
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if (regs != NULL) {
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#ifdef CONFIG_PPC_ADV_DEBUG_REGS
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task->thread.dbcr0 &= ~DBCR0_IC;
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task->thread.dbcr0 = DBCR0_IDM | DBCR0_BT;
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task->thread.debug.dbcr0 &= ~DBCR0_IC;
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task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT;
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regs->msr |= MSR_DE;
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#else
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regs->msr &= ~MSR_SE;
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@ -895,16 +895,16 @@ void user_disable_single_step(struct task_struct *task)
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* And, after doing so, if all debug flags are off, turn
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* off DBCR0(IDM) and MSR(DE) .... Torez
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*/
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task->thread.dbcr0 &= ~DBCR0_IC;
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task->thread.debug.dbcr0 &= ~DBCR0_IC;
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/*
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* Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
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*/
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if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0,
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task->thread.dbcr1)) {
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if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
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task->thread.debug.dbcr1)) {
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/*
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* All debug events were off.....
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*/
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task->thread.dbcr0 &= ~DBCR0_IDM;
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task->thread.debug.dbcr0 &= ~DBCR0_IDM;
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regs->msr &= ~MSR_DE;
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}
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#else
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@ -1023,14 +1023,14 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
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*/
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/* DAC's hold the whole address without any mode flags */
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task->thread.dac1 = data & ~0x3UL;
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task->thread.debug.dac1 = data & ~0x3UL;
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if (task->thread.dac1 == 0) {
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if (task->thread.debug.dac1 == 0) {
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dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
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if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0,
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task->thread.dbcr1)) {
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if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
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task->thread.debug.dbcr1)) {
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task->thread.regs->msr &= ~MSR_DE;
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task->thread.dbcr0 &= ~DBCR0_IDM;
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task->thread.debug.dbcr0 &= ~DBCR0_IDM;
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}
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return 0;
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}
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@ -1042,7 +1042,7 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
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/* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
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register */
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task->thread.dbcr0 |= DBCR0_IDM;
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task->thread.debug.dbcr0 |= DBCR0_IDM;
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/* Check for write and read flags and set DBCR0
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accordingly */
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@ -1072,10 +1072,10 @@ static long set_instruction_bp(struct task_struct *child,
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struct ppc_hw_breakpoint *bp_info)
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{
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int slot;
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int slot1_in_use = ((child->thread.dbcr0 & DBCR0_IAC1) != 0);
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int slot2_in_use = ((child->thread.dbcr0 & DBCR0_IAC2) != 0);
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int slot3_in_use = ((child->thread.dbcr0 & DBCR0_IAC3) != 0);
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int slot4_in_use = ((child->thread.dbcr0 & DBCR0_IAC4) != 0);
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int slot1_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC1) != 0);
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int slot2_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC2) != 0);
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int slot3_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC3) != 0);
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int slot4_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC4) != 0);
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if (dbcr_iac_range(child) & DBCR_IAC12MODE)
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slot2_in_use = 1;
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@ -1094,9 +1094,9 @@ static long set_instruction_bp(struct task_struct *child,
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/* We need a pair of IAC regsisters */
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if ((!slot1_in_use) && (!slot2_in_use)) {
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slot = 1;
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child->thread.iac1 = bp_info->addr;
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child->thread.iac2 = bp_info->addr2;
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child->thread.dbcr0 |= DBCR0_IAC1;
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child->thread.debug.iac1 = bp_info->addr;
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child->thread.debug.iac2 = bp_info->addr2;
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child->thread.debug.dbcr0 |= DBCR0_IAC1;
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if (bp_info->addr_mode ==
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PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
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dbcr_iac_range(child) |= DBCR_IAC12X;
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@ -1105,9 +1105,9 @@ static long set_instruction_bp(struct task_struct *child,
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#if CONFIG_PPC_ADV_DEBUG_IACS > 2
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} else if ((!slot3_in_use) && (!slot4_in_use)) {
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slot = 3;
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child->thread.iac3 = bp_info->addr;
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child->thread.iac4 = bp_info->addr2;
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child->thread.dbcr0 |= DBCR0_IAC3;
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child->thread.debug.iac3 = bp_info->addr;
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child->thread.debug.iac4 = bp_info->addr2;
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child->thread.debug.dbcr0 |= DBCR0_IAC3;
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if (bp_info->addr_mode ==
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PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
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dbcr_iac_range(child) |= DBCR_IAC34X;
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@ -1127,30 +1127,30 @@ static long set_instruction_bp(struct task_struct *child,
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*/
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if (slot2_in_use || (slot3_in_use == slot4_in_use)) {
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slot = 1;
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child->thread.iac1 = bp_info->addr;
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child->thread.dbcr0 |= DBCR0_IAC1;
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child->thread.debug.iac1 = bp_info->addr;
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child->thread.debug.dbcr0 |= DBCR0_IAC1;
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goto out;
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}
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}
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if (!slot2_in_use) {
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slot = 2;
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child->thread.iac2 = bp_info->addr;
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child->thread.dbcr0 |= DBCR0_IAC2;
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child->thread.debug.iac2 = bp_info->addr;
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child->thread.debug.dbcr0 |= DBCR0_IAC2;
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#if CONFIG_PPC_ADV_DEBUG_IACS > 2
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} else if (!slot3_in_use) {
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slot = 3;
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child->thread.iac3 = bp_info->addr;
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child->thread.dbcr0 |= DBCR0_IAC3;
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child->thread.debug.iac3 = bp_info->addr;
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child->thread.debug.dbcr0 |= DBCR0_IAC3;
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} else if (!slot4_in_use) {
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slot = 4;
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child->thread.iac4 = bp_info->addr;
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child->thread.dbcr0 |= DBCR0_IAC4;
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child->thread.debug.iac4 = bp_info->addr;
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child->thread.debug.dbcr0 |= DBCR0_IAC4;
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#endif
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} else
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return -ENOSPC;
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}
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out:
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child->thread.dbcr0 |= DBCR0_IDM;
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child->thread.debug.dbcr0 |= DBCR0_IDM;
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child->thread.regs->msr |= MSR_DE;
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return slot;
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@ -1160,49 +1160,49 @@ static int del_instruction_bp(struct task_struct *child, int slot)
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{
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switch (slot) {
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case 1:
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if ((child->thread.dbcr0 & DBCR0_IAC1) == 0)
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if ((child->thread.debug.dbcr0 & DBCR0_IAC1) == 0)
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return -ENOENT;
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if (dbcr_iac_range(child) & DBCR_IAC12MODE) {
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/* address range - clear slots 1 & 2 */
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child->thread.iac2 = 0;
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child->thread.debug.iac2 = 0;
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dbcr_iac_range(child) &= ~DBCR_IAC12MODE;
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}
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child->thread.iac1 = 0;
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child->thread.dbcr0 &= ~DBCR0_IAC1;
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child->thread.debug.iac1 = 0;
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child->thread.debug.dbcr0 &= ~DBCR0_IAC1;
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break;
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case 2:
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if ((child->thread.dbcr0 & DBCR0_IAC2) == 0)
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if ((child->thread.debug.dbcr0 & DBCR0_IAC2) == 0)
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return -ENOENT;
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if (dbcr_iac_range(child) & DBCR_IAC12MODE)
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/* used in a range */
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return -EINVAL;
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child->thread.iac2 = 0;
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child->thread.dbcr0 &= ~DBCR0_IAC2;
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child->thread.debug.iac2 = 0;
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child->thread.debug.dbcr0 &= ~DBCR0_IAC2;
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break;
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#if CONFIG_PPC_ADV_DEBUG_IACS > 2
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case 3:
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if ((child->thread.dbcr0 & DBCR0_IAC3) == 0)
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if ((child->thread.debug.dbcr0 & DBCR0_IAC3) == 0)
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return -ENOENT;
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if (dbcr_iac_range(child) & DBCR_IAC34MODE) {
|
||||
/* address range - clear slots 3 & 4 */
|
||||
child->thread.iac4 = 0;
|
||||
child->thread.debug.iac4 = 0;
|
||||
dbcr_iac_range(child) &= ~DBCR_IAC34MODE;
|
||||
}
|
||||
child->thread.iac3 = 0;
|
||||
child->thread.dbcr0 &= ~DBCR0_IAC3;
|
||||
child->thread.debug.iac3 = 0;
|
||||
child->thread.debug.dbcr0 &= ~DBCR0_IAC3;
|
||||
break;
|
||||
case 4:
|
||||
if ((child->thread.dbcr0 & DBCR0_IAC4) == 0)
|
||||
if ((child->thread.debug.dbcr0 & DBCR0_IAC4) == 0)
|
||||
return -ENOENT;
|
||||
|
||||
if (dbcr_iac_range(child) & DBCR_IAC34MODE)
|
||||
/* Used in a range */
|
||||
return -EINVAL;
|
||||
child->thread.iac4 = 0;
|
||||
child->thread.dbcr0 &= ~DBCR0_IAC4;
|
||||
child->thread.debug.iac4 = 0;
|
||||
child->thread.debug.dbcr0 &= ~DBCR0_IAC4;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
|
@ -1232,18 +1232,18 @@ static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
|
|||
dbcr_dac(child) |= DBCR_DAC1R;
|
||||
if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
|
||||
dbcr_dac(child) |= DBCR_DAC1W;
|
||||
child->thread.dac1 = (unsigned long)bp_info->addr;
|
||||
child->thread.debug.dac1 = (unsigned long)bp_info->addr;
|
||||
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
|
||||
if (byte_enable) {
|
||||
child->thread.dvc1 =
|
||||
child->thread.debug.dvc1 =
|
||||
(unsigned long)bp_info->condition_value;
|
||||
child->thread.dbcr2 |=
|
||||
child->thread.debug.dbcr2 |=
|
||||
((byte_enable << DBCR2_DVC1BE_SHIFT) |
|
||||
(condition_mode << DBCR2_DVC1M_SHIFT));
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
|
||||
} else if (child->thread.dbcr2 & DBCR2_DAC12MODE) {
|
||||
} else if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
|
||||
/* Both dac1 and dac2 are part of a range */
|
||||
return -ENOSPC;
|
||||
#endif
|
||||
|
@ -1253,19 +1253,19 @@ static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
|
|||
dbcr_dac(child) |= DBCR_DAC2R;
|
||||
if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
|
||||
dbcr_dac(child) |= DBCR_DAC2W;
|
||||
child->thread.dac2 = (unsigned long)bp_info->addr;
|
||||
child->thread.debug.dac2 = (unsigned long)bp_info->addr;
|
||||
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
|
||||
if (byte_enable) {
|
||||
child->thread.dvc2 =
|
||||
child->thread.debug.dvc2 =
|
||||
(unsigned long)bp_info->condition_value;
|
||||
child->thread.dbcr2 |=
|
||||
child->thread.debug.dbcr2 |=
|
||||
((byte_enable << DBCR2_DVC2BE_SHIFT) |
|
||||
(condition_mode << DBCR2_DVC2M_SHIFT));
|
||||
}
|
||||
#endif
|
||||
} else
|
||||
return -ENOSPC;
|
||||
child->thread.dbcr0 |= DBCR0_IDM;
|
||||
child->thread.debug.dbcr0 |= DBCR0_IDM;
|
||||
child->thread.regs->msr |= MSR_DE;
|
||||
|
||||
return slot + 4;
|
||||
|
@ -1277,32 +1277,32 @@ static int del_dac(struct task_struct *child, int slot)
|
|||
if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0)
|
||||
return -ENOENT;
|
||||
|
||||
child->thread.dac1 = 0;
|
||||
child->thread.debug.dac1 = 0;
|
||||
dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W);
|
||||
#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
|
||||
if (child->thread.dbcr2 & DBCR2_DAC12MODE) {
|
||||
child->thread.dac2 = 0;
|
||||
child->thread.dbcr2 &= ~DBCR2_DAC12MODE;
|
||||
if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
|
||||
child->thread.debug.dac2 = 0;
|
||||
child->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
|
||||
}
|
||||
child->thread.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
|
||||
child->thread.debug.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
|
||||
#endif
|
||||
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
|
||||
child->thread.dvc1 = 0;
|
||||
child->thread.debug.dvc1 = 0;
|
||||
#endif
|
||||
} else if (slot == 2) {
|
||||
if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0)
|
||||
return -ENOENT;
|
||||
|
||||
#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
|
||||
if (child->thread.dbcr2 & DBCR2_DAC12MODE)
|
||||
if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE)
|
||||
/* Part of a range */
|
||||
return -EINVAL;
|
||||
child->thread.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
|
||||
child->thread.debug.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
|
||||
#endif
|
||||
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
|
||||
child->thread.dvc2 = 0;
|
||||
child->thread.debug.dvc2 = 0;
|
||||
#endif
|
||||
child->thread.dac2 = 0;
|
||||
child->thread.debug.dac2 = 0;
|
||||
dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W);
|
||||
} else
|
||||
return -EINVAL;
|
||||
|
@ -1344,22 +1344,22 @@ static int set_dac_range(struct task_struct *child,
|
|||
return -EIO;
|
||||
}
|
||||
|
||||
if (child->thread.dbcr0 &
|
||||
if (child->thread.debug.dbcr0 &
|
||||
(DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W))
|
||||
return -ENOSPC;
|
||||
|
||||
if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
|
||||
child->thread.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
|
||||
child->thread.debug.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
|
||||
if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
|
||||
child->thread.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
|
||||
child->thread.dac1 = bp_info->addr;
|
||||
child->thread.dac2 = bp_info->addr2;
|
||||
child->thread.debug.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
|
||||
child->thread.debug.dac1 = bp_info->addr;
|
||||
child->thread.debug.dac2 = bp_info->addr2;
|
||||
if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
|
||||
child->thread.dbcr2 |= DBCR2_DAC12M;
|
||||
child->thread.debug.dbcr2 |= DBCR2_DAC12M;
|
||||
else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
|
||||
child->thread.dbcr2 |= DBCR2_DAC12MX;
|
||||
child->thread.debug.dbcr2 |= DBCR2_DAC12MX;
|
||||
else /* PPC_BREAKPOINT_MODE_MASK */
|
||||
child->thread.dbcr2 |= DBCR2_DAC12MM;
|
||||
child->thread.debug.dbcr2 |= DBCR2_DAC12MM;
|
||||
child->thread.regs->msr |= MSR_DE;
|
||||
|
||||
return 5;
|
||||
|
@ -1490,9 +1490,9 @@ static long ppc_del_hwdebug(struct task_struct *child, long data)
|
|||
rc = del_dac(child, (int)data - 4);
|
||||
|
||||
if (!rc) {
|
||||
if (!DBCR_ACTIVE_EVENTS(child->thread.dbcr0,
|
||||
child->thread.dbcr1)) {
|
||||
child->thread.dbcr0 &= ~DBCR0_IDM;
|
||||
if (!DBCR_ACTIVE_EVENTS(child->thread.debug.dbcr0,
|
||||
child->thread.debug.dbcr1)) {
|
||||
child->thread.debug.dbcr0 &= ~DBCR0_IDM;
|
||||
child->thread.regs->msr &= ~MSR_DE;
|
||||
}
|
||||
}
|
||||
|
@ -1670,7 +1670,7 @@ long arch_ptrace(struct task_struct *child, long request,
|
|||
if (addr > 0)
|
||||
break;
|
||||
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
||||
ret = put_user(child->thread.dac1, datalp);
|
||||
ret = put_user(child->thread.debug.dac1, datalp);
|
||||
#else
|
||||
dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) |
|
||||
(child->thread.hw_brk.type & HW_BRK_TYPE_DABR));
|
||||
|
|
|
@ -266,7 +266,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
|
|||
if (addr > 0)
|
||||
break;
|
||||
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
||||
ret = put_user(child->thread.dac1, (u32 __user *)data);
|
||||
ret = put_user(child->thread.debug.dac1, (u32 __user *)data);
|
||||
#else
|
||||
dabr_fake = (
|
||||
(child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) |
|
||||
|
|
|
@ -1312,7 +1312,7 @@ int sys_debug_setcontext(struct ucontext __user *ctx,
|
|||
unsigned char tmp;
|
||||
unsigned long new_msr = regs->msr;
|
||||
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
||||
unsigned long new_dbcr0 = current->thread.dbcr0;
|
||||
unsigned long new_dbcr0 = current->thread.debug.dbcr0;
|
||||
#endif
|
||||
|
||||
for (i=0; i<ndbg; i++) {
|
||||
|
@ -1327,7 +1327,7 @@ int sys_debug_setcontext(struct ucontext __user *ctx,
|
|||
} else {
|
||||
new_dbcr0 &= ~DBCR0_IC;
|
||||
if (!DBCR_ACTIVE_EVENTS(new_dbcr0,
|
||||
current->thread.dbcr1)) {
|
||||
current->thread.debug.dbcr1)) {
|
||||
new_msr &= ~MSR_DE;
|
||||
new_dbcr0 &= ~DBCR0_IDM;
|
||||
}
|
||||
|
@ -1362,7 +1362,7 @@ int sys_debug_setcontext(struct ucontext __user *ctx,
|
|||
the user is really doing something wrong. */
|
||||
regs->msr = new_msr;
|
||||
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
||||
current->thread.dbcr0 = new_dbcr0;
|
||||
current->thread.debug.dbcr0 = new_dbcr0;
|
||||
#endif
|
||||
|
||||
if (!access_ok(VERIFY_READ, ctx, sizeof(*ctx))
|
||||
|
|
|
@ -351,8 +351,8 @@ static inline int check_io_access(struct pt_regs *regs)
|
|||
#define REASON_TRAP ESR_PTR
|
||||
|
||||
/* single-step stuff */
|
||||
#define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
|
||||
#define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
|
||||
#define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
|
||||
#define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
|
||||
|
||||
#else
|
||||
/* On non-4xx, the reason for the machine check or program
|
||||
|
@ -1489,7 +1489,7 @@ static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
|
|||
if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
|
||||
dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
|
||||
#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
|
||||
current->thread.dbcr2 &= ~DBCR2_DAC12MODE;
|
||||
current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
|
||||
#endif
|
||||
do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
|
||||
5);
|
||||
|
@ -1500,24 +1500,24 @@ static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
|
|||
6);
|
||||
changed |= 0x01;
|
||||
} else if (debug_status & DBSR_IAC1) {
|
||||
current->thread.dbcr0 &= ~DBCR0_IAC1;
|
||||
current->thread.debug.dbcr0 &= ~DBCR0_IAC1;
|
||||
dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
|
||||
do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
|
||||
1);
|
||||
changed |= 0x01;
|
||||
} else if (debug_status & DBSR_IAC2) {
|
||||
current->thread.dbcr0 &= ~DBCR0_IAC2;
|
||||
current->thread.debug.dbcr0 &= ~DBCR0_IAC2;
|
||||
do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
|
||||
2);
|
||||
changed |= 0x01;
|
||||
} else if (debug_status & DBSR_IAC3) {
|
||||
current->thread.dbcr0 &= ~DBCR0_IAC3;
|
||||
current->thread.debug.dbcr0 &= ~DBCR0_IAC3;
|
||||
dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
|
||||
do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
|
||||
3);
|
||||
changed |= 0x01;
|
||||
} else if (debug_status & DBSR_IAC4) {
|
||||
current->thread.dbcr0 &= ~DBCR0_IAC4;
|
||||
current->thread.debug.dbcr0 &= ~DBCR0_IAC4;
|
||||
do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
|
||||
4);
|
||||
changed |= 0x01;
|
||||
|
@ -1527,19 +1527,20 @@ static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
|
|||
* Check all other debug flags and see if that bit needs to be turned
|
||||
* back on or not.
|
||||
*/
|
||||
if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1))
|
||||
if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
|
||||
current->thread.debug.dbcr1))
|
||||
regs->msr |= MSR_DE;
|
||||
else
|
||||
/* Make sure the IDM flag is off */
|
||||
current->thread.dbcr0 &= ~DBCR0_IDM;
|
||||
current->thread.debug.dbcr0 &= ~DBCR0_IDM;
|
||||
|
||||
if (changed & 0x01)
|
||||
mtspr(SPRN_DBCR0, current->thread.dbcr0);
|
||||
mtspr(SPRN_DBCR0, current->thread.debug.dbcr0);
|
||||
}
|
||||
|
||||
void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
|
||||
{
|
||||
current->thread.dbsr = debug_status;
|
||||
current->thread.debug.dbsr = debug_status;
|
||||
|
||||
/* Hack alert: On BookE, Branch Taken stops on the branch itself, while
|
||||
* on server, it stops on the target of the branch. In order to simulate
|
||||
|
@ -1556,8 +1557,8 @@ void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
|
|||
|
||||
/* Do the single step trick only when coming from userspace */
|
||||
if (user_mode(regs)) {
|
||||
current->thread.dbcr0 &= ~DBCR0_BT;
|
||||
current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
|
||||
current->thread.debug.dbcr0 &= ~DBCR0_BT;
|
||||
current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
|
||||
regs->msr |= MSR_DE;
|
||||
return;
|
||||
}
|
||||
|
@ -1585,13 +1586,13 @@ void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
|
|||
return;
|
||||
|
||||
if (user_mode(regs)) {
|
||||
current->thread.dbcr0 &= ~DBCR0_IC;
|
||||
if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0,
|
||||
current->thread.dbcr1))
|
||||
current->thread.debug.dbcr0 &= ~DBCR0_IC;
|
||||
if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
|
||||
current->thread.debug.dbcr1))
|
||||
regs->msr |= MSR_DE;
|
||||
else
|
||||
/* Make sure the IDM bit is off */
|
||||
current->thread.dbcr0 &= ~DBCR0_IDM;
|
||||
current->thread.debug.dbcr0 &= ~DBCR0_IDM;
|
||||
}
|
||||
|
||||
_exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
|
||||
|
|
Loading…
Reference in a new issue