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Staging: delete tty drivers

Browse source 
Delete the drivers/staging/tty drivers as no one has wanted to step up
and maintain and fix them.  This was discussed in commit
4a6514e6d0 (tty: move obsolete and broken
tty drivers to drivers/staging/tty/)

Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: Jiri Slaby <jslaby@suse.cz>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Greg Kroah-Hartman 2011-07-06 16:48:28 -07:00
parent bb2a97e9cc
commit 51c9d654c2
34 changed files with 0 additions and 29526 deletions
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2
drivers/staging/Kconfig
View file

@ -24,8 +24,6 @@ menuconfig STAGING
if STAGING
source "drivers/staging/tty/Kconfig"
source "drivers/staging/et131x/Kconfig"
source "drivers/staging/slicoss/Kconfig"

1
drivers/staging/Makefile
View file

@ -3,7 +3,6 @@
# fix for build system bug...
obj-$(CONFIG_STAGING) += staging.o
obj-y += tty/
obj-$(CONFIG_ET131X) += et131x/
obj-$(CONFIG_SLICOSS) += slicoss/
obj-$(CONFIG_VIDEO_GO7007) += go7007/

87
drivers/staging/tty/Kconfig
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@ -1,87 +0,0 @@
config STALLION
tristate "Stallion EasyIO or EC8/32 support"
depends on STALDRV && (ISA || EISA || PCI)
help
If you have an EasyIO or EasyConnection 8/32 multiport Stallion
card, then this is for you; say Y. Make sure to read
<file:Documentation/serial/stallion.txt>.
To compile this driver as a module, choose M here: the
module will be called stallion.
config ISTALLION
tristate "Stallion EC8/64, ONboard, Brumby support"
depends on STALDRV && (ISA || EISA || PCI)
help
If you have an EasyConnection 8/64, ONboard, Brumby or Stallion
serial multiport card, say Y here. Make sure to read
<file:Documentation/serial/stallion.txt>.
To compile this driver as a module, choose M here: the
module will be called istallion.
config DIGIEPCA
tristate "Digiboard Intelligent Async Support"
depends on SERIAL_NONSTANDARD && (ISA || EISA || PCI)
---help---
This is a driver for Digi International's Xx, Xeve, and Xem series
of cards which provide multiple serial ports. You would need
something like this to connect more than two modems to your Linux
box, for instance in order to become a dial-in server. This driver
supports the original PC (ISA) boards as well as PCI, and EISA. If
you have a card like this, say Y here and read the file
<file:Documentation/serial/digiepca.txt>.
To compile this driver as a module, choose M here: the
module will be called epca.
config RISCOM8
tristate "SDL RISCom/8 card support"
depends on SERIAL_NONSTANDARD
help
This is a driver for the SDL Communications RISCom/8 multiport card,
which gives you many serial ports. You would need something like
this to connect more than two modems to your Linux box, for instance
in order to become a dial-in server. If you have a card like that,
say Y here and read the file <file:Documentation/serial/riscom8.txt>.
Also it's possible to say M here and compile this driver as kernel
loadable module; the module will be called riscom8.
config SPECIALIX
tristate "Specialix IO8+ card support"
depends on SERIAL_NONSTANDARD
help
This is a driver for the Specialix IO8+ multiport card (both the
ISA and the PCI version) which gives you many serial ports. You
would need something like this to connect more than two modems to
your Linux box, for instance in order to become a dial-in server.
If you have a card like that, say Y here and read the file
<file:Documentation/serial/specialix.txt>. Also it's possible to say
M here and compile this driver as kernel loadable module which will be
called specialix.
config COMPUTONE
tristate "Computone IntelliPort Plus serial support"
depends on SERIAL_NONSTANDARD && (ISA || EISA || PCI)
---help---
This driver supports the entire family of Intelliport II/Plus
controllers with the exception of the MicroChannel controllers and
products previous to the Intelliport II. These are multiport cards,
which give you many serial ports. You would need something like this
to connect more than two modems to your Linux box, for instance in
order to become a dial-in server. If you have a card like that, say
Y here and read <file:Documentation/serial/computone.txt>.
To compile this driver as module, choose M here: the
module will be called ip2.
config SERIAL167
bool "CD2401 support for MVME166/7 serial ports"
depends on MVME16x
help
This is the driver for the serial ports on the Motorola MVME166,
167, and 172 boards. Everyone using one of these boards should say
Y here.

7
drivers/staging/tty/Makefile
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@ -1,7 +0,0 @@
obj-$(CONFIG_STALLION) += stallion.o
obj-$(CONFIG_ISTALLION) += istallion.o
obj-$(CONFIG_DIGIEPCA) += epca.o
obj-$(CONFIG_SERIAL167) += serial167.o
obj-$(CONFIG_SPECIALIX) += specialix.o
obj-$(CONFIG_RISCOM8) += riscom8.o
obj-$(CONFIG_COMPUTONE) += ip2/

6
drivers/staging/tty/TODO
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@ -1,6 +0,0 @@
These are a few tty/serial drivers that either do not build,
or work if they do build, or if they seem to work, are for obsolete
hardware, or are full of unfixable races and no one uses them anymore.
If no one steps up to adopt any of these drivers, they will be removed
in the 2.6.41 release.

263
drivers/staging/tty/cd1865.h
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@ -1,263 +0,0 @@
/*
* linux/drivers/char/cd1865.h -- Definitions relating to the CD1865
* for the Specialix IO8+ multiport serial driver.
*
* Copyright (C) 1997 Roger Wolff (R.E.Wolff@BitWizard.nl)
* Copyright (C) 1994-1996 Dmitry Gorodchanin (pgmdsg@ibi.com)
*
* Specialix pays for the development and support of this driver.
* Please DO contact io8-linux@specialix.co.uk if you require
* support.
*
* This driver was developed in the BitWizard linux device
* driver service. If you require a linux device driver for your
* product, please contact devices@BitWizard.nl for a quote.
*
*/
/*
* Definitions for Driving CD180/CD1864/CD1865 based eightport serial cards.
*/
/* Values of choice for Interrupt ACKs */
/* These values are "obligatory" if you use the register based
* interrupt acknowledgements. See page 99-101 of V2.0 of the CD1865
* databook */
#define SX_ACK_MINT 0x75 /* goes to PILR1 */
#define SX_ACK_TINT 0x76 /* goes to PILR2 */
#define SX_ACK_RINT 0x77 /* goes to PILR3 */
/* Chip ID (is used when chips ar daisy chained.) */
#define SX_ID 0x10
/* Definitions for Cirrus Logic CL-CD186x 8-port async mux chip */
#define CD186x_NCH 8 /* Total number of channels */
#define CD186x_TPC 16 /* Ticks per character */
#define CD186x_NFIFO 8 /* TX FIFO size */
/* Global registers */
#define CD186x_GIVR 0x40 /* Global Interrupt Vector Register */
#define CD186x_GICR 0x41 /* Global Interrupting Channel Register */
#define CD186x_PILR1 0x61 /* Priority Interrupt Level Register 1 */
#define CD186x_PILR2 0x62 /* Priority Interrupt Level Register 2 */
#define CD186x_PILR3 0x63 /* Priority Interrupt Level Register 3 */
#define CD186x_CAR 0x64 /* Channel Access Register */
#define CD186x_SRSR 0x65 /* Channel Access Register */
#define CD186x_GFRCR 0x6b /* Global Firmware Revision Code Register */
#define CD186x_PPRH 0x70 /* Prescaler Period Register High */
#define CD186x_PPRL 0x71 /* Prescaler Period Register Low */
#define CD186x_RDR 0x78 /* Receiver Data Register */
#define CD186x_RCSR 0x7a /* Receiver Character Status Register */
#define CD186x_TDR 0x7b /* Transmit Data Register */
#define CD186x_EOIR 0x7f /* End of Interrupt Register */
#define CD186x_MRAR 0x75 /* Modem Request Acknowledge register */
#define CD186x_TRAR 0x76 /* Transmit Request Acknowledge register */
#define CD186x_RRAR 0x77 /* Receive Request Acknowledge register */
#define CD186x_SRCR 0x66 /* Service Request Configuration register */
/* Channel Registers */
#define CD186x_CCR 0x01 /* Channel Command Register */
#define CD186x_IER 0x02 /* Interrupt Enable Register */
#define CD186x_COR1 0x03 /* Channel Option Register 1 */
#define CD186x_COR2 0x04 /* Channel Option Register 2 */
#define CD186x_COR3 0x05 /* Channel Option Register 3 */
#define CD186x_CCSR 0x06 /* Channel Control Status Register */
#define CD186x_RDCR 0x07 /* Receive Data Count Register */
#define CD186x_SCHR1 0x09 /* Special Character Register 1 */
#define CD186x_SCHR2 0x0a /* Special Character Register 2 */
#define CD186x_SCHR3 0x0b /* Special Character Register 3 */
#define CD186x_SCHR4 0x0c /* Special Character Register 4 */
#define CD186x_MCOR1 0x10 /* Modem Change Option 1 Register */
#define CD186x_MCOR2 0x11 /* Modem Change Option 2 Register */
#define CD186x_MCR 0x12 /* Modem Change Register */
#define CD186x_RTPR 0x18 /* Receive Timeout Period Register */
#define CD186x_MSVR 0x28 /* Modem Signal Value Register */
#define CD186x_MSVRTS 0x29 /* Modem Signal Value Register */
#define CD186x_MSVDTR 0x2a /* Modem Signal Value Register */
#define CD186x_RBPRH 0x31 /* Receive Baud Rate Period Register High */
#define CD186x_RBPRL 0x32 /* Receive Baud Rate Period Register Low */
#define CD186x_TBPRH 0x39 /* Transmit Baud Rate Period Register High */
#define CD186x_TBPRL 0x3a /* Transmit Baud Rate Period Register Low */
/* Global Interrupt Vector Register (R/W) */
#define GIVR_ITMASK 0x07 /* Interrupt type mask */
#define GIVR_IT_MODEM 0x01 /* Modem Signal Change Interrupt */
#define GIVR_IT_TX 0x02 /* Transmit Data Interrupt */
#define GIVR_IT_RCV 0x03 /* Receive Good Data Interrupt */
#define GIVR_IT_REXC 0x07 /* Receive Exception Interrupt */
/* Global Interrupt Channel Register (R/W) */
#define GICR_CHAN 0x1c /* Channel Number Mask */
#define GICR_CHAN_OFF 2 /* Channel Number shift */
/* Channel Address Register (R/W) */
#define CAR_CHAN 0x07 /* Channel Number Mask */
#define CAR_A7 0x08 /* A7 Address Extension (unused) */
/* Receive Character Status Register (R/O) */
#define RCSR_TOUT 0x80 /* Rx Timeout */
#define RCSR_SCDET 0x70 /* Special Character Detected Mask */
#define RCSR_NO_SC 0x00 /* No Special Characters Detected */
#define RCSR_SC_1 0x10 /* Special Char 1 (or 1 & 3) Detected */
#define RCSR_SC_2 0x20 /* Special Char 2 (or 2 & 4) Detected */
#define RCSR_SC_3 0x30 /* Special Char 3 Detected */
#define RCSR_SC_4 0x40 /* Special Char 4 Detected */
#define RCSR_BREAK 0x08 /* Break has been detected */
#define RCSR_PE 0x04 /* Parity Error */
#define RCSR_FE 0x02 /* Frame Error */
#define RCSR_OE 0x01 /* Overrun Error */
/* Channel Command Register (R/W) (commands in groups can be OR-ed) */
#define CCR_HARDRESET 0x81 /* Reset the chip */
#define CCR_SOFTRESET 0x80 /* Soft Channel Reset */
#define CCR_CORCHG1 0x42 /* Channel Option Register 1 Changed */
#define CCR_CORCHG2 0x44 /* Channel Option Register 2 Changed */
#define CCR_CORCHG3 0x48 /* Channel Option Register 3 Changed */
#define CCR_SSCH1 0x21 /* Send Special Character 1 */
#define CCR_SSCH2 0x22 /* Send Special Character 2 */
#define CCR_SSCH3 0x23 /* Send Special Character 3 */
#define CCR_SSCH4 0x24 /* Send Special Character 4 */
#define CCR_TXEN 0x18 /* Enable Transmitter */
#define CCR_RXEN 0x12 /* Enable Receiver */
#define CCR_TXDIS 0x14 /* Disable Transmitter */
#define CCR_RXDIS 0x11 /* Disable Receiver */
/* Interrupt Enable Register (R/W) */
#define IER_DSR 0x80 /* Enable interrupt on DSR change */
#define IER_CD 0x40 /* Enable interrupt on CD change */
#define IER_CTS 0x20 /* Enable interrupt on CTS change */
#define IER_RXD 0x10 /* Enable interrupt on Receive Data */
#define IER_RXSC 0x08 /* Enable interrupt on Receive Spec. Char */
#define IER_TXRDY 0x04 /* Enable interrupt on TX FIFO empty */
#define IER_TXEMPTY 0x02 /* Enable interrupt on TX completely empty */
#define IER_RET 0x01 /* Enable interrupt on RX Exc. Timeout */
/* Channel Option Register 1 (R/W) */
#define COR1_ODDP 0x80 /* Odd Parity */
#define COR1_PARMODE 0x60 /* Parity Mode mask */
#define COR1_NOPAR 0x00 /* No Parity */
#define COR1_FORCEPAR 0x20 /* Force Parity */
#define COR1_NORMPAR 0x40 /* Normal Parity */
#define COR1_IGNORE 0x10 /* Ignore Parity on RX */
#define COR1_STOPBITS 0x0c /* Number of Stop Bits */
#define COR1_1SB 0x00 /* 1 Stop Bit */
#define COR1_15SB 0x04 /* 1.5 Stop Bits */
#define COR1_2SB 0x08 /* 2 Stop Bits */
#define COR1_CHARLEN 0x03 /* Character Length */
#define COR1_5BITS 0x00 /* 5 bits */
#define COR1_6BITS 0x01 /* 6 bits */
#define COR1_7BITS 0x02 /* 7 bits */
#define COR1_8BITS 0x03 /* 8 bits */
/* Channel Option Register 2 (R/W) */
#define COR2_IXM 0x80 /* Implied XON mode */
#define COR2_TXIBE 0x40 /* Enable In-Band (XON/XOFF) Flow Control */
#define COR2_ETC 0x20 /* Embedded Tx Commands Enable */
#define COR2_LLM 0x10 /* Local Loopback Mode */
#define COR2_RLM 0x08 /* Remote Loopback Mode */
#define COR2_RTSAO 0x04 /* RTS Automatic Output Enable */
#define COR2_CTSAE 0x02 /* CTS Automatic Enable */
#define COR2_DSRAE 0x01 /* DSR Automatic Enable */
/* Channel Option Register 3 (R/W) */
#define COR3_XONCH 0x80 /* XON is a pair of characters (1 & 3) */
#define COR3_XOFFCH 0x40 /* XOFF is a pair of characters (2 & 4) */
#define COR3_FCT 0x20 /* Flow-Control Transparency Mode */
#define COR3_SCDE 0x10 /* Special Character Detection Enable */
#define COR3_RXTH 0x0f /* RX FIFO Threshold value (1-8) */
/* Channel Control Status Register (R/O) */
#define CCSR_RXEN 0x80 /* Receiver Enabled */
#define CCSR_RXFLOFF 0x40 /* Receive Flow Off (XOFF was sent) */
#define CCSR_RXFLON 0x20 /* Receive Flow On (XON was sent) */
#define CCSR_TXEN 0x08 /* Transmitter Enabled */
#define CCSR_TXFLOFF 0x04 /* Transmit Flow Off (got XOFF) */
#define CCSR_TXFLON 0x02 /* Transmit Flow On (got XON) */
/* Modem Change Option Register 1 (R/W) */
#define MCOR1_DSRZD 0x80 /* Detect 0->1 transition of DSR */
#define MCOR1_CDZD 0x40 /* Detect 0->1 transition of CD */
#define MCOR1_CTSZD 0x20 /* Detect 0->1 transition of CTS */
#define MCOR1_DTRTH 0x0f /* Auto DTR flow control Threshold (1-8) */
#define MCOR1_NODTRFC 0x0 /* Automatic DTR flow control disabled */
/* Modem Change Option Register 2 (R/W) */
#define MCOR2_DSROD 0x80 /* Detect 1->0 transition of DSR */
#define MCOR2_CDOD 0x40 /* Detect 1->0 transition of CD */
#define MCOR2_CTSOD 0x20 /* Detect 1->0 transition of CTS */
/* Modem Change Register (R/W) */
#define MCR_DSRCHG 0x80 /* DSR Changed */
#define MCR_CDCHG 0x40 /* CD Changed */
#define MCR_CTSCHG 0x20 /* CTS Changed */
/* Modem Signal Value Register (R/W) */
#define MSVR_DSR 0x80 /* Current state of DSR input */
#define MSVR_CD 0x40 /* Current state of CD input */
#define MSVR_CTS 0x20 /* Current state of CTS input */
#define MSVR_DTR 0x02 /* Current state of DTR output */
#define MSVR_RTS 0x01 /* Current state of RTS output */
/* Escape characters */
#define CD186x_C_ESC 0x00 /* Escape character */
#define CD186x_C_SBRK 0x81 /* Start sending BREAK */
#define CD186x_C_DELAY 0x82 /* Delay output */
#define CD186x_C_EBRK 0x83 /* Stop sending BREAK */
#define SRSR_RREQint 0x10 /* This chip wants "rec" serviced */
#define SRSR_TREQint 0x04 /* This chip wants "transmit" serviced */
#define SRSR_MREQint 0x01 /* This chip wants "mdm change" serviced */
#define SRCR_PKGTYPE 0x80
#define SRCR_REGACKEN 0x40
#define SRCR_DAISYEN 0x20
#define SRCR_GLOBPRI 0x10
#define SRCR_UNFAIR 0x08
#define SRCR_AUTOPRI 0x02
#define SRCR_PRISEL 0x01

100
drivers/staging/tty/digi1.h
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@ -1,100 +0,0 @@
/* Definitions for DigiBoard ditty(1) command. */
#if !defined(TIOCMODG)
#define TIOCMODG (('d'<<8) | 250) /* get modem ctrl state */
#define TIOCMODS (('d'<<8) | 251) /* set modem ctrl state */
#endif
#if !defined(TIOCMSET)
#define TIOCMSET (('d'<<8) | 252) /* set modem ctrl state */
#define TIOCMGET (('d'<<8) | 253) /* set modem ctrl state */
#endif
#if !defined(TIOCMBIC)
#define TIOCMBIC (('d'<<8) | 254) /* set modem ctrl state */
#define TIOCMBIS (('d'<<8) | 255) /* set modem ctrl state */
#endif
#if !defined(TIOCSDTR)
#define TIOCSDTR (('e'<<8) | 0) /* set DTR */
#define TIOCCDTR (('e'<<8) | 1) /* clear DTR */
#endif
/************************************************************************
* Ioctl command arguments for DIGI parameters.
************************************************************************/
#define DIGI_GETA (('e'<<8) | 94) /* Read params */
#define DIGI_SETA (('e'<<8) | 95) /* Set params */
#define DIGI_SETAW (('e'<<8) | 96) /* Drain & set params */
#define DIGI_SETAF (('e'<<8) | 97) /* Drain, flush & set params */
#define DIGI_GETFLOW (('e'<<8) | 99) /* Get startc/stopc flow */
/* control characters */
#define DIGI_SETFLOW (('e'<<8) | 100) /* Set startc/stopc flow */
/* control characters */
#define DIGI_GETAFLOW (('e'<<8) | 101) /* Get Aux. startc/stopc */
/* flow control chars */
#define DIGI_SETAFLOW (('e'<<8) | 102) /* Set Aux. startc/stopc */
/* flow control chars */
#define DIGI_GETINFO (('e'<<8) | 103) /* Fill in digi_info */
#define DIGI_POLLER (('e'<<8) | 104) /* Turn on/off poller */
#define DIGI_INIT (('e'<<8) | 105) /* Allow things to run. */
struct digiflow_struct
{
unsigned char startc; /* flow cntl start char */
unsigned char stopc; /* flow cntl stop char */
};
typedef struct digiflow_struct digiflow_t;
/************************************************************************
* Values for digi_flags
************************************************************************/
#define DIGI_IXON 0x0001 /* Handle IXON in the FEP */
#define DIGI_FAST 0x0002 /* Fast baud rates */
#define RTSPACE 0x0004 /* RTS input flow control */
#define CTSPACE 0x0008 /* CTS output flow control */
#define DSRPACE 0x0010 /* DSR output flow control */
#define DCDPACE 0x0020 /* DCD output flow control */
#define DTRPACE 0x0040 /* DTR input flow control */
#define DIGI_FORCEDCD 0x0100 /* Force carrier */
#define DIGI_ALTPIN 0x0200 /* Alternate RJ-45 pin config */
#define DIGI_AIXON 0x0400 /* Aux flow control in fep */
/************************************************************************
* Values for digiDload
************************************************************************/
#define NORMAL 0
#define PCI_CTL 1
#define SIZE8 0
#define SIZE16 1
#define SIZE32 2
/************************************************************************
* Structure used with ioctl commands for DIGI parameters.
************************************************************************/
struct digi_struct
{
unsigned short digi_flags; /* Flags (see above) */
};
typedef struct digi_struct digi_t;
struct digi_info
{
unsigned long board; /* Which board is this ? */
unsigned char status; /* Alive or dead */
unsigned char type; /* see epca.h */
unsigned char subtype; /* For future XEM, XR, etc ... */
unsigned short numports; /* Number of ports configured */
unsigned char *port; /* I/O Address */
unsigned char *membase; /* DPR Address */
unsigned char *version; /* For future ... */
unsigned short windowData; /* For future ... */
} ;

136
drivers/staging/tty/digiFep1.h
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@ -1,136 +0,0 @@
#define CSTART 0x400L
#define CMAX 0x800L
#define ISTART 0x800L
#define IMAX 0xC00L
#define CIN 0xD10L
#define GLOBAL 0xD10L
#define EIN 0xD18L
#define FEPSTAT 0xD20L
#define CHANSTRUCT 0x1000L
#define RXTXBUF 0x4000L
struct global_data
{
u16 cin;
u16 cout;
u16 cstart;
u16 cmax;
u16 ein;
u16 eout;
u16 istart;
u16 imax;
};
struct board_chan
{
u32 filler1;
u32 filler2;
u16 tseg;
u16 tin;
u16 tout;
u16 tmax;
u16 rseg;
u16 rin;
u16 rout;
u16 rmax;
u16 tlow;
u16 rlow;
u16 rhigh;
u16 incr;
u16 etime;
u16 edelay;
unchar *dev;
u16 iflag;
u16 oflag;
u16 cflag;
u16 gmask;
u16 col;
u16 delay;
u16 imask;
u16 tflush;
u32 filler3;
u32 filler4;
u32 filler5;
u32 filler6;
u8 num;
u8 ract;
u8 bstat;
u8 tbusy;
u8 iempty;
u8 ilow;
u8 idata;
u8 eflag;
u8 tflag;
u8 rflag;
u8 xmask;
u8 xval;
u8 mstat;
u8 mchange;
u8 mint;
u8 lstat;
u8 mtran;
u8 orun;
u8 startca;
u8 stopca;
u8 startc;
u8 stopc;
u8 vnext;
u8 hflow;
u8 fillc;
u8 ochar;
u8 omask;
u8 filler7;
u8 filler8[28];
};
#define SRXLWATER 0xE0
#define SRXHWATER 0xE1
#define STOUT 0xE2
#define PAUSETX 0xE3
#define RESUMETX 0xE4
#define SAUXONOFFC 0xE6
#define SENDBREAK 0xE8
#define SETMODEM 0xE9
#define SETIFLAGS 0xEA
#define SONOFFC 0xEB
#define STXLWATER 0xEC
#define PAUSERX 0xEE
#define RESUMERX 0xEF
#define SETBUFFER 0xF2
#define SETCOOKED 0xF3
#define SETHFLOW 0xF4
#define SETCTRLFLAGS 0xF5
#define SETVNEXT 0xF6
#define BREAK_IND 0x01
#define LOWTX_IND 0x02
#define EMPTYTX_IND 0x04
#define DATA_IND 0x08
#define MODEMCHG_IND 0x20
#define FEP_HUPCL 0002000
#if 0
#define RTS 0x02
#define CD 0x08
#define DSR 0x10
#define CTS 0x20
#define RI 0x40
#define DTR 0x80
#endif

42
drivers/staging/tty/digiPCI.h
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@ -1,42 +0,0 @@
/*************************************************************************
* Defines and structure definitions for PCI BIOS Interface
*************************************************************************/
#define PCIMAX 32 /* maximum number of PCI boards */
#define PCI_VENDOR_DIGI 0x114F
#define PCI_DEVICE_EPC 0x0002
#define PCI_DEVICE_RIGHTSWITCH 0x0003 /* For testing */
#define PCI_DEVICE_XEM 0x0004
#define PCI_DEVICE_XR 0x0005
#define PCI_DEVICE_CX 0x0006
#define PCI_DEVICE_XRJ 0x0009 /* Jupiter boards with */
#define PCI_DEVICE_EPCJ 0x000a /* PLX 9060 chip for PCI */
/*
* On the PCI boards, there is no IO space allocated
* The I/O registers will be in the first 3 bytes of the
* upper 2MB of the 4MB memory space. The board memory
* will be mapped into the low 2MB of the 4MB memory space
*/
/* Potential location of PCI Bios from E0000 to FFFFF*/
#define PCI_BIOS_SIZE 0x00020000
/* Size of Memory and I/O for PCI (4MB) */
#define PCI_RAM_SIZE 0x00400000
/* Size of Memory (2MB) */
#define PCI_MEM_SIZE 0x00200000
/* Offset of I/0 in Memory (2MB) */
#define PCI_IO_OFFSET 0x00200000
#define MEMOUTB(basemem, pnum, setmemval) *(caddr_t)((basemem) + ( PCI_IO_OFFSET | pnum << 4 | pnum )) = (setmemval)
#define MEMINB(basemem, pnum) *(caddr_t)((basemem) + (PCI_IO_OFFSET | pnum << 4 | pnum )) /* for PCI I/O */

2784
drivers/staging/tty/epca.c
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File diff suppressed because it is too large Load diff

158
drivers/staging/tty/epca.h
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@ -1,158 +0,0 @@
#define XEMPORTS 0xC02
#define XEPORTS 0xC22
#define MAX_ALLOC 0x100
#define MAXBOARDS 12
#define FEPCODESEG 0x0200L
#define FEPCODE 0x2000L
#define BIOSCODE 0xf800L
#define MISCGLOBAL 0x0C00L
#define NPORT 0x0C22L
#define MBOX 0x0C40L
#define PORTBASE 0x0C90L
/* Begin code defines used for epca_setup */
#define INVALID_BOARD_TYPE 0x1
#define INVALID_NUM_PORTS 0x2
#define INVALID_MEM_BASE 0x4
#define INVALID_PORT_BASE 0x8
#define INVALID_BOARD_STATUS 0x10
#define INVALID_ALTPIN 0x20
/* End code defines used for epca_setup */
#define FEPCLR 0x00
#define FEPMEM 0x02
#define FEPRST 0x04
#define FEPINT 0x08
#define FEPMASK 0x0e
#define FEPWIN 0x80
#define PCXE 0
#define PCXEVE 1
#define PCXEM 2
#define EISAXEM 3
#define PC64XE 4
#define PCXI 5
#define PCIXEM 7
#define PCICX 8
#define PCIXR 9
#define PCIXRJ 10
#define EPCA_NUM_TYPES 6
static char *board_desc[] =
{
"PC/Xe",
"PC/Xeve",
"PC/Xem",
"EISA/Xem",
"PC/64Xe",
"PC/Xi",
"unknown",
"PCI/Xem",
"PCI/CX",
"PCI/Xr",
"PCI/Xrj",
};
#define STARTC 021
#define STOPC 023
#define IAIXON 0x2000
#define TXSTOPPED 0x1
#define LOWWAIT 0x2
#define EMPTYWAIT 0x4
#define RXSTOPPED 0x8
#define TXBUSY 0x10
#define DISABLED 0
#define ENABLED 1
#define OFF 0
#define ON 1
#define FEPTIMEOUT 200000
#define SERIAL_TYPE_INFO 3
#define EPCA_EVENT_HANGUP 1
#define EPCA_MAGIC 0x5c6df104L
struct channel
{
long magic;
struct tty_port port;
unsigned char boardnum;
unsigned char channelnum;
unsigned char omodem; /* FEP output modem status */
unsigned char imodem; /* FEP input modem status */
unsigned char modemfake; /* Modem values to be forced */
unsigned char modem; /* Force values */
unsigned char hflow;
unsigned char dsr;
unsigned char dcd;
unsigned char m_rts ; /* The bits used in whatever FEP */
unsigned char m_dcd ; /* is indiginous to this board to */
unsigned char m_dsr ; /* represent each of the physical */
unsigned char m_cts ; /* handshake lines */
unsigned char m_ri ;
unsigned char m_dtr ;
unsigned char stopc;
unsigned char startc;
unsigned char stopca;
unsigned char startca;
unsigned char fepstopc;
unsigned char fepstartc;
unsigned char fepstopca;
unsigned char fepstartca;
unsigned char txwin;
unsigned char rxwin;
unsigned short fepiflag;
unsigned short fepcflag;
unsigned short fepoflag;
unsigned short txbufhead;
unsigned short txbufsize;
unsigned short rxbufhead;
unsigned short rxbufsize;
int close_delay;
unsigned long event;
uint dev;
unsigned long statusflags;
unsigned long c_iflag;
unsigned long c_cflag;
unsigned long c_lflag;
unsigned long c_oflag;
unsigned char __iomem *txptr;
unsigned char __iomem *rxptr;
struct board_info *board;
struct board_chan __iomem *brdchan;
struct digi_struct digiext;
struct work_struct tqueue;
struct global_data __iomem *mailbox;
};
struct board_info
{
unsigned char status;
unsigned char type;
unsigned char altpin;
unsigned short numports;
unsigned long port;
unsigned long membase;
void __iomem *re_map_port;
void __iomem *re_map_membase;
unsigned long memory_seg;
void ( * memwinon ) (struct board_info *, unsigned int) ;
void ( * memwinoff ) (struct board_info *, unsigned int) ;
void ( * globalwinon ) (struct channel *) ;
void ( * txwinon ) (struct channel *) ;
void ( * rxwinon ) (struct channel *) ;
void ( * memoff ) (struct channel *) ;
void ( * assertgwinon ) (struct channel *) ;
void ( * assertmemoff ) (struct channel *) ;
unsigned char poller_inhibited ;
};

7
drivers/staging/tty/epcaconfig.h
View file

@ -1,7 +0,0 @@
#define NUMCARDS 0
#define NBDEVS 0
struct board_info static_boards[NUMCARDS]={
};
/* DO NOT HAND EDIT THIS FILE! */

8
drivers/staging/tty/ip2/Makefile
View file

@ -1,8 +0,0 @@
#
# Makefile for the Computone IntelliPort Plus Driver
#
obj-$(CONFIG_COMPUTONE) += ip2.o
ip2-y := ip2main.o

210
drivers/staging/tty/ip2/i2cmd.c
View file

@ -1,210 +0,0 @@
/*******************************************************************************
*
* (c) 1998 by Computone Corporation
*
********************************************************************************
*
*
* PACKAGE: Linux tty Device Driver for IntelliPort family of multiport
* serial I/O controllers.
*
* DESCRIPTION: Definition table for In-line and Bypass commands. Applicable
* only when the standard loadware is active. (This is included
* source code, not a separate compilation module.)
*
*******************************************************************************/
//------------------------------------------------------------------------------
//
// Revision History:
//
// 10 October 1991 MAG First Draft
// 7 November 1991 MAG Reflects additional commands.
// 24 February 1992 MAG Additional commands for 1.4.x loadware
// 11 March 1992 MAG Additional commands
// 30 March 1992 MAG Additional command: CMD_DSS_NOW
// 18 May 1992 MAG Discovered commands 39 & 40 must be at the end of a
// packet: affects implementation.
//------------------------------------------------------------------------------
//************
//* Includes *
//************
#include "i2cmd.h" /* To get some bit-defines */
//------------------------------------------------------------------------------
// Here is the table of global arrays which represent each type of command
// supported in the IntelliPort standard loadware. See also i2cmd.h
// for a more complete explanation of what is going on.
//------------------------------------------------------------------------------
// Here are the various globals: note that the names are not used except through
// the macros defined in i2cmd.h. Also note that although they are character
// arrays here (for extendability) they are cast to structure pointers in the
// i2cmd.h macros. See i2cmd.h for flags definitions.
// Length Flags Command
static UCHAR ct02[] = { 1, BTH, 0x02 }; // DTR UP
static UCHAR ct03[] = { 1, BTH, 0x03 }; // DTR DN
static UCHAR ct04[] = { 1, BTH, 0x04 }; // RTS UP
static UCHAR ct05[] = { 1, BTH, 0x05 }; // RTS DN
static UCHAR ct06[] = { 1, BYP, 0x06 }; // START FL
static UCHAR ct07[] = { 2, BTH, 0x07,0 }; // BAUD
static UCHAR ct08[] = { 2, BTH, 0x08,0 }; // BITS
static UCHAR ct09[] = { 2, BTH, 0x09,0 }; // STOP
static UCHAR ct10[] = { 2, BTH, 0x0A,0 }; // PARITY
static UCHAR ct11[] = { 2, BTH, 0x0B,0 }; // XON
static UCHAR ct12[] = { 2, BTH, 0x0C,0 }; // XOFF
static UCHAR ct13[] = { 1, BTH, 0x0D }; // STOP FL
static UCHAR ct14[] = { 1, BYP|VIP, 0x0E }; // ACK HOTK
//static UCHAR ct15[]={ 2, BTH|VIP, 0x0F,0 }; // IRQ SET
static UCHAR ct16[] = { 2, INL, 0x10,0 }; // IXONOPTS
static UCHAR ct17[] = { 2, INL, 0x11,0 }; // OXONOPTS
static UCHAR ct18[] = { 1, INL, 0x12 }; // CTSENAB
static UCHAR ct19[] = { 1, BTH, 0x13 }; // CTSDSAB
static UCHAR ct20[] = { 1, INL, 0x14 }; // DCDENAB
static UCHAR ct21[] = { 1, BTH, 0x15 }; // DCDDSAB
static UCHAR ct22[] = { 1, BTH, 0x16 }; // DSRENAB
static UCHAR ct23[] = { 1, BTH, 0x17 }; // DSRDSAB
static UCHAR ct24[] = { 1, BTH, 0x18 }; // RIENAB
static UCHAR ct25[] = { 1, BTH, 0x19 }; // RIDSAB
static UCHAR ct26[] = { 2, BTH, 0x1A,0 }; // BRKENAB
static UCHAR ct27[] = { 1, BTH, 0x1B }; // BRKDSAB
//static UCHAR ct28[]={ 2, BTH, 0x1C,0 }; // MAXBLOKSIZE
//static UCHAR ct29[]={ 2, 0, 0x1D,0 }; // reserved
static UCHAR ct30[] = { 1, INL, 0x1E }; // CTSFLOWENAB
static UCHAR ct31[] = { 1, INL, 0x1F }; // CTSFLOWDSAB
static UCHAR ct32[] = { 1, INL, 0x20 }; // RTSFLOWENAB
static UCHAR ct33[] = { 1, INL, 0x21 }; // RTSFLOWDSAB
static UCHAR ct34[] = { 2, BTH, 0x22,0 }; // ISTRIPMODE
static UCHAR ct35[] = { 2, BTH|END, 0x23,0 }; // SENDBREAK
static UCHAR ct36[] = { 2, BTH, 0x24,0 }; // SETERRMODE
//static UCHAR ct36a[]={ 3, INL, 0x24,0,0 }; // SET_REPLACE
// The following is listed for completeness, but should never be sent directly
// by user-level code. It is sent only by library routines in response to data
// movement.
//static UCHAR ct37[]={ 5, BYP|VIP, 0x25,0,0,0,0 }; // FLOW PACKET
// Back to normal
//static UCHAR ct38[] = {11, BTH|VAR, 0x26,0,0,0,0,0,0,0,0,0,0 }; // DEF KEY SEQ
//static UCHAR ct39[]={ 3, BTH|END, 0x27,0,0 }; // OPOSTON
//static UCHAR ct40[]={ 1, BTH|END, 0x28 }; // OPOSTOFF
static UCHAR ct41[] = { 1, BYP, 0x29 }; // RESUME
//static UCHAR ct42[]={ 2, BTH, 0x2A,0 }; // TXBAUD
//static UCHAR ct43[]={ 2, BTH, 0x2B,0 }; // RXBAUD
//static UCHAR ct44[]={ 2, BTH, 0x2C,0 }; // MS PING
//static UCHAR ct45[]={ 1, BTH, 0x2D }; // HOTENAB
//static UCHAR ct46[]={ 1, BTH, 0x2E }; // HOTDSAB
//static UCHAR ct47[]={ 7, BTH, 0x2F,0,0,0,0,0,0 }; // UNIX FLAGS
//static UCHAR ct48[]={ 1, BTH, 0x30 }; // DSRFLOWENAB
//static UCHAR ct49[]={ 1, BTH, 0x31 }; // DSRFLOWDSAB
//static UCHAR ct50[]={ 1, BTH, 0x32 }; // DTRFLOWENAB
//static UCHAR ct51[]={ 1, BTH, 0x33 }; // DTRFLOWDSAB
//static UCHAR ct52[]={ 1, BTH, 0x34 }; // BAUDTABRESET
//static UCHAR ct53[] = { 3, BTH, 0x35,0,0 }; // BAUDREMAP
static UCHAR ct54[] = { 3, BTH, 0x36,0,0 }; // CUSTOMBAUD1
static UCHAR ct55[] = { 3, BTH, 0x37,0,0 }; // CUSTOMBAUD2
static UCHAR ct56[] = { 2, BTH|END, 0x38,0 }; // PAUSE
static UCHAR ct57[] = { 1, BYP, 0x39 }; // SUSPEND
static UCHAR ct58[] = { 1, BYP, 0x3A }; // UNSUSPEND
static UCHAR ct59[] = { 2, BTH, 0x3B,0 }; // PARITYCHK
static UCHAR ct60[] = { 1, INL|VIP, 0x3C }; // BOOKMARKREQ
//static UCHAR ct61[]={ 2, BTH, 0x3D,0 }; // INTERNALLOOP
//static UCHAR ct62[]={ 2, BTH, 0x3E,0 }; // HOTKTIMEOUT
static UCHAR ct63[] = { 2, INL, 0x3F,0 }; // SETTXON
static UCHAR ct64[] = { 2, INL, 0x40,0 }; // SETTXOFF
//static UCHAR ct65[]={ 2, BTH, 0x41,0 }; // SETAUTORTS
//static UCHAR ct66[]={ 2, BTH, 0x42,0 }; // SETHIGHWAT
//static UCHAR ct67[]={ 2, BYP, 0x43,0 }; // STARTSELFL
//static UCHAR ct68[]={ 2, INL, 0x44,0 }; // ENDSELFL
//static UCHAR ct69[]={ 1, BYP, 0x45 }; // HWFLOW_OFF
//static UCHAR ct70[]={ 1, BTH, 0x46 }; // ODSRFL_ENAB
//static UCHAR ct71[]={ 1, BTH, 0x47 }; // ODSRFL_DSAB
//static UCHAR ct72[]={ 1, BTH, 0x48 }; // ODCDFL_ENAB
//static UCHAR ct73[]={ 1, BTH, 0x49 }; // ODCDFL_DSAB
//static UCHAR ct74[]={ 2, BTH, 0x4A,0 }; // LOADLEVEL
//static UCHAR ct75[]={ 2, BTH, 0x4B,0 }; // STATDATA
//static UCHAR ct76[]={ 1, BYP, 0x4C }; // BREAK_ON
//static UCHAR ct77[]={ 1, BYP, 0x4D }; // BREAK_OFF
//static UCHAR ct78[]={ 1, BYP, 0x4E }; // GETFC
static UCHAR ct79[] = { 2, BYP, 0x4F,0 }; // XMIT_NOW
//static UCHAR ct80[]={ 4, BTH, 0x50,0,0,0 }; // DIVISOR_LATCH
//static UCHAR ct81[]={ 1, BYP, 0x51 }; // GET_STATUS
//static UCHAR ct82[]={ 1, BYP, 0x52 }; // GET_TXCNT
//static UCHAR ct83[]={ 1, BYP, 0x53 }; // GET_RXCNT
//static UCHAR ct84[]={ 1, BYP, 0x54 }; // GET_BOXIDS
//static UCHAR ct85[]={10, BYP, 0x55,0,0,0,0,0,0,0,0,0 }; // ENAB_MULT
//static UCHAR ct86[]={ 2, BTH, 0x56,0 }; // RCV_ENABLE
static UCHAR ct87[] = { 1, BYP, 0x57 }; // HW_TEST
//static UCHAR ct88[]={ 3, BTH, 0x58,0,0 }; // RCV_THRESHOLD
//static UCHAR ct90[]={ 3, BYP, 0x5A,0,0 }; // Set SILO
//static UCHAR ct91[]={ 2, BYP, 0x5B,0 }; // timed break
// Some composite commands as well
//static UCHAR cc01[]={ 2, BTH, 0x02,0x04 }; // DTR & RTS UP
//static UCHAR cc02[]={ 2, BTH, 0x03,0x05 }; // DTR & RTS DN
//********
//* Code *
//********
//******************************************************************************
// Function: i2cmdUnixFlags(iflag, cflag, lflag)
// Parameters: Unix tty flags
//
// Returns: Pointer to command structure
//
// Description:
//
// This routine sets the parameters of command 47 and returns a pointer to the
// appropriate structure.
//******************************************************************************
#if 0
cmdSyntaxPtr
i2cmdUnixFlags(unsigned short iflag,unsigned short cflag,unsigned short lflag)
{
cmdSyntaxPtr pCM = (cmdSyntaxPtr) ct47;
pCM->cmd[1] = (unsigned char) iflag;
pCM->cmd[2] = (unsigned char) (iflag >> 8);
pCM->cmd[3] = (unsigned char) cflag;
pCM->cmd[4] = (unsigned char) (cflag >> 8);
pCM->cmd[5] = (unsigned char) lflag;
pCM->cmd[6] = (unsigned char) (lflag >> 8);
return pCM;
}
#endif /* 0 */
//******************************************************************************
// Function: i2cmdBaudDef(which, rate)
// Parameters: ?
//
// Returns: Pointer to command structure
//
// Description:
//
// This routine sets the parameters of commands 54 or 55 (according to the
// argument which), and returns a pointer to the appropriate structure.
//******************************************************************************
static cmdSyntaxPtr
i2cmdBaudDef(int which, unsigned short rate)
{
cmdSyntaxPtr pCM;
switch(which)
{
case 1:
pCM = (cmdSyntaxPtr) ct54;
break;
default:
case 2:
pCM = (cmdSyntaxPtr) ct55;
break;
}
pCM->cmd[1] = (unsigned char) rate;
pCM->cmd[2] = (unsigned char) (rate >> 8);
return pCM;
}

630
drivers/staging/tty/ip2/i2cmd.h
View file

@ -1,630 +0,0 @@
/*******************************************************************************
*
* (c) 1999 by Computone Corporation
*
********************************************************************************
*
*
* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
* serial I/O controllers.
*
* DESCRIPTION: Definitions and support for In-line and Bypass commands.
* Applicable only when the standard loadware is active.
*
*******************************************************************************/
//------------------------------------------------------------------------------
// Revision History:
//
// 10 October 1991 MAG First Draft
// 7 November 1991 MAG Reflects some new commands
// 20 February 1992 MAG CMD_HOTACK corrected: no argument.
// 24 February 1992 MAG Support added for new commands for 1.4.x loadware.
// 11 March 1992 MAG Additional commands.
// 16 March 1992 MAG Additional commands.
// 30 March 1992 MAG Additional command: CMD_DSS_NOW
// 18 May 1992 MAG Changed CMD_OPOST
//
//------------------------------------------------------------------------------
#ifndef I2CMD_H // To prevent multiple includes
#define I2CMD_H 1
#include "ip2types.h"
// This module is designed to provide a uniform method of sending commands to
// the board through command packets. The difficulty is, some commands take
// parameters, others do not. Furthermore, it is often useful to send several
// commands to the same channel as part of the same packet. (See also i2pack.h.)
//
// This module is designed so that the caller should not be responsible for
// remembering the exact syntax of each command, or at least so that the
// compiler could check things somewhat. I'll explain as we go...
//
// First, a structure which can embody the syntax of each type of command.
//
typedef struct _cmdSyntax
{
UCHAR length; // Number of bytes in the command
UCHAR flags; // Information about the command (see below)
// The command and its parameters, which may be of arbitrary length. Don't
// worry yet how the parameters will be initialized; macros later take care
// of it. Also, don't worry about the arbitrary length issue; this structure
// is never used to allocate space (see i2cmd.c).
UCHAR cmd[2];
} cmdSyntax, *cmdSyntaxPtr;
// Bit assignments for flags
#define INL 1 // Set if suitable for inline commands
#define BYP 2 // Set if suitable for bypass commands
#define BTH (INL|BYP) // suitable for either!
#define END 4 // Set if this must be the last command in a block
#define VIP 8 // Set if this command is special in some way and really
// should only be sent from the library-level and not
// directly from user-level
#define VAR 0x10 // This command is of variable length!
// Declarations for the global arrays used to bear the commands and their
// arguments.
//
// Note: Since these are globals and the arguments might change, it is important
// that the library routine COPY these into buffers from whence they would be
// sent, rather than merely storing the pointers. In multi-threaded
// environments, important that the copy should obtain before any context switch
// is allowed. Also, for parameterized commands, DO NOT ISSUE THE SAME COMMAND
// MORE THAN ONCE WITH THE SAME PARAMETERS in the same call.
//
static UCHAR ct02[];
static UCHAR ct03[];
static UCHAR ct04[];
static UCHAR ct05[];
static UCHAR ct06[];
static UCHAR ct07[];
static UCHAR ct08[];
static UCHAR ct09[];
static UCHAR ct10[];
static UCHAR ct11[];
static UCHAR ct12[];
static UCHAR ct13[];
static UCHAR ct14[];
static UCHAR ct15[];
static UCHAR ct16[];
static UCHAR ct17[];
static UCHAR ct18[];
static UCHAR ct19[];
static UCHAR ct20[];
static UCHAR ct21[];
static UCHAR ct22[];
static UCHAR ct23[];
static UCHAR ct24[];
static UCHAR ct25[];
static UCHAR ct26[];
static UCHAR ct27[];
static UCHAR ct28[];
static UCHAR ct29[];
static UCHAR ct30[];
static UCHAR ct31[];
static UCHAR ct32[];
static UCHAR ct33[];
static UCHAR ct34[];
static UCHAR ct35[];
static UCHAR ct36[];
static UCHAR ct36a[];
static UCHAR ct41[];
static UCHAR ct42[];
static UCHAR ct43[];
static UCHAR ct44[];
static UCHAR ct45[];
static UCHAR ct46[];
static UCHAR ct48[];
static UCHAR ct49[];
static UCHAR ct50[];
static UCHAR ct51[];
static UCHAR ct52[];
static UCHAR ct56[];
static UCHAR ct57[];
static UCHAR ct58[];
static UCHAR ct59[];
static UCHAR ct60[];
static UCHAR ct61[];
static UCHAR ct62[];
static UCHAR ct63[];
static UCHAR ct64[];
static UCHAR ct65[];
static UCHAR ct66[];
static UCHAR ct67[];
static UCHAR ct68[];
static UCHAR ct69[];
static UCHAR ct70[];
static UCHAR ct71[];
static UCHAR ct72[];
static UCHAR ct73[];
static UCHAR ct74[];
static UCHAR ct75[];
static UCHAR ct76[];
static UCHAR ct77[];
static UCHAR ct78[];
static UCHAR ct79[];
static UCHAR ct80[];
static UCHAR ct81[];
static UCHAR ct82[];
static UCHAR ct83[];
static UCHAR ct84[];
static UCHAR ct85[];
static UCHAR ct86[];
static UCHAR ct87[];
static UCHAR ct88[];
static UCHAR ct89[];
static UCHAR ct90[];
static UCHAR ct91[];
static UCHAR cc01[];
static UCHAR cc02[];
// Now, refer to i2cmd.c, and see the character arrays defined there. They are
// cast here to cmdSyntaxPtr.
//
// There are library functions for issuing bypass or inline commands. These
// functions take one or more arguments of the type cmdSyntaxPtr. The routine
// then can figure out how long each command is supposed to be and easily add it
// to the list.
//
// For ease of use, we define manifests which return pointers to appropriate
// cmdSyntaxPtr things. But some commands also take arguments. If a single
// argument is used, we define a macro which performs the single assignment and
// (through the expedient of a comma expression) references the appropriate
// pointer. For commands requiring several arguments, we actually define a
// function to perform the assignments.
#define CMD_DTRUP (cmdSyntaxPtr)(ct02) // Raise DTR
#define CMD_DTRDN (cmdSyntaxPtr)(ct03) // Lower DTR
#define CMD_RTSUP (cmdSyntaxPtr)(ct04) // Raise RTS
#define CMD_RTSDN (cmdSyntaxPtr)(ct05) // Lower RTS
#define CMD_STARTFL (cmdSyntaxPtr)(ct06) // Start Flushing Data
#define CMD_DTRRTS_UP (cmdSyntaxPtr)(cc01) // Raise DTR and RTS
#define CMD_DTRRTS_DN (cmdSyntaxPtr)(cc02) // Lower DTR and RTS
// Set Baud Rate for transmit and receive
#define CMD_SETBAUD(arg) \
(((cmdSyntaxPtr)(ct07))->cmd[1] = (arg),(cmdSyntaxPtr)(ct07))
#define CBR_50 1
#define CBR_75 2
#define CBR_110 3
#define CBR_134 4
#define CBR_150 5
#define CBR_200 6
#define CBR_300 7
#define CBR_600 8
#define CBR_1200 9
#define CBR_1800 10
#define CBR_2400 11
#define CBR_4800 12
#define CBR_9600 13
#define CBR_19200 14
#define CBR_38400 15
#define CBR_2000 16
#define CBR_3600 17
#define CBR_7200 18
#define CBR_56000 19
#define CBR_57600 20
#define CBR_64000 21
#define CBR_76800 22
#define CBR_115200 23
#define CBR_C1 24 // Custom baud rate 1
#define CBR_C2 25 // Custom baud rate 2
#define CBR_153600 26
#define CBR_230400 27
#define CBR_307200 28
#define CBR_460800 29
#define CBR_921600 30
// Set Character size
//
#define CMD_SETBITS(arg) \
(((cmdSyntaxPtr)(ct08))->cmd[1] = (arg),(cmdSyntaxPtr)(ct08))
#define CSZ_5 0
#define CSZ_6 1
#define CSZ_7 2
#define CSZ_8 3
// Set number of stop bits
//
#define CMD_SETSTOP(arg) \
(((cmdSyntaxPtr)(ct09))->cmd[1] = (arg),(cmdSyntaxPtr)(ct09))
#define CST_1 0
#define CST_15 1 // 1.5 stop bits
#define CST_2 2
// Set parity option
//
#define CMD_SETPAR(arg) \
(((cmdSyntaxPtr)(ct10))->cmd[1] = (arg),(cmdSyntaxPtr)(ct10))
#define CSP_NP 0 // no parity
#define CSP_OD 1 // odd parity
#define CSP_EV 2 // Even parity
#define CSP_SP 3 // Space parity
#define CSP_MK 4 // Mark parity
// Define xon char for transmitter flow control
//
#define CMD_DEF_IXON(arg) \
(((cmdSyntaxPtr)(ct11))->cmd[1] = (arg),(cmdSyntaxPtr)(ct11))
// Define xoff char for transmitter flow control
//
#define CMD_DEF_IXOFF(arg) \
(((cmdSyntaxPtr)(ct12))->cmd[1] = (arg),(cmdSyntaxPtr)(ct12))
#define CMD_STOPFL (cmdSyntaxPtr)(ct13) // Stop Flushing data
// Acknowledge receipt of hotkey signal
//
#define CMD_HOTACK (cmdSyntaxPtr)(ct14)
// Define irq level to use. Should actually be sent by library-level code, not
// directly from user...
//
#define CMDVALUE_IRQ 15 // For library use at initialization. Until this command
// is sent, board processing doesn't really start.
#define CMD_SET_IRQ(arg) \
(((cmdSyntaxPtr)(ct15))->cmd[1] = (arg),(cmdSyntaxPtr)(ct15))
#define CIR_POLL 0 // No IRQ - Poll
#define CIR_3 3 // IRQ 3
#define CIR_4 4 // IRQ 4
#define CIR_5 5 // IRQ 5
#define CIR_7 7 // IRQ 7
#define CIR_10 10 // IRQ 10
#define CIR_11 11 // IRQ 11
#define CIR_12 12 // IRQ 12
#define CIR_15 15 // IRQ 15
// Select transmit flow xon/xoff options
//
#define CMD_IXON_OPT(arg) \
(((cmdSyntaxPtr)(ct16))->cmd[1] = (arg),(cmdSyntaxPtr)(ct16))
#define CIX_NONE 0 // Incoming Xon/Xoff characters not special
#define CIX_XON 1 // Xoff disable, Xon enable
#define CIX_XANY 2 // Xoff disable, any key enable
// Select receive flow xon/xoff options
//
#define CMD_OXON_OPT(arg) \
(((cmdSyntaxPtr)(ct17))->cmd[1] = (arg),(cmdSyntaxPtr)(ct17))
#define COX_NONE 0 // Don't send Xon/Xoff
#define COX_XON 1 // Send xon/xoff to start/stop incoming data
#define CMD_CTS_REP (cmdSyntaxPtr)(ct18) // Enable CTS reporting
#define CMD_CTS_NREP (cmdSyntaxPtr)(ct19) // Disable CTS reporting
#define CMD_DCD_REP (cmdSyntaxPtr)(ct20) // Enable DCD reporting
#define CMD_DCD_NREP (cmdSyntaxPtr)(ct21) // Disable DCD reporting
#define CMD_DSR_REP (cmdSyntaxPtr)(ct22) // Enable DSR reporting
#define CMD_DSR_NREP (cmdSyntaxPtr)(ct23) // Disable DSR reporting
#define CMD_RI_REP (cmdSyntaxPtr)(ct24) // Enable RI reporting
#define CMD_RI_NREP (cmdSyntaxPtr)(ct25) // Disable RI reporting
// Enable break reporting and select style
//
#define CMD_BRK_REP(arg) \
(((cmdSyntaxPtr)(ct26))->cmd[1] = (arg),(cmdSyntaxPtr)(ct26))
#define CBK_STAT 0x00 // Report breaks as a status (exception,irq)
#define CBK_NULL 0x01 // Report breaks as a good null
#define CBK_STAT_SEQ 0x02 // Report breaks as a status AND as in-band character
// sequence FFh, 01h, 10h
#define CBK_SEQ 0x03 // Report breaks as the in-band
//sequence FFh, 01h, 10h ONLY.
#define CBK_FLSH 0x04 // if this bit set also flush input data
#define CBK_POSIX 0x08 // if this bit set report as FF,0,0 sequence
#define CBK_SINGLE 0x10 // if this bit set with CBK_SEQ or CBK_STAT_SEQ
//then reports single null instead of triple
#define CMD_BRK_NREP (cmdSyntaxPtr)(ct27) // Disable break reporting
// Specify maximum block size for received data
//
#define CMD_MAX_BLOCK(arg) \
(((cmdSyntaxPtr)(ct28))->cmd[1] = (arg),(cmdSyntaxPtr)(ct28))
// -- COMMAND 29 is reserved --
#define CMD_CTSFL_ENAB (cmdSyntaxPtr)(ct30) // Enable CTS flow control
#define CMD_CTSFL_DSAB (cmdSyntaxPtr)(ct31) // Disable CTS flow control
#define CMD_RTSFL_ENAB (cmdSyntaxPtr)(ct32) // Enable RTS flow control
#define CMD_RTSFL_DSAB (cmdSyntaxPtr)(ct33) // Disable RTS flow control
// Specify istrip option
//
#define CMD_ISTRIP_OPT(arg) \
(((cmdSyntaxPtr)(ct34))->cmd[1] = (arg),(cmdSyntaxPtr)(ct34))
#define CIS_NOSTRIP 0 // Strip characters to character size
#define CIS_STRIP 1 // Strip any 8-bit characters to 7 bits
// Send a break of arg milliseconds
//
#define CMD_SEND_BRK(arg) \
(((cmdSyntaxPtr)(ct35))->cmd[1] = (arg),(cmdSyntaxPtr)(ct35))
// Set error reporting mode
//
#define CMD_SET_ERROR(arg) \
(((cmdSyntaxPtr)(ct36))->cmd[1] = (arg),(cmdSyntaxPtr)(ct36))
#define CSE_ESTAT 0 // Report error in a status packet
#define CSE_NOREP 1 // Treat character as though it were good
#define CSE_DROP 2 // Discard the character
#define CSE_NULL 3 // Replace with a null
#define CSE_MARK 4 // Replace with a 3-character sequence (as Unix)
#define CSE_REPLACE 0x8 // Replace the errored character with the
// replacement character defined here
#define CSE_STAT_REPLACE 0x18 // Replace the errored character with the
// replacement character defined here AND
// report the error as a status packet (as in
// CSE_ESTAT).
// COMMAND 37, to send flow control packets, is handled only by low-level
// library code in response to data movement and shouldn't ever be sent by the
// user code. See i2pack.h and the body of i2lib.c for details.
// Enable on-board post-processing, using options given in oflag argument.
// Formerly, this command was automatically preceded by a CMD_OPOST_OFF command
// because the loadware does not permit sending back-to-back CMD_OPOST_ON
// commands without an intervening CMD_OPOST_OFF. BUT, WE LEARN 18 MAY 92, that
// CMD_OPOST_ON and CMD_OPOST_OFF must each be at the end of a packet (or in a
// solo packet). This means the caller must specify separately CMD_OPOST_OFF,
// CMD_OPOST_ON(parm) when he calls i2QueueCommands(). That function will ensure
// each gets a separate packet. Extra CMD_OPOST_OFF's are always ok.
//
#define CMD_OPOST_ON(oflag) \
(*(USHORT *)(((cmdSyntaxPtr)(ct39))->cmd[1]) = (oflag), \
(cmdSyntaxPtr)(ct39))
#define CMD_OPOST_OFF (cmdSyntaxPtr)(ct40) // Disable on-board post-proc
#define CMD_RESUME (cmdSyntaxPtr)(ct41) // Resume: behave as though an XON
// were received;
// Set Transmit baud rate (see command 7 for arguments)
//
#define CMD_SETBAUD_TX(arg) \
(((cmdSyntaxPtr)(ct42))->cmd[1] = (arg),(cmdSyntaxPtr)(ct42))
// Set Receive baud rate (see command 7 for arguments)
//
#define CMD_SETBAUD_RX(arg) \
(((cmdSyntaxPtr)(ct43))->cmd[1] = (arg),(cmdSyntaxPtr)(ct43))
// Request interrupt from board each arg milliseconds. Interrupt will specify
// "received data", even though there may be no data present. If arg == 0,
// disables any such interrupts.
//
#define CMD_PING_REQ(arg) \
(((cmdSyntaxPtr)(ct44))->cmd[1] = (arg),(cmdSyntaxPtr)(ct44))
#define CMD_HOT_ENAB (cmdSyntaxPtr)(ct45) // Enable Hot-key checking
#define CMD_HOT_DSAB (cmdSyntaxPtr)(ct46) // Disable Hot-key checking
#if 0
// COMMAND 47: Send Protocol info via Unix flags:
// iflag = Unix tty t_iflag
// cflag = Unix tty t_cflag
// lflag = Unix tty t_lflag
// See System V Unix/Xenix documentation for the meanings of the bit fields
// within these flags
//
#define CMD_UNIX_FLAGS(iflag,cflag,lflag) i2cmdUnixFlags(iflag,cflag,lflag)
#endif /* 0 */
#define CMD_DSRFL_ENAB (cmdSyntaxPtr)(ct48) // Enable DSR receiver ctrl
#define CMD_DSRFL_DSAB (cmdSyntaxPtr)(ct49) // Disable DSR receiver ctrl
#define CMD_DTRFL_ENAB (cmdSyntaxPtr)(ct50) // Enable DTR flow control
#define CMD_DTRFL_DSAB (cmdSyntaxPtr)(ct51) // Disable DTR flow control
#define CMD_BAUD_RESET (cmdSyntaxPtr)(ct52) // Reset baudrate table
// COMMAND 54: Define custom rate #1
// rate = (short) 1/10 of the desired baud rate
//
#define CMD_BAUD_DEF1(rate) i2cmdBaudDef(1,rate)
// COMMAND 55: Define custom rate #2
// rate = (short) 1/10 of the desired baud rate
//
#define CMD_BAUD_DEF2(rate) i2cmdBaudDef(2,rate)
// Pause arg hundredths of seconds. (Note, this is NOT milliseconds.)
//
#define CMD_PAUSE(arg) \
(((cmdSyntaxPtr)(ct56))->cmd[1] = (arg),(cmdSyntaxPtr)(ct56))
#define CMD_SUSPEND (cmdSyntaxPtr)(ct57) // Suspend output
#define CMD_UNSUSPEND (cmdSyntaxPtr)(ct58) // Un-Suspend output
// Set parity-checking options
//
#define CMD_PARCHK(arg) \
(((cmdSyntaxPtr)(ct59))->cmd[1] = (arg),(cmdSyntaxPtr)(ct59))
#define CPK_ENAB 0 // Enable parity checking on input
#define CPK_DSAB 1 // Disable parity checking on input
#define CMD_BMARK_REQ (cmdSyntaxPtr)(ct60) // Bookmark request
// Enable/Disable internal loopback mode
//
#define CMD_INLOOP(arg) \
(((cmdSyntaxPtr)(ct61))->cmd[1] = (arg),(cmdSyntaxPtr)(ct61))
#define CIN_DISABLE 0 // Normal operation (default)
#define CIN_ENABLE 1 // Internal (local) loopback
#define CIN_REMOTE 2 // Remote loopback
// Specify timeout for hotkeys: Delay will be (arg x 10) milliseconds, arg == 0
// --> no timeout: wait forever.
//
#define CMD_HOT_TIME(arg) \
(((cmdSyntaxPtr)(ct62))->cmd[1] = (arg),(cmdSyntaxPtr)(ct62))
// Define (outgoing) xon for receive flow control
//
#define CMD_DEF_OXON(arg) \
(((cmdSyntaxPtr)(ct63))->cmd[1] = (arg),(cmdSyntaxPtr)(ct63))
// Define (outgoing) xoff for receiver flow control
//
#define CMD_DEF_OXOFF(arg) \
(((cmdSyntaxPtr)(ct64))->cmd[1] = (arg),(cmdSyntaxPtr)(ct64))
// Enable/Disable RTS on transmit (1/2 duplex-style)
//
#define CMD_RTS_XMIT(arg) \
(((cmdSyntaxPtr)(ct65))->cmd[1] = (arg),(cmdSyntaxPtr)(ct65))
#define CHD_DISABLE 0
#define CHD_ENABLE 1
// Set high-water-mark level (debugging use only)
//
#define CMD_SETHIGHWAT(arg) \
(((cmdSyntaxPtr)(ct66))->cmd[1] = (arg),(cmdSyntaxPtr)(ct66))
// Start flushing tagged data (tag = 0-14)
//
#define CMD_START_SELFL(tag) \
(((cmdSyntaxPtr)(ct67))->cmd[1] = (tag),(cmdSyntaxPtr)(ct67))
// End flushing tagged data (tag = 0-14)
//
#define CMD_END_SELFL(tag) \
(((cmdSyntaxPtr)(ct68))->cmd[1] = (tag),(cmdSyntaxPtr)(ct68))
#define CMD_HWFLOW_OFF (cmdSyntaxPtr)(ct69) // Disable HW TX flow control
#define CMD_ODSRFL_ENAB (cmdSyntaxPtr)(ct70) // Enable DSR output f/c
#define CMD_ODSRFL_DSAB (cmdSyntaxPtr)(ct71) // Disable DSR output f/c
#define CMD_ODCDFL_ENAB (cmdSyntaxPtr)(ct72) // Enable DCD output f/c
#define CMD_ODCDFL_DSAB (cmdSyntaxPtr)(ct73) // Disable DCD output f/c
// Set transmit interrupt load level. Count should be an even value 2-12
//
#define CMD_LOADLEVEL(count) \
(((cmdSyntaxPtr)(ct74))->cmd[1] = (count),(cmdSyntaxPtr)(ct74))
// If reporting DSS changes, map to character sequence FFh, 2, MSR
//
#define CMD_STATDATA(arg) \
(((cmdSyntaxPtr)(ct75))->cmd[1] = (arg),(cmdSyntaxPtr)(ct75))
#define CSTD_DISABLE// Report DSS changes as status packets only (default)
#define CSTD_ENABLE // Report DSS changes as in-band data sequence as well as
// by status packet.
#define CMD_BREAK_ON (cmdSyntaxPtr)(ct76)// Set break and stop xmit
#define CMD_BREAK_OFF (cmdSyntaxPtr)(ct77)// End break and restart xmit
#define CMD_GETFC (cmdSyntaxPtr)(ct78)// Request for flow control packet
// from board.
// Transmit this character immediately
//
#define CMD_XMIT_NOW(ch) \
(((cmdSyntaxPtr)(ct79))->cmd[1] = (ch),(cmdSyntaxPtr)(ct79))
// Set baud rate via "divisor latch"
//
#define CMD_DIVISOR_LATCH(which,value) \
(((cmdSyntaxPtr)(ct80))->cmd[1] = (which), \
*(USHORT *)(((cmdSyntaxPtr)(ct80))->cmd[2]) = (value), \
(cmdSyntaxPtr)(ct80))
#define CDL_RX 1 // Set receiver rate
#define CDL_TX 2 // Set transmit rate
// (CDL_TX | CDL_RX) Set both rates
// Request for special diagnostic status pkt from the board.
//
#define CMD_GET_STATUS (cmdSyntaxPtr)(ct81)
// Request time-stamped transmit character count packet.
//
#define CMD_GET_TXCNT (cmdSyntaxPtr)(ct82)
// Request time-stamped receive character count packet.
//
#define CMD_GET_RXCNT (cmdSyntaxPtr)(ct83)
// Request for box/board I.D. packet.
#define CMD_GET_BOXIDS (cmdSyntaxPtr)(ct84)
// Enable or disable multiple channels according to bit-mapped ushorts box 1-4
//
#define CMD_ENAB_MULT(enable, box1, box2, box3, box4) \
(((cmdSytaxPtr)(ct85))->cmd[1] = (enable), \
*(USHORT *)(((cmdSyntaxPtr)(ct85))->cmd[2]) = (box1), \
*(USHORT *)(((cmdSyntaxPtr)(ct85))->cmd[4]) = (box2), \
*(USHORT *)(((cmdSyntaxPtr)(ct85))->cmd[6]) = (box3), \
*(USHORT *)(((cmdSyntaxPtr)(ct85))->cmd[8]) = (box4), \
(cmdSyntaxPtr)(ct85))
#define CEM_DISABLE 0
#define CEM_ENABLE 1
// Enable or disable receiver or receiver interrupts (default both enabled)
//
#define CMD_RCV_ENABLE(ch) \
(((cmdSyntaxPtr)(ct86))->cmd[1] = (ch),(cmdSyntaxPtr)(ct86))
#define CRE_OFF 0 // Disable the receiver
#define CRE_ON 1 // Enable the receiver
#define CRE_INTOFF 2 // Disable receiver interrupts (to loadware)
#define CRE_INTON 3 // Enable receiver interrupts (to loadware)
// Starts up a hardware test process, which runs transparently, and sends a
// STAT_HWFAIL packet in case a hardware failure is detected.
//
#define CMD_HW_TEST (cmdSyntaxPtr)(ct87)
// Change receiver threshold and timeout value:
// Defaults: timeout = 20mS
// threshold count = 8 when DTRflow not in use,
// threshold count = 5 when DTRflow in use.
//
#define CMD_RCV_THRESHOLD(count,ms) \
(((cmdSyntaxPtr)(ct88))->cmd[1] = (count), \
((cmdSyntaxPtr)(ct88))->cmd[2] = (ms), \
(cmdSyntaxPtr)(ct88))
// Makes the loadware report DSS signals for this channel immediately.
//
#define CMD_DSS_NOW (cmdSyntaxPtr)(ct89)
// Set the receive silo parameters
// timeout is ms idle wait until delivery (~VTIME)
// threshold is max characters cause interrupt (~VMIN)
//
#define CMD_SET_SILO(timeout,threshold) \
(((cmdSyntaxPtr)(ct90))->cmd[1] = (timeout), \
((cmdSyntaxPtr)(ct90))->cmd[2] = (threshold), \
(cmdSyntaxPtr)(ct90))
// Set timed break in decisecond (1/10s)
//
#define CMD_LBREAK(ds) \
(((cmdSyntaxPtr)(ct91))->cmd[1] = (ds),(cmdSyntaxPtr)(ct66))
#endif // I2CMD_H

1403
drivers/staging/tty/ip2/i2ellis.c
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566
drivers/staging/tty/ip2/i2ellis.h
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@ -1,566 +0,0 @@
/*******************************************************************************
*
* (c) 1999 by Computone Corporation
*
********************************************************************************
*
*
* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
* serial I/O controllers.
*
* DESCRIPTION: Mainline code for the device driver
*
*******************************************************************************/
//------------------------------------------------------------------------------
// i2ellis.h
//
// IntelliPort-II and IntelliPort-IIEX
//
// Extremely
// Low
// Level
// Interface
// Services
//
// Structure Definitions and declarations for "ELLIS" service routines found in
// i2ellis.c
//
// These routines are based on properties of the IntelliPort-II and -IIEX
// hardware and bootstrap firmware, and are not sensitive to particular
// conventions of any particular loadware.
//
// Unlike i2hw.h, which provides IRONCLAD hardware definitions, the material
// here and in i2ellis.c is intended to provice a useful, but not required,
// layer of insulation from the hardware specifics.
//------------------------------------------------------------------------------
#ifndef I2ELLIS_H /* To prevent multiple includes */
#define I2ELLIS_H 1
//------------------------------------------------
// Revision History:
//
// 30 September 1991 MAG First Draft Started
// 12 October 1991 ...continued...
//
// 20 December 1996 AKM Linux version
//-------------------------------------------------
//----------------------
// Mandatory Includes:
//----------------------
#include "ip2types.h"
#include "i2hw.h" // The hardware definitions
//------------------------------------------
// STAT_BOXIDS packets
//------------------------------------------
#define MAX_BOX 4
typedef struct _bidStat
{
unsigned char bid_value[MAX_BOX];
} bidStat, *bidStatPtr;
// This packet is sent in response to a CMD_GET_BOXIDS bypass command. For -IIEX
// boards, reports the hardware-specific "asynchronous resource register" on
// each expansion box. Boxes not present report 0xff. For -II boards, the first
// element contains 0x80 for 8-port, 0x40 for 4-port boards.
// Box IDs aka ARR or Async Resource Register (more than you want to know)
// 7 6 5 4 3 2 1 0
// F F N N L S S S
// =============================
// F F - Product Family Designator
// =====+++++++++++++++++++++++++++++++
// 0 0 - Intelliport II EX / ISA-8
// 1 0 - IntelliServer
// 0 1 - SAC - Port Device (Intelliport III ??? )
// =====+++++++++++++++++++++++++++++++++++++++
// N N - Number of Ports
// 0 0 - 8 (eight)
// 0 1 - 4 (four)
// 1 0 - 12 (twelve)
// 1 1 - 16 (sixteen)
// =++++++++++++++++++++++++++++++++++
// L - LCD Display Module Present
// 0 - No
// 1 - LCD module present
// =========+++++++++++++++++++++++++++++++++++++
// S S S - Async Signals Supported Designator
// 0 0 0 - 8dss, Mod DCE DB25 Female
// 0 0 1 - 6dss, RJ-45
// 0 1 0 - RS-232/422 dss, DB25 Female
// 0 1 1 - RS-232/422 dss, separate 232/422 DB25 Female
// 1 0 0 - 6dss, 921.6 I/F with ST654's
// 1 0 1 - RS-423/232 8dss, RJ-45 10Pin
// 1 1 0 - 6dss, Mod DCE DB25 Female
// 1 1 1 - NO BOX PRESENT
#define FF(c) ((c & 0xC0) >> 6)
#define NN(c) ((c & 0x30) >> 4)
#define L(c) ((c & 0x08) >> 3)
#define SSS(c) (c & 0x07)
#define BID_HAS_654(x) (SSS(x) == 0x04)
#define BID_NO_BOX 0xff /* no box */
#define BID_8PORT 0x80 /* IP2-8 port */
#define BID_4PORT 0x81 /* IP2-4 port */
#define BID_EXP_MASK 0x30 /* IP2-EX */
#define BID_EXP_8PORT 0x00 /* 8, */
#define BID_EXP_4PORT 0x10 /* 4, */
#define BID_EXP_UNDEF 0x20 /* UNDEF, */
#define BID_EXP_16PORT 0x30 /* 16, */
#define BID_LCD_CTRL 0x08 /* LCD Controller */
#define BID_LCD_NONE 0x00 /* - no controller present */
#define BID_LCD_PRES 0x08 /* - controller present */
#define BID_CON_MASK 0x07 /* - connector pinouts */
#define BID_CON_DB25 0x00 /* - DB-25 F */
#define BID_CON_RJ45 0x01 /* - rj45 */
//------------------------------------------------------------------------------
// i2eBordStr
//
// This structure contains all the information the ELLIS routines require in
// dealing with a particular board.
//------------------------------------------------------------------------------
// There are some queues here which are guaranteed to never contain the entry
// for a single channel twice. So they must be slightly larger to allow
// unambiguous full/empty management
//
#define CH_QUEUE_SIZE ABS_MOST_PORTS+2
typedef struct _i2eBordStr
{
porStr i2ePom; // Structure containing the power-on message.
unsigned short i2ePomSize;
// The number of bytes actually read if
// different from sizeof i2ePom, indicates
// there is an error!
unsigned short i2eStartMail;
// Contains whatever inbound mailbox data
// present at startup. NO_MAIL_HERE indicates
// nothing was present. No special
// significance as of this writing, but may be
// useful for diagnostic reasons.
unsigned short i2eValid;
// Indicates validity of the structure; if
// i2eValid == I2E_MAGIC, then we can trust
// the other fields. Some (especially
// initialization) functions are good about
// checking for validity. Many functions do
// not, it being assumed that the larger
// context assures we are using a valid
// i2eBordStrPtr.
unsigned short i2eError;
// Used for returning an error condition from
// several functions which use i2eBordStrPtr
// as an argument.
// Accelerators to characterize separate features of a board, derived from a
// number of sources.
unsigned short i2eFifoSize;
// Always, the size of the FIFO. For
// IntelliPort-II, always the same, for -IIEX
// taken from the Power-On reset message.
volatile
unsigned short i2eFifoRemains;
// Used during normal operation to indicate a
// lower bound on the amount of data which
// might be in the outbound fifo.
unsigned char i2eFifoStyle;
// Accelerator which tells which style (-II or
// -IIEX) FIFO we are using.
unsigned char i2eDataWidth16;
// Accelerator which tells whether we should
// do 8 or 16-bit data transfers.
unsigned char i2eMaxIrq;
// The highest allowable IRQ, based on the
// slot size.
// Accelerators for various addresses on the board
int i2eBase; // I/O Address of the Board
int i2eData; // From here data transfers happen
int i2eStatus; // From here status reads happen
int i2ePointer; // (IntelliPort-II: pointer/commands)
int i2eXMail; // (IntelliPOrt-IIEX: mailboxes
int i2eXMask; // (IntelliPort-IIEX: mask write
//-------------------------------------------------------
// Information presented in a common format across boards
// For each box, bit map of the channels present. Box closest to
// the host is box 0. LSB is channel 0. IntelliPort-II (non-expandable)
// is taken to be box 0. These are derived from product i.d. registers.
unsigned short i2eChannelMap[ABS_MAX_BOXES];
// Same as above, except each is derived from firmware attempting to detect
// the uart presence (by reading a valid GFRCR register). If bits are set in
// i2eChannelMap and not in i2eGoodMap, there is a potential problem.
unsigned short i2eGoodMap[ABS_MAX_BOXES];
// ---------------------------
// For indirect function calls
// Routine to cause an N-millisecond delay: Patched by the ii2Initialize
// function.
void (*i2eDelay)(unsigned int);
// Routine to write N bytes to the board through the FIFO. Returns true if
// all copacetic, otherwise returns false and error is in i2eError field.
// IF COUNT IS ODD, ROUNDS UP TO THE NEXT EVEN NUMBER.
int (*i2eWriteBuf)(struct _i2eBordStr *, unsigned char *, int);
// Routine to read N bytes from the board through the FIFO. Returns true if
// copacetic, otherwise returns false and error in i2eError.
// IF COUNT IS ODD, ROUNDS UP TO THE NEXT EVEN NUMBER.
int (*i2eReadBuf)(struct _i2eBordStr *, unsigned char *, int);
// Returns a word from FIFO. Will use 2 byte operations if needed.
unsigned short (*i2eReadWord)(struct _i2eBordStr *);
// Writes a word to FIFO. Will use 2 byte operations if needed.
void (*i2eWriteWord)(struct _i2eBordStr *, unsigned short);
// Waits specified time for the Transmit FIFO to go empty. Returns true if
// ok, otherwise returns false and error in i2eError.
int (*i2eWaitForTxEmpty)(struct _i2eBordStr *, int);
// Returns true or false according to whether the outgoing mailbox is empty.
int (*i2eTxMailEmpty)(struct _i2eBordStr *);
// Checks whether outgoing mailbox is empty. If so, sends mail and returns
// true. Otherwise returns false.
int (*i2eTrySendMail)(struct _i2eBordStr *, unsigned char);
// If no mail available, returns NO_MAIL_HERE, else returns the value in the
// mailbox (guaranteed can't be NO_MAIL_HERE).
unsigned short (*i2eGetMail)(struct _i2eBordStr *);
// Enables the board to interrupt the host when it writes to the mailbox.
// Irqs will not occur, however, until the loadware separately enables
// interrupt generation to the host. The standard loadware does this in
// response to a command packet sent by the host. (Also, disables
// any other potential interrupt sources from the board -- other than the
// inbound mailbox).
void (*i2eEnableMailIrq)(struct _i2eBordStr *);
// Writes an arbitrary value to the mask register.
void (*i2eWriteMask)(struct _i2eBordStr *, unsigned char);
// State information
// During downloading, indicates the number of blocks remaining to download
// to the board.
short i2eToLoad;
// State of board (see manifests below) (e.g., whether in reset condition,
// whether standard loadware is installed, etc.
unsigned char i2eState;
// These three fields are only valid when there is loadware running on the
// board. (i2eState == II_STATE_LOADED or i2eState == II_STATE_STDLOADED )
unsigned char i2eLVersion; // Loadware version
unsigned char i2eLRevision; // Loadware revision
unsigned char i2eLSub; // Loadware subrevision
// Flags which only have meaning in the context of the standard loadware.
// Somewhat violates the layering concept, but there is so little additional
// needed at the board level (while much additional at the channel level),
// that this beats maintaining two different per-board structures.
// Indicates which IRQ the board has been initialized (from software) to use
// For MicroChannel boards, any value different from IRQ_UNDEFINED means
// that the software command has been sent to enable interrupts (or specify
// they are disabled). Special value: IRQ_UNDEFINED indicates that the
// software command to select the interrupt has not yet been sent, therefore
// (since the standard loadware insists that it be sent before any other
// packets are sent) no other packets should be sent yet.
unsigned short i2eUsingIrq;
// This is set when we hit the MB_OUT_STUFFED mailbox, which prevents us
// putting more in the mailbox until an appropriate mailbox message is
// received.
unsigned char i2eWaitingForEmptyFifo;
// Any mailbox bits waiting to be sent to the board are OR'ed in here.
unsigned char i2eOutMailWaiting;
// The head of any incoming packet is read into here, is then examined and
// we dispatch accordingly.
unsigned short i2eLeadoffWord[1];
// Running counter of interrupts where the mailbox indicated incoming data.
unsigned short i2eFifoInInts;
// Running counter of interrupts where the mailbox indicated outgoing data
// had been stripped.
unsigned short i2eFifoOutInts;
// If not void, gives the address of a routine to call if fatal board error
// is found (only applies to standard l/w).
void (*i2eFatalTrap)(struct _i2eBordStr *);
// Will point to an array of some sort of channel structures (whose format
// is unknown at this level, being a function of what loadware is
// installed and the code configuration (max sizes of buffers, etc.)).
void *i2eChannelPtr;
// Set indicates that the board has gone fatal.
unsigned short i2eFatal;
// The number of elements pointed to by i2eChannelPtr.
unsigned short i2eChannelCnt;
// Ring-buffers of channel structures whose channels have particular needs.
rwlock_t Fbuf_spinlock;
volatile
unsigned short i2Fbuf_strip; // Strip index
volatile
unsigned short i2Fbuf_stuff; // Stuff index
void *i2Fbuf[CH_QUEUE_SIZE]; // An array of channel pointers
// of channels who need to send
// flow control packets.
rwlock_t Dbuf_spinlock;
volatile
unsigned short i2Dbuf_strip; // Strip index
volatile
unsigned short i2Dbuf_stuff; // Stuff index
void *i2Dbuf[CH_QUEUE_SIZE]; // An array of channel pointers
// of channels who need to send
// data or in-line command packets.
rwlock_t Bbuf_spinlock;
volatile
unsigned short i2Bbuf_strip; // Strip index
volatile
unsigned short i2Bbuf_stuff; // Stuff index
void *i2Bbuf[CH_QUEUE_SIZE]; // An array of channel pointers
// of channels who need to send
// bypass command packets.
/*
* A set of flags to indicate that certain events have occurred on at least
* one of the ports on this board. We use this to decide whether to spin
* through the channels looking for breaks, etc.
*/
int got_input;
int status_change;
bidStat channelBtypes;
/*
* Debugging counters, etc.
*/
unsigned long debugFlowQueued;
unsigned long debugInlineQueued;
unsigned long debugDataQueued;
unsigned long debugBypassQueued;
unsigned long debugFlowCount;
unsigned long debugInlineCount;
unsigned long debugBypassCount;
rwlock_t read_fifo_spinlock;
rwlock_t write_fifo_spinlock;
// For queuing interrupt bottom half handlers. /\/\|=mhw=|\/\/
struct work_struct tqueue_interrupt;
struct timer_list SendPendingTimer; // Used by iiSendPending
unsigned int SendPendingRetry;
} i2eBordStr, *i2eBordStrPtr;
//-------------------------------------------------------------------
// Macro Definitions for the indirect calls defined in the i2eBordStr
//-------------------------------------------------------------------
//
#define iiDelay(a,b) (*(a)->i2eDelay)(b)
#define iiWriteBuf(a,b,c) (*(a)->i2eWriteBuf)(a,b,c)
#define iiReadBuf(a,b,c) (*(a)->i2eReadBuf)(a,b,c)
#define iiWriteWord(a,b) (*(a)->i2eWriteWord)(a,b)
#define iiReadWord(a) (*(a)->i2eReadWord)(a)
#define iiWaitForTxEmpty(a,b) (*(a)->i2eWaitForTxEmpty)(a,b)
#define iiTxMailEmpty(a) (*(a)->i2eTxMailEmpty)(a)
#define iiTrySendMail(a,b) (*(a)->i2eTrySendMail)(a,b)
#define iiGetMail(a) (*(a)->i2eGetMail)(a)
#define iiEnableMailIrq(a) (*(a)->i2eEnableMailIrq)(a)
#define iiDisableMailIrq(a) (*(a)->i2eWriteMask)(a,0)
#define iiWriteMask(a,b) (*(a)->i2eWriteMask)(a,b)
//-------------------------------------------
// Manifests for i2eBordStr:
//-------------------------------------------
typedef void (*delayFunc_t)(unsigned int);
// i2eValid
//
#define I2E_MAGIC 0x4251 // Structure is valid.
#define I2E_INCOMPLETE 0x1122 // Structure failed during init.
// i2eError
//
#define I2EE_GOOD 0 // Operation successful
#define I2EE_BADADDR 1 // Address out of range
#define I2EE_BADSTATE 2 // Attempt to perform a function when the board
// structure was in the incorrect state
#define I2EE_BADMAGIC 3 // Bad magic number from Power On test (i2ePomSize
// reflects what was read
#define I2EE_PORM_SHORT 4 // Power On message too short
#define I2EE_PORM_LONG 5 // Power On message too long
#define I2EE_BAD_FAMILY 6 // Un-supported board family type
#define I2EE_INCONSIST 7 // Firmware reports something impossible,
// e.g. unexpected number of ports... Almost no
// excuse other than bad FIFO...
#define I2EE_POSTERR 8 // Power-On self test reported a bad error
#define I2EE_BADBUS 9 // Unknown Bus type declared in message
#define I2EE_TXE_TIME 10 // Timed out waiting for TX Fifo to empty
#define I2EE_INVALID 11 // i2eValid field does not indicate a valid and
// complete board structure (for functions which
// require this be so.)
#define I2EE_BAD_PORT 12 // Discrepancy between channels actually found and
// what the product is supposed to have. Check
// i2eGoodMap vs i2eChannelMap for details.
#define I2EE_BAD_IRQ 13 // Someone specified an unsupported IRQ
#define I2EE_NOCHANNELS 14 // No channel structures have been defined (for
// functions requiring this).
// i2eFifoStyle
//
#define FIFO_II 0 /* IntelliPort-II style: see also i2hw.h */
#define FIFO_IIEX 1 /* IntelliPort-IIEX style */
// i2eGetMail
//
#define NO_MAIL_HERE 0x1111 // Since mail is unsigned char, cannot possibly
// promote to 0x1111.
// i2eState
//
#define II_STATE_COLD 0 // Addresses have been defined, but board not even
// reset yet.
#define II_STATE_RESET 1 // Board,if it exists, has just been reset
#define II_STATE_READY 2 // Board ready for its first block
#define II_STATE_LOADING 3 // Board continuing load
#define II_STATE_LOADED 4 // Board has finished load: status ok
#define II_STATE_BADLOAD 5 // Board has finished load: failed!
#define II_STATE_STDLOADED 6 // Board has finished load: standard firmware
// i2eUsingIrq
//
#define I2_IRQ_UNDEFINED 0x1352 /* No valid irq (or polling = 0) can
* ever promote to this! */
//------------------------------------------
// Handy Macros for i2ellis.c and others
// Note these are common to -II and -IIEX
//------------------------------------------
// Given a pointer to the board structure, does the input FIFO have any data or
// not?
//
#define I2_HAS_INPUT(pB) !(inb(pB->i2eStatus) & ST_IN_EMPTY)
// Given a pointer to the board structure, is there anything in the incoming
// mailbox?
//
#define I2_HAS_MAIL(pB) (inb(pB->i2eStatus) & ST_IN_MAIL)
#define I2_UPDATE_FIFO_ROOM(pB) ((pB)->i2eFifoRemains = (pB)->i2eFifoSize)
//------------------------------------------
// Function Declarations for i2ellis.c
//------------------------------------------
//
// Functions called directly
//
// Initialization of a board & structure is in four (five!) parts:
//
// 1) iiSetAddress() - Define the board address & delay function for a board.
// 2) iiReset() - Reset the board (provided it exists)
// -- Note you may do this to several boards --
// 3) iiResetDelay() - Delay for 2 seconds (once for all boards)
// 4) iiInitialize() - Attempt to read Power-up message; further initialize
// accelerators
//
// Then you may use iiDownloadAll() or iiDownloadFile() (in i2file.c) to write
// loadware. To change loadware, you must begin again with step 2, resetting
// the board again (step 1 not needed).
static int iiSetAddress(i2eBordStrPtr, int, delayFunc_t );
static int iiReset(i2eBordStrPtr);
static int iiResetDelay(i2eBordStrPtr);
static int iiInitialize(i2eBordStrPtr);
// Routine to validate that all channels expected are there.
//
extern int iiValidateChannels(i2eBordStrPtr);
// Routine used to download a block of loadware.
//
static int iiDownloadBlock(i2eBordStrPtr, loadHdrStrPtr, int);
// Return values given by iiDownloadBlock, iiDownloadAll, iiDownloadFile:
//
#define II_DOWN_BADVALID 0 // board structure is invalid
#define II_DOWN_CONTINUING 1 // So far, so good, firmware expects more
#define II_DOWN_GOOD 2 // Download complete, CRC good
#define II_DOWN_BAD 3 // Download complete, but CRC bad
#define II_DOWN_BADFILE 4 // Bad magic number in loadware file
#define II_DOWN_BADSTATE 5 // Board is in an inappropriate state for
// downloading loadware. (see i2eState)
#define II_DOWN_TIMEOUT 6 // Timeout waiting for firmware
#define II_DOWN_OVER 7 // Too much data
#define II_DOWN_UNDER 8 // Not enough data
#define II_DOWN_NOFILE 9 // Loadware file not found
// Routine to download an entire loadware module: Return values are a subset of
// iiDownloadBlock's, excluding, of course, II_DOWN_CONTINUING
//
static int iiDownloadAll(i2eBordStrPtr, loadHdrStrPtr, int, int);
// Many functions defined here return True if good, False otherwise, with an
// error code in i2eError field. Here is a handy macro for setting the error
// code and returning.
//
#define I2_COMPLETE(pB,code) do { \
pB->i2eError = code; \
return (code == I2EE_GOOD);\
} while (0)
#endif // I2ELLIS_H

652
drivers/staging/tty/ip2/i2hw.h
View file

@ -1,652 +0,0 @@
/*******************************************************************************
*
* (c) 1999 by Computone Corporation
*
********************************************************************************
*
*
* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
* serial I/O controllers.
*
* DESCRIPTION: Definitions limited to properties of the hardware or the
* bootstrap firmware. As such, they are applicable regardless of
* operating system or loadware (standard or diagnostic).
*
*******************************************************************************/
#ifndef I2HW_H
#define I2HW_H 1
//------------------------------------------------------------------------------
// Revision History:
//
// 23 September 1991 MAG First Draft Started...through...
// 11 October 1991 ... Continuing development...
// 6 August 1993 Added support for ISA-4 (asic) which is architected
// as an ISA-CEX with a single 4-port box.
//
// 20 December 1996 AKM Version for Linux
//
//------------------------------------------------------------------------------
/*------------------------------------------------------------------------------
HARDWARE DESCRIPTION:
Introduction:
The IntelliPort-II and IntelliPort-IIEX products occupy a block of eight (8)
addresses in the host's I/O space.
Some addresses are used to transfer data to/from the board, some to transfer
so-called "mailbox" messages, and some to read bit-mapped status information.
While all the products in the line are functionally similar, some use a 16-bit
data path to transfer data while others use an 8-bit path. Also, the use of
command /status/mailbox registers differs slightly between the II and IIEX
branches of the family.
The host determines what type of board it is dealing with by reading a string of
sixteen characters from the board. These characters are always placed in the
fifo by the board's local processor whenever the board is reset (either from
power-on or under software control) and are known as the "Power-on Reset
Message." In order that this message can be read from either type of board, the
hardware registers used in reading this message are the same. Once this message
has been read by the host, then it has the information required to operate.
General Differences between boards:
The greatest structural difference is between the -II and -IIEX families of
product. The -II boards use the Am4701 dual 512x8 bidirectional fifo to support
the data path, mailbox registers, and status registers. This chip contains some
features which are not used in the IntelliPort-II products; a description of
these is omitted here. Because of these many features, it contains many
registers, too many to access directly within a small address space. They are
accessed by first writing a value to a "pointer" register. This value selects
the register to be accessed. The next read or write to that address accesses
the selected register rather than the pointer register.
The -IIEX boards use a proprietary design similar to the Am4701 in function. But
because of a simpler, more streamlined design it doesn't require so many
registers. This means they can be accessed directly in single operations rather
than through a pointer register.
Besides these differences, there are differences in whether 8-bit or 16-bit
transfers are used to move data to the board.
The -II boards are capable only of 8-bit data transfers, while the -IIEX boards
may be configured for either 8-bit or 16-bit data transfers. If the on-board DIP
switch #8 is ON, and the card has been installed in a 16-bit slot, 16-bit
transfers are supported (and will be expected by the standard loadware). The
on-board firmware can determine the position of the switch, and whether the
board is installed in a 16-bit slot; it supplies this information to the host as
part of the power-up reset message.
The configuration switch (#8) and slot selection do not directly configure the
hardware. It is up to the on-board loadware and host-based drivers to act
according to the selected options. That is, loadware and drivers could be
written to perform 8-bit transfers regardless of the state of the DIP switch or
slot (and in a diagnostic environment might well do so). Likewise, 16-bit
transfers could be performed as long as the card is in a 16-bit slot.
Note the slot selection and DIP switch selection are provided separately: a
board running in 8-bit mode in a 16-bit slot has a greater range of possible
interrupts to choose from; information of potential use to the host.
All 8-bit data transfers are done in the same way, regardless of whether on a
-II board or a -IIEX board.
The host must consider two things then: 1) whether a -II or -IIEX product is
being used, and 2) whether an 8-bit or 16-bit data path is used.
A further difference is that -II boards always have a 512-byte fifo operating in
each direction. -IIEX boards may use fifos of varying size; this size is
reported as part of the power-up message.
I/O Map Of IntelliPort-II and IntelliPort-IIEX boards:
(Relative to the chosen base address)
Addr R/W IntelliPort-II IntelliPort-IIEX
---- --- -------------- ----------------
0 R/W Data Port (byte) Data Port (byte or word)
1 R/W (Not used) (MSB of word-wide data written to Data Port)
2 R Status Register Status Register
2 W Pointer Register Interrupt Mask Register
3 R/W (Not used) Mailbox Registers (6 bits: 11111100)
4,5 -- Reserved for future products
6 -- Reserved for future products
7 R Guaranteed to have no effect
7 W Hardware reset of board.
Rules:
All data transfers are performed using the even i/o address. If byte-wide data
transfers are being used, do INB/OUTB operations on the data port. If word-wide
transfers are used, do INW/OUTW operations. In some circumstances (such as
reading the power-up message) you will do INB from the data port, but in this
case the MSB of each word read is lost. When accessing all other unreserved
registers, use byte operations only.
------------------------------------------------------------------------------*/
//------------------------------------------------
// Mandatory Includes:
//------------------------------------------------
//
#include "ip2types.h"
//-------------------------------------------------------------------------
// Manifests for the I/O map:
//-------------------------------------------------------------------------
// R/W: Data port (byte) for IntelliPort-II,
// R/W: Data port (byte or word) for IntelliPort-IIEX
// Incoming or outgoing data passes through a FIFO, the status of which is
// available in some of the bits in FIFO_STATUS. This (bidirectional) FIFO is
// the primary means of transferring data, commands, flow-control, and status
// information between the host and board.
//
#define FIFO_DATA 0
// Another way of passing information between the board and the host is
// through "mailboxes". Unlike a FIFO, a mailbox holds only a single byte of
// data. Writing data to the mailbox causes a status bit to be set, and
// potentially interrupting the intended receiver. The sender has some way to
// determine whether the data has been read yet; as soon as it has, it may send
// more. The mailboxes are handled differently on -II and -IIEX products, as
// suggested below.
//------------------------------------------------------------------------------
// Read: Status Register for IntelliPort-II or -IIEX
// The presence of any bit set here will cause an interrupt to the host,
// provided the corresponding bit has been unmasked in the interrupt mask
// register. Furthermore, interrupts to the host are disabled globally until the
// loadware selects the irq line to use. With the exception of STN_MR, the bits
// remain set so long as the associated condition is true.
//
#define FIFO_STATUS 2
// Bit map of status bits which are identical for -II and -IIEX
//
#define ST_OUT_FULL 0x40 // Outbound FIFO full
#define ST_IN_EMPTY 0x20 // Inbound FIFO empty
#define ST_IN_MAIL 0x04 // Inbound Mailbox full
// The following exists only on the Intelliport-IIEX, and indicates that the
// board has not read the last outgoing mailbox data yet. In the IntelliPort-II,
// the outgoing mailbox may be read back: a zero indicates the board has read
// the data.
//
#define STE_OUT_MAIL 0x80 // Outbound mailbox full (!)
// The following bits are defined differently for -II and -IIEX boards. Code
// which relies on these bits will need to be functionally different for the two
// types of boards and should be generally avoided because of the additional
// complexity this creates:
// Bit map of status bits only on -II
// Fifo has been RESET (cleared when the status register is read). Note that
// this condition cannot be masked and would always interrupt the host, except
// that the hardware reset also disables interrupts globally from the board
// until re-enabled by loadware. This could also arise from the
// Am4701-supported command to reset the chip, but this command is generally not
// used here.
//
#define STN_MR 0x80
// See the AMD Am4701 data sheet for details on the following four bits. They
// are not presently used by Computone drivers.
//
#define STN_OUT_AF 0x10 // Outbound FIFO almost full (programmable)
#define STN_IN_AE 0x08 // Inbound FIFO almost empty (programmable)
#define STN_BD 0x02 // Inbound byte detected
#define STN_PE 0x01 // Parity/Framing condition detected
// Bit-map of status bits only on -IIEX
//
#define STE_OUT_HF 0x10 // Outbound FIFO half full
#define STE_IN_HF 0x08 // Inbound FIFO half full
#define STE_IN_FULL 0x02 // Inbound FIFO full
#define STE_OUT_MT 0x01 // Outbound FIFO empty
//------------------------------------------------------------------------------
// Intelliport-II -- Write Only: the pointer register.
// Values are written to this register to select the Am4701 internal register to
// be accessed on the next operation.
//
#define FIFO_PTR 0x02
// Values for the pointer register
//
#define SEL_COMMAND 0x1 // Selects the Am4701 command register
// Some possible commands:
//
#define SEL_CMD_MR 0x80 // Am4701 command to reset the chip
#define SEL_CMD_SH 0x40 // Am4701 command to map the "other" port into the
// status register.
#define SEL_CMD_UNSH 0 // Am4701 command to "unshift": port maps into its
// own status register.
#define SEL_MASK 0x2 // Selects the Am4701 interrupt mask register. The
// interrupt mask register is bit-mapped to match
// the status register (FIFO_STATUS) except for
// STN_MR. (See above.)
#define SEL_BYTE_DET 0x3 // Selects the Am4701 byte-detect register. (Not
// normally used except in diagnostics.)
#define SEL_OUTMAIL 0x4 // Selects the outbound mailbox (R/W). Reading back
// a value of zero indicates that the mailbox has
// been read by the board and is available for more
// data./ Writing to the mailbox optionally
// interrupts the board, depending on the loadware's
// setting of its interrupt mask register.
#define SEL_AEAF 0x5 // Selects AE/AF threshold register.
#define SEL_INMAIL 0x6 // Selects the inbound mailbox (Read)
//------------------------------------------------------------------------------
// IntelliPort-IIEX -- Write Only: interrupt mask (and misc flags) register:
// Unlike IntelliPort-II, bit assignments do NOT match those of the status
// register.
//
#define FIFO_MASK 0x2
// Mailbox readback select:
// If set, reads to FIFO_MAIL will read the OUTBOUND mailbox (host to board). If
// clear (default on reset) reads to FIFO_MAIL will read the INBOUND mailbox.
// This is the normal situation. The clearing of a mailbox is determined on
// -IIEX boards by waiting for the STE_OUT_MAIL bit to clear. Readback
// capability is provided for diagnostic purposes only.
//
#define MX_OUTMAIL_RSEL 0x80
#define MX_IN_MAIL 0x40 // Enables interrupts when incoming mailbox goes
// full (ST_IN_MAIL set).
#define MX_IN_FULL 0x20 // Enables interrupts when incoming FIFO goes full
// (STE_IN_FULL).
#define MX_IN_MT 0x08 // Enables interrupts when incoming FIFO goes empty
// (ST_IN_MT).
#define MX_OUT_FULL 0x04 // Enables interrupts when outgoing FIFO goes full
// (ST_OUT_FULL).
#define MX_OUT_MT 0x01 // Enables interrupts when outgoing FIFO goes empty
// (STE_OUT_MT).
// Any remaining bits are reserved, and should be written to ZERO for
// compatibility with future Computone products.
//------------------------------------------------------------------------------
// IntelliPort-IIEX: -- These are only 6-bit mailboxes !!! -- 11111100 (low two
// bits always read back 0).
// Read: One of the mailboxes, usually Inbound.
// Inbound Mailbox (MX_OUTMAIL_RSEL = 0)
// Outbound Mailbox (MX_OUTMAIL_RSEL = 1)
// Write: Outbound Mailbox
// For the IntelliPort-II boards, the outbound mailbox is read back to determine
// whether the board has read the data (0 --> data has been read). For the
// IntelliPort-IIEX, this is done by reading a status register. To determine
// whether mailbox is available for more outbound data, use the STE_OUT_MAIL bit
// in FIFO_STATUS. Moreover, although the Outbound Mailbox can be read back by
// setting MX_OUTMAIL_RSEL, it is NOT cleared when the board reads it, as is the
// case with the -II boards. For this reason, FIFO_MAIL is normally used to read
// the inbound FIFO, and MX_OUTMAIL_RSEL kept clear. (See above for
// MX_OUTMAIL_RSEL description.)
//
#define FIFO_MAIL 0x3
//------------------------------------------------------------------------------
// WRITE ONLY: Resets the board. (Data doesn't matter).
//
#define FIFO_RESET 0x7
//------------------------------------------------------------------------------
// READ ONLY: Will have no effect. (Data is undefined.)
// Actually, there will be an effect, in that the operation is sure to generate
// a bus cycle: viz., an I/O byte Read. This fact can be used to enforce short
// delays when no comparable time constant is available.
//
#define FIFO_NOP 0x7
//------------------------------------------------------------------------------
// RESET & POWER-ON RESET MESSAGE
/*------------------------------------------------------------------------------
RESET:
The IntelliPort-II and -IIEX boards are reset in three ways: Power-up, channel
reset, and via a write to the reset register described above. For products using
the ISA bus, these three sources of reset are equvalent. For MCA and EISA buses,
the Power-up and channel reset sources cause additional hardware initialization
which should only occur at system startup time.
The third type of reset, called a "command reset", is done by writing any data
to the FIFO_RESET address described above. This resets the on-board processor,
FIFO, UARTS, and associated hardware.
This passes control of the board to the bootstrap firmware, which performs a
Power-On Self Test and which detects its current configuration. For example,
-IIEX products determine the size of FIFO which has been installed, and the
number and type of expansion boxes attached.
This and other information is then written to the FIFO in a 16-byte data block
to be read by the host. This block is guaranteed to be present within two (2)
seconds of having received the command reset. The firmware is now ready to
receive loadware from the host.
It is good practice to perform a command reset to the board explicitly as part
of your software initialization. This allows your code to properly restart from
a soft boot. (Many systems do not issue channel reset on soft boot).
Because of a hardware reset problem on some of the Cirrus Logic 1400's which are
used on the product, it is recommended that you reset the board twice, separated
by an approximately 50 milliseconds delay. (VERY approximately: probably ok to
be off by a factor of five. The important point is that the first command reset
in fact generates a reset pulse on the board. This pulse is guaranteed to last
less than 10 milliseconds. The additional delay ensures the 1400 has had the
chance to respond sufficiently to the first reset. Why not a longer delay? Much
more than 50 milliseconds gets to be noticeable, but the board would still work.
Once all 16 bytes of the Power-on Reset Message have been read, the bootstrap
firmware is ready to receive loadware.
Note on Power-on Reset Message format:
The various fields have been designed with future expansion in view.
Combinations of bitfields and values have been defined which define products
which may not currently exist. This has been done to allow drivers to anticipate
the possible introduction of products in a systematic fashion. This is not
intended to suggest that each potential product is actually under consideration.
------------------------------------------------------------------------------*/
//----------------------------------------
// Format of Power-on Reset Message
//----------------------------------------
typedef union _porStr // "por" stands for Power On Reset
{
unsigned char c[16]; // array used when considering the message as a
// string of undifferentiated characters
struct // Elements used when considering values
{
// The first two bytes out of the FIFO are two magic numbers. These are
// intended to establish that there is indeed a member of the
// IntelliPort-II(EX) family present. The remaining bytes may be
// expected // to be valid. When reading the Power-on Reset message,
// if the magic numbers do not match it is probably best to stop
// reading immediately. You are certainly not reading our board (unless
// hardware is faulty), and may in fact be reading some other piece of
// hardware.
unsigned char porMagic1; // magic number: first byte == POR_MAGIC_1
unsigned char porMagic2; // magic number: second byte == POR_MAGIC_2
// The Version, Revision, and Subrevision are stored as absolute numbers
// and would normally be displayed in the format V.R.S (e.g. 1.0.2)
unsigned char porVersion; // Bootstrap firmware version number
unsigned char porRevision; // Bootstrap firmware revision number
unsigned char porSubRev; // Bootstrap firmware sub-revision number
unsigned char porID; // Product ID: Bit-mapped according to
// conventions described below. Among other
// things, this allows us to distinguish
// IntelliPort-II boards from IntelliPort-IIEX
// boards.
unsigned char porBus; // IntelliPort-II: Unused
// IntelliPort-IIEX: Bus Information:
// Bit-mapped below
unsigned char porMemory; // On-board DRAM size: in 32k blocks
// porPorts1 (and porPorts2) are used to determine the ports which are
// available to the board. For non-expandable product, a single number
// is sufficient. For expandable product, the board may be connected
// to as many as four boxes. Each box may be (so far) either a 16-port
// or an 8-port size. Whenever an 8-port box is used, the remaining 8
// ports leave gaps between existing channels. For that reason,
// expandable products must report a MAP of available channels. Since
// each UART supports four ports, we represent each UART found by a
// single bit. Using two bytes to supply the mapping information we
// report the presence or absence of up to 16 UARTS, or 64 ports in
// steps of 4 ports. For -IIEX products, the ports are numbered
// starting at the box closest to the controller in the "chain".
// Interpreted Differently for IntelliPort-II and -IIEX.
// -II: Number of ports (Derived actually from product ID). See
// Diag1&2 to indicate if uart was actually detected.
// -IIEX: Bit-map of UARTS found, LSB (see below for MSB of this). This
// bitmap is based on detecting the uarts themselves;
// see porFlags for information from the box i.d's.
unsigned char porPorts1;
unsigned char porDiag1; // Results of on-board P.O.S.T, 1st byte
unsigned char porDiag2; // Results of on-board P.O.S.T, 2nd byte
unsigned char porSpeed; // Speed of local CPU: given as MHz x10
// e.g., 16.0 MHz CPU is reported as 160
unsigned char porFlags; // Misc information (see manifests below)
// Bit-mapped: CPU type, UART's present
unsigned char porPorts2; // -II: Undefined
// -IIEX: Bit-map of UARTS found, MSB (see
// above for LSB)
// IntelliPort-II: undefined
// IntelliPort-IIEX: 1 << porFifoSize gives the size, in bytes, of the
// host interface FIFO, in each direction. When running the -IIEX in
// 8-bit mode, fifo capacity is halved. The bootstrap firmware will
// have already accounted for this fact in generating this number.
unsigned char porFifoSize;
// IntelliPort-II: undefined
// IntelliPort-IIEX: The number of boxes connected. (Presently 1-4)
unsigned char porNumBoxes;
} e;
} porStr, *porStrPtr;
//--------------------------
// Values for porStr fields
//--------------------------
//---------------------
// porMagic1, porMagic2
//----------------------
//
#define POR_MAGIC_1 0x96 // The only valid value for porMagic1
#define POR_MAGIC_2 0x35 // The only valid value for porMagic2
#define POR_1_INDEX 0 // Byte position of POR_MAGIC_1
#define POR_2_INDEX 1 // Ditto for POR_MAGIC_2
//----------------------
// porID
//----------------------
//
#define POR_ID_FAMILY 0xc0 // These bits indicate the general family of
// product.
#define POR_ID_FII 0x00 // Family is "IntelliPort-II"
#define POR_ID_FIIEX 0x40 // Family is "IntelliPort-IIEX"
// These bits are reserved, presently zero. May be used at a later date to
// convey other product information.
//
#define POR_ID_RESERVED 0x3c
#define POR_ID_SIZE 0x03 // Remaining bits indicate number of ports &
// Connector information.
#define POR_ID_II_8 0x00 // For IntelliPort-II, indicates 8-port using
// standard brick.
#define POR_ID_II_8R 0x01 // For IntelliPort-II, indicates 8-port using
// RJ11's (no CTS)
#define POR_ID_II_6 0x02 // For IntelliPort-II, indicates 6-port using
// RJ45's
#define POR_ID_II_4 0x03 // For IntelliPort-II, indicates 4-port using
// 4xRJ45 connectors
#define POR_ID_EX 0x00 // For IntelliPort-IIEX, indicates standard
// expandable controller (other values reserved)
//----------------------
// porBus
//----------------------
// IntelliPort-IIEX only: Board is installed in a 16-bit slot
//
#define POR_BUS_SLOT16 0x20
// IntelliPort-IIEX only: DIP switch #8 is on, selecting 16-bit host interface
// operation.
//
#define POR_BUS_DIP16 0x10
// Bits 0-2 indicate type of bus: This information is stored in the bootstrap
// loadware, different loadware being used on different products for different
// buses. For most situations, the drivers do not need this information; but it
// is handy in a diagnostic environment. For example, on microchannel boards,
// you would not want to try to test several interrupts, only the one for which
// you were configured.
//
#define POR_BUS_TYPE 0x07
// Unknown: this product doesn't know what bus it is running in. (e.g. if same
// bootstrap firmware were wanted for two different buses.)
//
#define POR_BUS_T_UNK 0
// Note: existing firmware for ISA-8 and MC-8 currently report the POR_BUS_T_UNK
// state, since the same bootstrap firmware is used for each.
#define POR_BUS_T_MCA 1 // MCA BUS */
#define POR_BUS_T_EISA 2 // EISA BUS */
#define POR_BUS_T_ISA 3 // ISA BUS */
// Values 4-7 Reserved
// Remaining bits are reserved
//----------------------
// porDiag1
//----------------------
#define POR_BAD_MAPPER 0x80 // HW failure on P.O.S.T: Chip mapper failed
// These two bits valid only for the IntelliPort-II
//
#define POR_BAD_UART1 0x01 // First 1400 bad
#define POR_BAD_UART2 0x02 // Second 1400 bad
//----------------------
// porDiag2
//----------------------
#define POR_DEBUG_PORT 0x80 // debug port was detected by the P.O.S.T
#define POR_DIAG_OK 0x00 // Indicates passage: Failure codes not yet
// available.
// Other bits undefined.
//----------------------
// porFlags
//----------------------
#define POR_CPU 0x03 // These bits indicate supposed CPU type
#define POR_CPU_8 0x01 // Board uses an 80188 (no such thing yet)
#define POR_CPU_6 0x02 // Board uses an 80186 (all existing products)
#define POR_CEX4 0x04 // If set, this is an ISA-CEX/4: An ISA-4 (asic)
// which is architected like an ISA-CEX connected
// to a (hitherto impossible) 4-port box.
#define POR_BOXES 0xf0 // Valid for IntelliPort-IIEX only: Map of Box
// sizes based on box I.D.
#define POR_BOX_16 0x10 // Set indicates 16-port, clear 8-port
//-------------------------------------
// LOADWARE and DOWNLOADING CODE
//-------------------------------------
/*
Loadware may be sent to the board in two ways:
1) It may be read from a (binary image) data file block by block as each block
is sent to the board. This is only possible when the initialization is
performed by code which can access your file system. This is most suitable
for diagnostics and appications which use the interface library directly.
2) It may be hard-coded into your source by including a .h file (typically
supplied by Computone), which declares a data array and initializes every
element. This achieves the same result as if an entire loadware file had
been read into the array.
This requires more data space in your program, but access to the file system
is not required. This method is more suited to driver code, which typically
is running at a level too low to access the file system directly.
At present, loadware can only be generated at Computone.
All Loadware begins with a header area which has a particular format. This
includes a magic number which identifies the file as being (purportedly)
loadware, CRC (for the loader), and version information.
*/
//-----------------------------------------------------------------------------
// Format of loadware block
//
// This is defined as a union so we can pass a pointer to one of these items
// and (if it is the first block) pick out the version information, etc.
//
// Otherwise, to deal with this as a simple character array
//------------------------------------------------------------------------------
#define LOADWARE_BLOCK_SIZE 512 // Number of bytes in each block of loadware
typedef union _loadHdrStr
{
unsigned char c[LOADWARE_BLOCK_SIZE]; // Valid for every block
struct // These fields are valid for only the first block of loadware.
{
unsigned char loadMagic; // Magic number: see below
unsigned char loadBlocksMore; // How many more blocks?
unsigned char loadCRC[2]; // Two CRC bytes: used by loader
unsigned char loadVersion; // Version number
unsigned char loadRevision; // Revision number
unsigned char loadSubRevision; // Sub-revision number
unsigned char loadSpares[9]; // Presently unused
unsigned char loadDates[32]; // Null-terminated string which can give
// date and time of compilation
} e;
} loadHdrStr, *loadHdrStrPtr;
//------------------------------------
// Defines for downloading code:
//------------------------------------
// The loadMagic field in the first block of the loadfile must be this, else the
// file is not valid.
//
#define MAGIC_LOADFILE 0x3c
// How do we know the load was successful? On completion of the load, the
// bootstrap firmware returns a code to indicate whether it thought the download
// was valid and intends to execute it. These are the only possible valid codes:
//
#define LOADWARE_OK 0xc3 // Download was ok
#define LOADWARE_BAD 0x5a // Download was bad (CRC error)
// Constants applicable to writing blocks of loadware:
// The first block of loadware might take 600 mS to load, in extreme cases.
// (Expandable board: worst case for sending startup messages to the LCD's).
// The 600mS figure is not really a calculation, but a conservative
// guess/guarantee. Usually this will be within 100 mS, like subsequent blocks.
//
#define MAX_DLOAD_START_TIME 1000 // 1000 mS
#define MAX_DLOAD_READ_TIME 100 // 100 mS
// Firmware should respond with status (see above) within this long of host
// having sent the final block.
//
#define MAX_DLOAD_ACK_TIME 100 // 100 mS, again!
//------------------------------------------------------
// MAXIMUM NUMBER OF PORTS PER BOARD:
// This is fixed for now (with the expandable), but may
// be expanding according to even newer products.
//------------------------------------------------------
//
#define ABS_MAX_BOXES 4 // Absolute most boxes per board
#define ABS_BIGGEST_BOX 16 // Absolute the most ports per box
#define ABS_MOST_PORTS (ABS_MAX_BOXES * ABS_BIGGEST_BOX)
#define I2_OUTSW(port, addr, count) outsw((port), (addr), (((count)+1)/2))
#define I2_OUTSB(port, addr, count) outsb((port), (addr), (((count)+1))&-2)
#define I2_INSW(port, addr, count) insw((port), (addr), (((count)+1)/2))
#define I2_INSB(port, addr, count) insb((port), (addr), (((count)+1))&-2)
#endif // I2HW_H

2214
drivers/staging/tty/ip2/i2lib.c
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351
drivers/staging/tty/ip2/i2lib.h
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@ -1,351 +0,0 @@
/*******************************************************************************
*
* (c) 1998 by Computone Corporation
*
********************************************************************************
*
*
* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
* serial I/O controllers.
*
* DESCRIPTION: Header file for high level library functions
*
*******************************************************************************/
#ifndef I2LIB_H
#define I2LIB_H 1
//------------------------------------------------------------------------------
// I2LIB.H
//
// IntelliPort-II and IntelliPort-IIEX
//
// Defines, structure definitions, and external declarations for i2lib.c
//------------------------------------------------------------------------------
//--------------------------------------
// Mandatory Includes:
//--------------------------------------
#include "ip2types.h"
#include "i2ellis.h"
#include "i2pack.h"
#include "i2cmd.h"
#include <linux/workqueue.h>
//------------------------------------------------------------------------------
// i2ChanStr -- Channel Structure:
// Used to track per-channel information for the library routines using standard
// loadware. Note also, a pointer to an array of these structures is patched
// into the i2eBordStr (see i2ellis.h)
//------------------------------------------------------------------------------
//
// If we make some limits on the maximum block sizes, we can avoid dealing with
// buffer wrap. The wrapping of the buffer is based on where the start of the
// packet is. Then there is always room for the packet contiguously.
//
// Maximum total length of an outgoing data or in-line command block. The limit
// of 36 on data is quite arbitrary and based more on DOS memory limitations
// than the board interface. However, for commands, the maximum packet length is
// MAX_CMD_PACK_SIZE, because the field size for the count is only a few bits
// (see I2PACK.H) in such packets. For data packets, the count field size is not
// the limiting factor. As of this writing, MAX_OBUF_BLOCK < MAX_CMD_PACK_SIZE,
// but be careful if wanting to modify either.
//
#define MAX_OBUF_BLOCK 36
// Another note on maximum block sizes: we are buffering packets here. Data is
// put into the buffer (if there is room) regardless of the credits from the
// board. The board sends new credits whenever it has removed from his buffers a
// number of characters equal to 80% of total buffer size. (Of course, the total
// buffer size is what is reported when the very first set of flow control
// status packets are received from the board. Therefore, to be robust, you must
// always fill the board to at least 80% of the current credit limit, else you
// might not give it enough to trigger a new report. These conditions are
// obtained here so long as the maximum output block size is less than 20% the
// size of the board's output buffers. This is true at present by "coincidence"
// or "infernal knowledge": the board's output buffers are at least 700 bytes
// long (20% = 140 bytes, at least). The 80% figure is "official", so the safest
// strategy might be to trap the first flow control report and guarantee that
// the effective maxObufBlock is the minimum of MAX_OBUF_BLOCK and 20% of first
// reported buffer credit.
//
#define MAX_CBUF_BLOCK 6 // Maximum total length of a bypass command block
#define IBUF_SIZE 512 // character capacity of input buffer per channel
#define OBUF_SIZE 1024// character capacity of output buffer per channel
#define CBUF_SIZE 10 // character capacity of output bypass buffer
typedef struct _i2ChanStr
{
// First, back-pointers so that given a pointer to this structure, you can
// determine the correct board and channel number to reference, (say, when
// issuing commands, etc. (Note, channel number is in infl.hd.i2sChannel.)
int port_index; // Index of port in channel structure array attached
// to board structure.
PTTY pTTY; // Pointer to tty structure for port (OS specific)
USHORT validity; // Indicates whether the given channel has been
// initialized, really exists (or is a missing
// channel, e.g. channel 9 on an 8-port box.)
i2eBordStrPtr pMyBord; // Back-pointer to this channel's board structure
int wopen; // waiting fer carrier
int throttled; // Set if upper layer can take no data
int flags; // Defined in tty.h
PWAITQ open_wait; // Pointer for OS sleep function.
PWAITQ close_wait; // Pointer for OS sleep function.
PWAITQ delta_msr_wait;// Pointer for OS sleep function.
PWAITQ dss_now_wait; // Pointer for OS sleep function.
struct timer_list BookmarkTimer; // Used by i2DrainOutput
wait_queue_head_t pBookmarkWait; // Used by i2DrainOutput
int BaudBase;
int BaudDivisor;
USHORT ClosingDelay;
USHORT ClosingWaitTime;
volatile
flowIn infl; // This structure is initialized as a completely
// formed flow-control command packet, and as such
// has the channel number, also the capacity and
// "as-of" data needed continuously.
USHORT sinceLastFlow; // Counts the number of characters read from input
// buffers, since the last time flow control info
// was sent.
USHORT whenSendFlow; // Determines when new flow control is to be sent to
// the board. Note unlike earlier manifestations of
// the driver, these packets can be sent from
// in-place.
USHORT channelNeeds; // Bit map of important things which must be done
// for this channel. (See bits below )
volatile
flowStat outfl; // Same type of structure is used to hold current
// flow control information used to control our
// output. "asof" is kept updated as data is sent,
// and "room" never goes to zero.
// The incoming ring buffer
// Unlike the outgoing buffers, this holds raw data, not packets. The two
// extra bytes are used to hold the byte-padding when there is room for an
// odd number of bytes before we must wrap.
//
UCHAR Ibuf[IBUF_SIZE + 2];
volatile
USHORT Ibuf_stuff; // Stuffing index
volatile
USHORT Ibuf_strip; // Stripping index
// The outgoing ring-buffer: Holds Data and command packets. N.B., even
// though these are in the channel structure, the channel is also written
// here, the easier to send it to the fifo when ready. HOWEVER, individual
// packets here are NOT padded to even length: the routines for writing
// blocks to the fifo will pad to even byte counts.
//
UCHAR Obuf[OBUF_SIZE+MAX_OBUF_BLOCK+4];
volatile
USHORT Obuf_stuff; // Stuffing index
volatile
USHORT Obuf_strip; // Stripping index
int Obuf_char_count;
// The outgoing bypass-command buffer. Unlike earlier manifestations, the
// flow control packets are sent directly from the structures. As above, the
// channel number is included in the packet, but they are NOT padded to even
// size.
//
UCHAR Cbuf[CBUF_SIZE+MAX_CBUF_BLOCK+2];
volatile
USHORT Cbuf_stuff; // Stuffing index
volatile
USHORT Cbuf_strip; // Stripping index
// The temporary buffer for the Linux tty driver PutChar entry.
//
UCHAR Pbuf[MAX_OBUF_BLOCK - sizeof (i2DataHeader)];
volatile
USHORT Pbuf_stuff; // Stuffing index
// The state of incoming data-set signals
//
USHORT dataSetIn; // Bit-mapped according to below. Also indicates
// whether a break has been detected since last
// inquiry.
// The state of outcoming data-set signals (as far as we can tell!)
//
USHORT dataSetOut; // Bit-mapped according to below.
// Most recent hot-key identifier detected
//
USHORT hotKeyIn; // Hot key as sent by the board, HOT_CLEAR indicates
// no hot key detected since last examined.
// Counter of outstanding requests for bookmarks
//
short bookMarks; // Number of outstanding bookmark requests, (+ive
// whenever a bookmark request if queued up, -ive
// whenever a bookmark is received).
// Misc options
//
USHORT channelOptions; // See below
// To store various incoming special packets
//
debugStat channelStatus;
cntStat channelRcount;
cntStat channelTcount;
failStat channelFail;
// To store the last values for line characteristics we sent to the board.
//
int speed;
int flush_flags;
void (*trace)(unsigned short,unsigned char,unsigned char,unsigned long,...);
/*
* Kernel counters for the 4 input interrupts
*/
struct async_icount icount;
/*
* Task queues for processing input packets from the board.
*/
struct work_struct tqueue_input;
struct work_struct tqueue_status;
struct work_struct tqueue_hangup;
rwlock_t Ibuf_spinlock;
rwlock_t Obuf_spinlock;
rwlock_t Cbuf_spinlock;
rwlock_t Pbuf_spinlock;
} i2ChanStr, *i2ChanStrPtr;
//---------------------------------------------------
// Manifests and bit-maps for elements in i2ChanStr
//---------------------------------------------------
//
// flush flags
//
#define STARTFL_FLAG 1
#define STOPFL_FLAG 2
// validity
//
#define CHANNEL_MAGIC_BITS 0xff00
#define CHANNEL_MAGIC 0x5300 // (validity & CHANNEL_MAGIC_BITS) ==
// CHANNEL_MAGIC --> structure good
#define CHANNEL_SUPPORT 0x0001 // Indicates channel is supported, exists,
// and passed P.O.S.T.
// channelNeeds
//
#define NEED_FLOW 1 // Indicates flow control has been queued
#define NEED_INLINE 2 // Indicates inline commands or data queued
#define NEED_BYPASS 4 // Indicates bypass commands queued
#define NEED_CREDIT 8 // Indicates would be sending except has not sufficient
// credit. The data is still in the channel structure,
// but the channel is not enqueued in the board
// structure again until there is a credit received from
// the board.
// dataSetIn (Also the bits for i2GetStatus return value)
//
#define I2_DCD 1
#define I2_CTS 2
#define I2_DSR 4
#define I2_RI 8
// dataSetOut (Also the bits for i2GetStatus return value)
//
#define I2_DTR 1
#define I2_RTS 2
// i2GetStatus() can optionally clear these bits
//
#define I2_BRK 0x10 // A break was detected
#define I2_PAR 0x20 // A parity error was received
#define I2_FRA 0x40 // A framing error was received
#define I2_OVR 0x80 // An overrun error was received
// i2GetStatus() automatically clears these bits */
//
#define I2_DDCD 0x100 // DCD changed from its former value
#define I2_DCTS 0x200 // CTS changed from its former value
#define I2_DDSR 0x400 // DSR changed from its former value
#define I2_DRI 0x800 // RI changed from its former value
// hotKeyIn
//
#define HOT_CLEAR 0x1322 // Indicates that no hot-key has been detected
// channelOptions
//
#define CO_NBLOCK_WRITE 1 // Writes don't block waiting for buffer. (Default
// is, they do wait.)
// fcmodes
//
#define I2_OUTFLOW_CTS 0x0001
#define I2_INFLOW_RTS 0x0002
#define I2_INFLOW_DSR 0x0004
#define I2_INFLOW_DTR 0x0008
#define I2_OUTFLOW_DSR 0x0010
#define I2_OUTFLOW_DTR 0x0020
#define I2_OUTFLOW_XON 0x0040
#define I2_OUTFLOW_XANY 0x0080
#define I2_INFLOW_XON 0x0100
#define I2_CRTSCTS (I2_OUTFLOW_CTS|I2_INFLOW_RTS)
#define I2_IXANY_MODE (I2_OUTFLOW_XON|I2_OUTFLOW_XANY)
//-------------------------------------------
// Macros used from user level like functions
//-------------------------------------------
// Macros to set and clear channel options
//
#define i2SetOption(pCh, option) pCh->channelOptions |= option
#define i2ClrOption(pCh, option) pCh->channelOptions &= ~option
// Macro to set fatal-error trap
//
#define i2SetFatalTrap(pB, routine) pB->i2eFatalTrap = routine
//--------------------------------------------
// Declarations and prototypes for i2lib.c
//--------------------------------------------
//
static int i2InitChannels(i2eBordStrPtr, int, i2ChanStrPtr);
static int i2QueueCommands(int, i2ChanStrPtr, int, int, cmdSyntaxPtr,...);
static int i2GetStatus(i2ChanStrPtr, int);
static int i2Input(i2ChanStrPtr);
static int i2InputFlush(i2ChanStrPtr);
static int i2Output(i2ChanStrPtr, const char *, int);
static int i2OutputFree(i2ChanStrPtr);
static int i2ServiceBoard(i2eBordStrPtr);
static void i2DrainOutput(i2ChanStrPtr, int);
#ifdef IP2DEBUG_TRACE
void ip2trace(unsigned short,unsigned char,unsigned char,unsigned long,...);
#else
#define ip2trace(a,b,c,d...) do {} while (0)
#endif
// Argument to i2QueueCommands
//
#define C_IN_LINE 1
#define C_BYPASS 0
#endif // I2LIB_H

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drivers/staging/tty/ip2/i2pack.h
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@ -1,364 +0,0 @@
/*******************************************************************************
*
* (c) 1998 by Computone Corporation
*
********************************************************************************
*
*
* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
* serial I/O controllers.
*
* DESCRIPTION: Definitions of the packets used to transfer data and commands
* Host <--> Board. Information provided here is only applicable
* when the standard loadware is active.
*
*******************************************************************************/
#ifndef I2PACK_H
#define I2PACK_H 1
//-----------------------------------------------
// Revision History:
//
// 10 October 1991 MAG First draft
// 24 February 1992 MAG Additions for 1.4.x loadware
// 11 March 1992 MAG New status packets
//
//-----------------------------------------------
//------------------------------------------------------------------------------
// Packet Formats:
//
// Information passes between the host and board through the FIFO in packets.
// These have headers which indicate the type of packet. Because the fifo data
// path may be 16-bits wide, the protocol is constrained such that each packet
// is always padded to an even byte count. (The lower-level interface routines
// -- i2ellis.c -- are designed to do this).
//
// The sender (be it host or board) must place some number of complete packets
// in the fifo, then place a message in the mailbox that packets are available.
// Placing such a message interrupts the "receiver" (be it board or host), who
// reads the mailbox message and determines that there are incoming packets
// ready. Since there are no partial packets, and the length of a packet is
// given in the header, the remainder of the packet can be read without checking
// for FIFO empty condition. The process is repeated, packet by packet, until
// the incoming FIFO is empty. Then the receiver uses the outbound mailbox to
// signal the board that it has read the data. Only then can the sender place
// additional data in the fifo.
//------------------------------------------------------------------------------
//
//------------------------------------------------
// Definition of Packet Header Area
//------------------------------------------------
//
// Caution: these only define header areas. In actual use the data runs off
// beyond the end of these structures.
//
// Since these structures are based on sequences of bytes which go to the board,
// there cannot be ANY padding between the elements.
#pragma pack(1)
//----------------------------
// DATA PACKETS
//----------------------------
typedef struct _i2DataHeader
{
unsigned char i2sChannel; /* The channel number: 0-255 */
// -- Bitfields are allocated LSB first --
// For incoming data, indicates whether this is an ordinary packet or a
// special one (e.g., hot key hit).
unsigned i2sId : 2 __attribute__ ((__packed__));
// For tagging data packets. There are flush commands which flush only data
// packets bearing a particular tag. (used in implementing IntelliView and
// IntelliPrint). THE TAG VALUE 0xf is RESERVED and must not be used (it has
// meaning internally to the loadware).
unsigned i2sTag : 4;
// These two bits determine the type of packet sent/received.
unsigned i2sType : 2;
// The count of data to follow: does not include the possible additional
// padding byte. MAXIMUM COUNT: 4094. The top four bits must be 0.
unsigned short i2sCount;
} i2DataHeader, *i2DataHeaderPtr;
// Structure is immediately followed by the data, proper.
//----------------------------
// NON-DATA PACKETS
//----------------------------
typedef struct _i2CmdHeader
{
unsigned char i2sChannel; // The channel number: 0-255 (Except where noted
// - see below
// Number of bytes of commands, status or whatever to follow
unsigned i2sCount : 6;
// These two bits determine the type of packet sent/received.
unsigned i2sType : 2;
} i2CmdHeader, *i2CmdHeaderPtr;
// Structure is immediately followed by the applicable data.
//---------------------------------------
// Flow Control Packets (Outbound)
//---------------------------------------
// One type of outbound command packet is so important that the entire structure
// is explicitly defined here. That is the flow-control packet. This is never
// sent by user-level code (as would be the commands to raise/lower DTR, for
// example). These are only sent by the library routines in response to reading
// incoming data into the buffers.
//
// The parameters inside the command block are maintained in place, then the
// block is sent at the appropriate time.
typedef struct _flowIn
{
i2CmdHeader hd; // Channel #, count, type (see above)
unsigned char fcmd; // The flow control command (37)
unsigned short asof; // As of byte number "asof" (LSB first!) I have room
// for "room" bytes
unsigned short room;
} flowIn, *flowInPtr;
//----------------------------------------
// (Incoming) Status Packets
//----------------------------------------
// Incoming packets which are non-data packets are status packets. In this case,
// the channel number in the header is unimportant. What follows are one or more
// sub-packets, the first word of which consists of the channel (first or low
// byte) and the status indicator (second or high byte), followed by possibly
// more data.
#define STAT_CTS_UP 0 /* CTS raised (no other bytes) */
#define STAT_CTS_DN 1 /* CTS dropped (no other bytes) */
#define STAT_DCD_UP 2 /* DCD raised (no other bytes) */
#define STAT_DCD_DN 3 /* DCD dropped (no other bytes) */
#define STAT_DSR_UP 4 /* DSR raised (no other bytes) */
#define STAT_DSR_DN 5 /* DSR dropped (no other bytes) */
#define STAT_RI_UP 6 /* RI raised (no other bytes) */
#define STAT_RI_DN 7 /* RI dropped (no other bytes) */
#define STAT_BRK_DET 8 /* BRK detect (no other bytes) */
#define STAT_FLOW 9 /* Flow control(-- more: see below */
#define STAT_BMARK 10 /* Bookmark (no other bytes)
* Bookmark is sent as a response to
* a command 60: request for bookmark
*/
#define STAT_STATUS 11 /* Special packet: see below */
#define STAT_TXCNT 12 /* Special packet: see below */
#define STAT_RXCNT 13 /* Special packet: see below */
#define STAT_BOXIDS 14 /* Special packet: see below */
#define STAT_HWFAIL 15 /* Special packet: see below */
#define STAT_MOD_ERROR 0xc0
#define STAT_MODEM 0xc0/* If status & STAT_MOD_ERROR:
* == STAT_MODEM, then this is a modem
* status packet, given in response to a
* CMD_DSS_NOW command.
* The low nibble has each data signal:
*/
#define STAT_MOD_DCD 0x8
#define STAT_MOD_RI 0x4
#define STAT_MOD_DSR 0x2
#define STAT_MOD_CTS 0x1
#define STAT_ERROR 0x80/* If status & STAT_MOD_ERROR
* == STAT_ERROR, then
* sort of error on the channel.
* The remaining seven bits indicate
* what sort of error it is.
*/
/* The low three bits indicate parity, framing, or overrun errors */
#define STAT_E_PARITY 4 /* Parity error */
#define STAT_E_FRAMING 2 /* Framing error */
#define STAT_E_OVERRUN 1 /* (uxart) overrun error */
//---------------------------------------
// STAT_FLOW packets
//---------------------------------------
typedef struct _flowStat
{
unsigned short asof;
unsigned short room;
}flowStat, *flowStatPtr;
// flowStat packets are received from the board to regulate the flow of outgoing
// data. A local copy of this structure is also kept to track the amount of
// credits used and credits remaining. "room" is the amount of space in the
// board's buffers, "as of" having received a certain byte number. When sending
// data to the fifo, you must calculate how much buffer space your packet will
// use. Add this to the current "asof" and subtract it from the current "room".
//
// The calculation for the board's buffer is given by CREDIT_USAGE, where size
// is the un-rounded count of either data characters or command characters.
// (Which is to say, the count rounded up, plus two).
#define CREDIT_USAGE(size) (((size) + 3) & ~1)
//---------------------------------------
// STAT_STATUS packets
//---------------------------------------
typedef struct _debugStat
{
unsigned char d_ccsr;
unsigned char d_txinh;
unsigned char d_stat1;
unsigned char d_stat2;
} debugStat, *debugStatPtr;
// debugStat packets are sent to the host in response to a CMD_GET_STATUS
// command. Each byte is bit-mapped as described below:
#define D_CCSR_XON 2 /* Has received XON, ready to transmit */
#define D_CCSR_XOFF 4 /* Has received XOFF, not transmitting */
#define D_CCSR_TXENAB 8 /* Transmitter is enabled */
#define D_CCSR_RXENAB 0x80 /* Receiver is enabled */
#define D_TXINH_BREAK 1 /* We are sending a break */
#define D_TXINH_EMPTY 2 /* No data to send */
#define D_TXINH_SUSP 4 /* Output suspended via command 57 */
#define D_TXINH_CMD 8 /* We are processing an in-line command */
#define D_TXINH_LCD 0x10 /* LCD diagnostics are running */
#define D_TXINH_PAUSE 0x20 /* We are processing a PAUSE command */
#define D_TXINH_DCD 0x40 /* DCD is low, preventing transmission */
#define D_TXINH_DSR 0x80 /* DSR is low, preventing transmission */
#define D_STAT1_TXEN 1 /* Transmit INTERRUPTS enabled */
#define D_STAT1_RXEN 2 /* Receiver INTERRUPTS enabled */
#define D_STAT1_MDEN 4 /* Modem (data set sigs) interrupts enabled */
#define D_STAT1_RLM 8 /* Remote loopback mode selected */
#define D_STAT1_LLM 0x10 /* Local internal loopback mode selected */
#define D_STAT1_CTS 0x20 /* CTS is low, preventing transmission */
#define D_STAT1_DTR 0x40 /* DTR is low, to stop remote transmission */
#define D_STAT1_RTS 0x80 /* RTS is low, to stop remote transmission */
#define D_STAT2_TXMT 1 /* Transmit buffers are all empty */
#define D_STAT2_RXMT 2 /* Receive buffers are all empty */
#define D_STAT2_RXINH 4 /* Loadware has tried to inhibit remote
* transmission: dropped DTR, sent XOFF,
* whatever...
*/
#define D_STAT2_RXFLO 8 /* Loadware can send no more data to host
* until it receives a flow-control packet
*/
//-----------------------------------------
// STAT_TXCNT and STAT_RXCNT packets
//----------------------------------------
typedef struct _cntStat
{
unsigned short cs_time; // (Assumes host is little-endian!)
unsigned short cs_count;
} cntStat, *cntStatPtr;
// These packets are sent in response to a CMD_GET_RXCNT or a CMD_GET_TXCNT
// bypass command. cs_time is a running 1 Millisecond counter which acts as a
// time stamp. cs_count is a running counter of data sent or received from the
// uxarts. (Not including data added by the chip itself, as with CRLF
// processing).
//------------------------------------------
// STAT_HWFAIL packets
//------------------------------------------
typedef struct _failStat
{
unsigned char fs_written;
unsigned char fs_read;
unsigned short fs_address;
} failStat, *failStatPtr;
// This packet is sent whenever the on-board diagnostic process detects an
// error. At startup, this process is dormant. The host can wake it up by
// issuing the bypass command CMD_HW_TEST. The process runs at low priority and
// performs continuous hardware verification; writing data to certain on-board
// registers, reading it back, and comparing. If it detects an error, this
// packet is sent to the host, and the process goes dormant again until the host
// sends another CMD_HW_TEST. It then continues with the next register to be
// tested.
//------------------------------------------------------------------------------
// Macros to deal with the headers more easily! Note that these are defined so
// they may be used as "left" as well as "right" expressions.
//------------------------------------------------------------------------------
// Given a pointer to the packet, reference the channel number
//
#define CHANNEL_OF(pP) ((i2DataHeaderPtr)(pP))->i2sChannel
// Given a pointer to the packet, reference the Packet type
//
#define PTYPE_OF(pP) ((i2DataHeaderPtr)(pP))->i2sType
// The possible types of packets
//
#define PTYPE_DATA 0 /* Host <--> Board */
#define PTYPE_BYPASS 1 /* Host ---> Board */
#define PTYPE_INLINE 2 /* Host ---> Board */
#define PTYPE_STATUS 2 /* Host <--- Board */
// Given a pointer to a Data packet, reference the Tag
//
#define TAG_OF(pP) ((i2DataHeaderPtr)(pP))->i2sTag
// Given a pointer to a Data packet, reference the data i.d.
//
#define ID_OF(pP) ((i2DataHeaderPtr)(pP))->i2sId
// The possible types of ID's
//
#define ID_ORDINARY_DATA 0
#define ID_HOT_KEY 1
// Given a pointer to a Data packet, reference the count
//
#define DATA_COUNT_OF(pP) ((i2DataHeaderPtr)(pP))->i2sCount
// Given a pointer to a Data packet, reference the beginning of data
//
#define DATA_OF(pP) &((unsigned char *)(pP))[4] // 4 = size of header
// Given a pointer to a Non-Data packet, reference the count
//
#define CMD_COUNT_OF(pP) ((i2CmdHeaderPtr)(pP))->i2sCount
#define MAX_CMD_PACK_SIZE 62 // Maximum size of such a count
// Given a pointer to a Non-Data packet, reference the beginning of data
//
#define CMD_OF(pP) &((unsigned char *)(pP))[2] // 2 = size of header
//--------------------------------
// MailBox Bits:
//--------------------------------
//--------------------------
// Outgoing (host to board)
//--------------------------
//
#define MB_OUT_STUFFED 0x80 // Host has placed output in fifo
#define MB_IN_STRIPPED 0x40 // Host has read in all input from fifo
//--------------------------
// Incoming (board to host)
//--------------------------
//
#define MB_IN_STUFFED 0x80 // Board has placed input in fifo
#define MB_OUT_STRIPPED 0x40 // Board has read all output from fifo
#define MB_FATAL_ERROR 0x20 // Board has encountered a fatal error
#pragma pack() // Reset padding to command-line default
#endif // I2PACK_H

107
drivers/staging/tty/ip2/ip2.h
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@ -1,107 +0,0 @@
/*******************************************************************************
*
* (c) 1998 by Computone Corporation
*
********************************************************************************
*
*
* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
* serial I/O controllers.
*
* DESCRIPTION: Driver constants for configuration and tuning
*
* NOTES:
*
*******************************************************************************/
#ifndef IP2_H
#define IP2_H
#include "ip2types.h"
#include "i2cmd.h"
/*************/
/* Constants */
/*************/
/* Device major numbers - since version 2.0.26. */
#define IP2_TTY_MAJOR 71
#define IP2_CALLOUT_MAJOR 72
#define IP2_IPL_MAJOR 73
/* Board configuration array.
* This array defines the hardware irq and address for up to IP2_MAX_BOARDS
* (4 supported per ip2_types.h) ISA board addresses and irqs MUST be specified,
* PCI and EISA boards are probed for and automagicly configed
* iff the addresses are set to 1 and 2 respectivily.
* 0x0100 - 0x03f0 == ISA
* 1 == PCI
* 2 == EISA
* 0 == (skip this board)
* This array defines the hardware addresses for them. Special
* addresses are EISA and PCI which go sniffing for boards.
* In a multiboard system the position in the array determines which port
* devices are assigned to each board:
* board 0 is assigned ttyF0.. to ttyF63,
* board 1 is assigned ttyF64 to ttyF127,
* board 2 is assigned ttyF128 to ttyF191,
* board 3 is assigned ttyF192 to ttyF255.
*
* In PCI and EISA bus systems each range is mapped to card in
* monotonically increasing slot number order, ISA position is as specified
* here.
* If the irqs are ALL set to 0,0,0,0 all boards operate in
* polled mode. For interrupt operation ISA boards require that the IRQ be
* specified, while PCI and EISA boards any nonzero entry
* will enable interrupts using the BIOS configured irq for the board.
* An invalid irq entry will default to polled mode for that card and print
* console warning.
* When the driver is loaded as a module these setting can be overridden on the
* modprobe command line or on an option line in /etc/modprobe.conf.
* If the driver is built-in the configuration must be
* set here for ISA cards and address set to 1 and 2 for PCI and EISA.
*
* Here is an example that shows most if not all possibe combinations:
*static ip2config_t ip2config =
*{
* {11,1,0,0}, // irqs
* { // Addresses
* 0x0308, // Board 0, ttyF0 - ttyF63// ISA card at io=0x308, irq=11
* 0x0001, // Board 1, ttyF64 - ttyF127//PCI card configured by BIOS
* 0x0000, // Board 2, ttyF128 - ttyF191// Slot skipped
* 0x0002 // Board 3, ttyF192 - ttyF255//EISA card configured by BIOS
* // but polled not irq driven
* }
*};
*/
/* this structure is zeroed out because the suggested method is to configure
* the driver as a module, set up the parameters with an options line in
* /etc/modprobe.conf and load with modprobe or kmod, the kernel
* module loader
*/
/* This structure is NOW always initialized when the driver is initialized.
* Compiled in defaults MUST be added to the io and irq arrays in
* ip2.c. Those values are configurable from insmod parameters in the
* case of modules or from command line parameters (ip2=io,irq) when
* compiled in.
*/
static ip2config_t ip2config =
{
{0,0,0,0}, // irqs
{ // Addresses
/* Do NOT set compile time defaults HERE! Use the arrays in
ip2.c! These WILL be overwritten! =mhw= */
0x0000, // Board 0, ttyF0 - ttyF63
0x0000, // Board 1, ttyF64 - ttyF127
0x0000, // Board 2, ttyF128 - ttyF191
0x0000 // Board 3, ttyF192 - ttyF255
}
};
#endif

35
drivers/staging/tty/ip2/ip2ioctl.h
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/*******************************************************************************
*
* (c) 1998 by Computone Corporation
*
********************************************************************************
*
*
* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
* serial I/O controllers.
*
* DESCRIPTION: Driver constants for configuration and tuning
*
* NOTES:
*
*******************************************************************************/
#ifndef IP2IOCTL_H
#define IP2IOCTL_H
//*************
//* Constants *
//*************
// High baud rates (if not defined elsewhere.
#ifndef B153600
# define B153600 0010005
#endif
#ifndef B307200
# define B307200 0010006
#endif
#ifndef B921600
# define B921600 0010007
#endif
#endif

3234
drivers/staging/tty/ip2/ip2main.c
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42
drivers/staging/tty/ip2/ip2trace.h
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//
union ip2breadcrumb
{
struct {
unsigned char port, cat, codes, label;
} __attribute__ ((packed)) hdr;
unsigned long value;
};
#define ITRC_NO_PORT 0xFF
#define CHANN (pCh->port_index)
#define ITRC_ERROR '!'
#define ITRC_INIT 'A'
#define ITRC_OPEN 'B'
#define ITRC_CLOSE 'C'
#define ITRC_DRAIN 'D'
#define ITRC_IOCTL 'E'
#define ITRC_FLUSH 'F'
#define ITRC_STATUS 'G'
#define ITRC_HANGUP 'H'
#define ITRC_INTR 'I'
#define ITRC_SFLOW 'J'
#define ITRC_SBCMD 'K'
#define ITRC_SICMD 'L'
#define ITRC_MODEM 'M'
#define ITRC_INPUT 'N'
#define ITRC_OUTPUT 'O'
#define ITRC_PUTC 'P'
#define ITRC_QUEUE 'Q'
#define ITRC_STFLW 'R'
#define ITRC_SFIFO 'S'
#define ITRC_VERIFY 'V'
#define ITRC_WRITE 'W'
#define ITRC_ENTER 0x00
#define ITRC_RETURN 0xFF
#define ITRC_QUEUE_ROOM 2
#define ITRC_QUEUE_CMD 6

57
drivers/staging/tty/ip2/ip2types.h
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/*******************************************************************************
*
* (c) 1998 by Computone Corporation
*
********************************************************************************
*
*
* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
* serial I/O controllers.
*
* DESCRIPTION: Driver constants and type definitions.
*
* NOTES:
*
*******************************************************************************/
#ifndef IP2TYPES_H
#define IP2TYPES_H
//*************
//* Constants *
//*************
// Define some limits for this driver. Ports per board is a hardware limitation
// that will not change. Current hardware limits this to 64 ports per board.
// Boards per driver is a self-imposed limit.
//
#define IP2_MAX_BOARDS 4
#define IP2_PORTS_PER_BOARD ABS_MOST_PORTS
#define IP2_MAX_PORTS (IP2_MAX_BOARDS*IP2_PORTS_PER_BOARD)
#define ISA 0
#define PCI 1
#define EISA 2
//********************
//* Type Definitions *
//********************
typedef struct tty_struct * PTTY;
typedef wait_queue_head_t PWAITQ;
typedef unsigned char UCHAR;
typedef unsigned int UINT;
typedef unsigned short USHORT;
typedef unsigned long ULONG;
typedef struct
{
short irq[IP2_MAX_BOARDS];
unsigned short addr[IP2_MAX_BOARDS];
int type[IP2_MAX_BOARDS];
#ifdef CONFIG_PCI
struct pci_dev *pci_dev[IP2_MAX_BOARDS];
#endif
} ip2config_t;
#endif

4507
drivers/staging/tty/istallion.c
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1560
drivers/staging/tty/riscom8.c
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91
drivers/staging/tty/riscom8.h
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/*
* linux/drivers/char/riscom8.h -- RISCom/8 multiport serial driver.
*
* Copyright (C) 1994-1996 Dmitry Gorodchanin (pgmdsg@ibi.com)
*
* This code is loosely based on the Linux serial driver, written by
* Linus Torvalds, Theodore T'so and others. The RISCom/8 card
* programming info was obtained from various drivers for other OSes
* (FreeBSD, ISC, etc), but no source code from those drivers were
* directly included in this driver.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __LINUX_RISCOM8_H
#define __LINUX_RISCOM8_H
#include <linux/serial.h>
#ifdef __KERNEL__
#define RC_NBOARD 4
/* NOTE: RISCom decoder recognizes 16 addresses... */
#define RC_NPORT 8
#define RC_BOARD(line) (((line) >> 3) & 0x07)
#define RC_PORT(line) ((line) & (RC_NPORT - 1))
/* Ticks per sec. Used for setting receiver timeout and break length */
#define RISCOM_TPS 4000
/* Yeah, after heavy testing I decided it must be 6.
* Sure, You can change it if needed.
*/
#define RISCOM_RXFIFO 6 /* Max. receiver FIFO size (1-8) */
#define RISCOM8_MAGIC 0x0907
#define RC_IOBASE1 0x220
#define RC_IOBASE2 0x240
#define RC_IOBASE3 0x250
#define RC_IOBASE4 0x260
struct riscom_board {
unsigned long flags;
unsigned short base;
unsigned char irq;
signed char count;
unsigned char DTR;
};
#define RC_BOARD_PRESENT 0x00000001
#define RC_BOARD_ACTIVE 0x00000002
struct riscom_port {
int magic;
struct tty_port port;
int baud_base;
int timeout;
int custom_divisor;
int xmit_head;
int xmit_tail;
int xmit_cnt;
short wakeup_chars;
short break_length;
unsigned char mark_mask;
unsigned char IER;
unsigned char MSVR;
unsigned char COR2;
#ifdef RC_REPORT_OVERRUN
unsigned long overrun;
#endif
#ifdef RC_REPORT_FIFO
unsigned long hits[10];
#endif
};
#endif /* __KERNEL__ */
#endif /* __LINUX_RISCOM8_H */

254
drivers/staging/tty/riscom8_reg.h
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/*
* linux/drivers/char/riscom8_reg.h -- RISCom/8 multiport serial driver.
*/
/*
* Definitions for RISCom/8 Async Mux card by SDL Communications, Inc.
*/
/*
* Address mapping between Cirrus Logic CD180 chip internal registers
* and ISA port addresses:
*
* CL-CD180 A6 A5 A4 A3 A2 A1 A0
* ISA A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
*/
#define RC_TO_ISA(r) ((((r)&0x07)<<1) | (((r)&~0x07)<<7))
/* RISCom/8 On-Board Registers (assuming address translation) */
#define RC_RI 0x100 /* Ring Indicator Register (R/O) */
#define RC_DTR 0x100 /* DTR Register (W/O) */
#define RC_BSR 0x101 /* Board Status Register (R/O) */
#define RC_CTOUT 0x101 /* Clear Timeout (W/O) */
/* Board Status Register */
#define RC_BSR_TOUT 0x08 /* Hardware Timeout */
#define RC_BSR_RINT 0x04 /* Receiver Interrupt */
#define RC_BSR_TINT 0x02 /* Transmitter Interrupt */
#define RC_BSR_MINT 0x01 /* Modem Ctl Interrupt */
/* On-board oscillator frequency (in Hz) */
#define RC_OSCFREQ 9830400
/* Values of choice for Interrupt ACKs */
#define RC_ACK_MINT 0x81 /* goes to PILR1 */
#define RC_ACK_RINT 0x82 /* goes to PILR3 */
#define RC_ACK_TINT 0x84 /* goes to PILR2 */
/* Chip ID (sorry, only one chip now) */
#define RC_ID 0x10
/* Definitions for Cirrus Logic CL-CD180 8-port async mux chip */
#define CD180_NCH 8 /* Total number of channels */
#define CD180_TPC 16 /* Ticks per character */
#define CD180_NFIFO 8 /* TX FIFO size */
/* Global registers */
#define CD180_GIVR 0x40 /* Global Interrupt Vector Register */
#define CD180_GICR 0x41 /* Global Interrupting Channel Register */
#define CD180_PILR1 0x61 /* Priority Interrupt Level Register 1 */
#define CD180_PILR2 0x62 /* Priority Interrupt Level Register 2 */
#define CD180_PILR3 0x63 /* Priority Interrupt Level Register 3 */
#define CD180_CAR 0x64 /* Channel Access Register */
#define CD180_GFRCR 0x6b /* Global Firmware Revision Code Register */
#define CD180_PPRH 0x70 /* Prescaler Period Register High */
#define CD180_PPRL 0x71 /* Prescaler Period Register Low */
#define CD180_RDR 0x78 /* Receiver Data Register */
#define CD180_RCSR 0x7a /* Receiver Character Status Register */
#define CD180_TDR 0x7b /* Transmit Data Register */
#define CD180_EOIR 0x7f /* End of Interrupt Register */
/* Channel Registers */
#define CD180_CCR 0x01 /* Channel Command Register */
#define CD180_IER 0x02 /* Interrupt Enable Register */
#define CD180_COR1 0x03 /* Channel Option Register 1 */
#define CD180_COR2 0x04 /* Channel Option Register 2 */
#define CD180_COR3 0x05 /* Channel Option Register 3 */
#define CD180_CCSR 0x06 /* Channel Control Status Register */
#define CD180_RDCR 0x07 /* Receive Data Count Register */
#define CD180_SCHR1 0x09 /* Special Character Register 1 */
#define CD180_SCHR2 0x0a /* Special Character Register 2 */
#define CD180_SCHR3 0x0b /* Special Character Register 3 */
#define CD180_SCHR4 0x0c /* Special Character Register 4 */
#define CD180_MCOR1 0x10 /* Modem Change Option 1 Register */
#define CD180_MCOR2 0x11 /* Modem Change Option 2 Register */
#define CD180_MCR 0x12 /* Modem Change Register */
#define CD180_RTPR 0x18 /* Receive Timeout Period Register */
#define CD180_MSVR 0x28 /* Modem Signal Value Register */
#define CD180_RBPRH 0x31 /* Receive Baud Rate Period Register High */
#define CD180_RBPRL 0x32 /* Receive Baud Rate Period Register Low */
#define CD180_TBPRH 0x39 /* Transmit Baud Rate Period Register High */
#define CD180_TBPRL 0x3a /* Transmit Baud Rate Period Register Low */
/* Global Interrupt Vector Register (R/W) */
#define GIVR_ITMASK 0x07 /* Interrupt type mask */
#define GIVR_IT_MODEM 0x01 /* Modem Signal Change Interrupt */
#define GIVR_IT_TX 0x02 /* Transmit Data Interrupt */
#define GIVR_IT_RCV 0x03 /* Receive Good Data Interrupt */
#define GIVR_IT_REXC 0x07 /* Receive Exception Interrupt */
/* Global Interrupt Channel Register (R/W) */
#define GICR_CHAN 0x1c /* Channel Number Mask */
#define GICR_CHAN_OFF 2 /* Channel Number Offset */
/* Channel Address Register (R/W) */
#define CAR_CHAN 0x07 /* Channel Number Mask */
#define CAR_A7 0x08 /* A7 Address Extension (unused) */
/* Receive Character Status Register (R/O) */
#define RCSR_TOUT 0x80 /* Rx Timeout */
#define RCSR_SCDET 0x70 /* Special Character Detected Mask */
#define RCSR_NO_SC 0x00 /* No Special Characters Detected */
#define RCSR_SC_1 0x10 /* Special Char 1 (or 1 & 3) Detected */
#define RCSR_SC_2 0x20 /* Special Char 2 (or 2 & 4) Detected */
#define RCSR_SC_3 0x30 /* Special Char 3 Detected */
#define RCSR_SC_4 0x40 /* Special Char 4 Detected */
#define RCSR_BREAK 0x08 /* Break has been detected */
#define RCSR_PE 0x04 /* Parity Error */
#define RCSR_FE 0x02 /* Frame Error */
#define RCSR_OE 0x01 /* Overrun Error */
/* Channel Command Register (R/W) (commands in groups can be OR-ed) */
#define CCR_HARDRESET 0x81 /* Reset the chip */
#define CCR_SOFTRESET 0x80 /* Soft Channel Reset */
#define CCR_CORCHG1 0x42 /* Channel Option Register 1 Changed */
#define CCR_CORCHG2 0x44 /* Channel Option Register 2 Changed */
#define CCR_CORCHG3 0x48 /* Channel Option Register 3 Changed */
#define CCR_SSCH1 0x21 /* Send Special Character 1 */
#define CCR_SSCH2 0x22 /* Send Special Character 2 */
#define CCR_SSCH3 0x23 /* Send Special Character 3 */
#define CCR_SSCH4 0x24 /* Send Special Character 4 */
#define CCR_TXEN 0x18 /* Enable Transmitter */
#define CCR_RXEN 0x12 /* Enable Receiver */
#define CCR_TXDIS 0x14 /* Disable Transmitter */
#define CCR_RXDIS 0x11 /* Disable Receiver */
/* Interrupt Enable Register (R/W) */
#define IER_DSR 0x80 /* Enable interrupt on DSR change */
#define IER_CD 0x40 /* Enable interrupt on CD change */
#define IER_CTS 0x20 /* Enable interrupt on CTS change */
#define IER_RXD 0x10 /* Enable interrupt on Receive Data */
#define IER_RXSC 0x08 /* Enable interrupt on Receive Spec. Char */
#define IER_TXRDY 0x04 /* Enable interrupt on TX FIFO empty */
#define IER_TXEMPTY 0x02 /* Enable interrupt on TX completely empty */
#define IER_RET 0x01 /* Enable interrupt on RX Exc. Timeout */
/* Channel Option Register 1 (R/W) */
#define COR1_ODDP 0x80 /* Odd Parity */
#define COR1_PARMODE 0x60 /* Parity Mode mask */
#define COR1_NOPAR 0x00 /* No Parity */
#define COR1_FORCEPAR 0x20 /* Force Parity */
#define COR1_NORMPAR 0x40 /* Normal Parity */
#define COR1_IGNORE 0x10 /* Ignore Parity on RX */
#define COR1_STOPBITS 0x0c /* Number of Stop Bits */
#define COR1_1SB 0x00 /* 1 Stop Bit */
#define COR1_15SB 0x04 /* 1.5 Stop Bits */
#define COR1_2SB 0x08 /* 2 Stop Bits */
#define COR1_CHARLEN 0x03 /* Character Length */
#define COR1_5BITS 0x00 /* 5 bits */
#define COR1_6BITS 0x01 /* 6 bits */
#define COR1_7BITS 0x02 /* 7 bits */
#define COR1_8BITS 0x03 /* 8 bits */
/* Channel Option Register 2 (R/W) */
#define COR2_IXM 0x80 /* Implied XON mode */
#define COR2_TXIBE 0x40 /* Enable In-Band (XON/XOFF) Flow Control */
#define COR2_ETC 0x20 /* Embedded Tx Commands Enable */
#define COR2_LLM 0x10 /* Local Loopback Mode */
#define COR2_RLM 0x08 /* Remote Loopback Mode */
#define COR2_RTSAO 0x04 /* RTS Automatic Output Enable */
#define COR2_CTSAE 0x02 /* CTS Automatic Enable */
#define COR2_DSRAE 0x01 /* DSR Automatic Enable */
/* Channel Option Register 3 (R/W) */
#define COR3_XONCH 0x80 /* XON is a pair of characters (1 & 3) */
#define COR3_XOFFCH 0x40 /* XOFF is a pair of characters (2 & 4) */
#define COR3_FCT 0x20 /* Flow-Control Transparency Mode */
#define COR3_SCDE 0x10 /* Special Character Detection Enable */
#define COR3_RXTH 0x0f /* RX FIFO Threshold value (1-8) */
/* Channel Control Status Register (R/O) */
#define CCSR_RXEN 0x80 /* Receiver Enabled */
#define CCSR_RXFLOFF 0x40 /* Receive Flow Off (XOFF was sent) */
#define CCSR_RXFLON 0x20 /* Receive Flow On (XON was sent) */
#define CCSR_TXEN 0x08 /* Transmitter Enabled */
#define CCSR_TXFLOFF 0x04 /* Transmit Flow Off (got XOFF) */
#define CCSR_TXFLON 0x02 /* Transmit Flow On (got XON) */
/* Modem Change Option Register 1 (R/W) */
#define MCOR1_DSRZD 0x80 /* Detect 0->1 transition of DSR */
#define MCOR1_CDZD 0x40 /* Detect 0->1 transition of CD */
#define MCOR1_CTSZD 0x20 /* Detect 0->1 transition of CTS */
#define MCOR1_DTRTH 0x0f /* Auto DTR flow control Threshold (1-8) */
#define MCOR1_NODTRFC 0x0 /* Automatic DTR flow control disabled */
/* Modem Change Option Register 2 (R/W) */
#define MCOR2_DSROD 0x80 /* Detect 1->0 transition of DSR */
#define MCOR2_CDOD 0x40 /* Detect 1->0 transition of CD */
#define MCOR2_CTSOD 0x20 /* Detect 1->0 transition of CTS */
/* Modem Change Register (R/W) */
#define MCR_DSRCHG 0x80 /* DSR Changed */
#define MCR_CDCHG 0x40 /* CD Changed */
#define MCR_CTSCHG 0x20 /* CTS Changed */
/* Modem Signal Value Register (R/W) */
#define MSVR_DSR 0x80 /* Current state of DSR input */
#define MSVR_CD 0x40 /* Current state of CD input */
#define MSVR_CTS 0x20 /* Current state of CTS input */
#define MSVR_DTR 0x02 /* Current state of DTR output */
#define MSVR_RTS 0x01 /* Current state of RTS output */
/* Escape characters */
#define CD180_C_ESC 0x00 /* Escape character */
#define CD180_C_SBRK 0x81 /* Start sending BREAK */
#define CD180_C_DELAY 0x82 /* Delay output */
#define CD180_C_EBRK 0x83 /* Stop sending BREAK */

2489
drivers/staging/tty/serial167.c
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2368
drivers/staging/tty/specialix.c
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140
drivers/staging/tty/specialix_io8.h
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@ -1,140 +0,0 @@
/*
* linux/drivers/char/specialix_io8.h --
* Specialix IO8+ multiport serial driver.
*
* Copyright (C) 1997 Roger Wolff (R.E.Wolff@BitWizard.nl)
* Copyright (C) 1994-1996 Dmitry Gorodchanin (pgmdsg@ibi.com)
*
*
* Specialix pays for the development and support of this driver.
* Please DO contact io8-linux@specialix.co.uk if you require
* support.
*
* This driver was developed in the BitWizard linux device
* driver service. If you require a linux device driver for your
* product, please contact devices@BitWizard.nl for a quote.
*
* This code is firmly based on the riscom/8 serial driver,
* written by Dmitry Gorodchanin. The specialix IO8+ card
* programming information was obtained from the CL-CD1865 Data
* Book, and Specialix document number 6200059: IO8+ Hardware
* Functional Specification.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this program; if not, write to the Free
* Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139,
* USA.
* */
#ifndef __LINUX_SPECIALIX_H
#define __LINUX_SPECIALIX_H
#include <linux/serial.h>
#ifdef __KERNEL__
/* You can have max 4 ISA cards in one PC, and I recommend not much
more than a few PCI versions of the card. */
#define SX_NBOARD 8
/* NOTE: Specialix decoder recognizes 4 addresses, but only two are used.... */
#define SX_IO_SPACE 4
/* The PCI version decodes 8 addresses, but still only 2 are used. */
#define SX_PCI_IO_SPACE 8
/* eight ports per board. */
#define SX_NPORT 8
#define SX_BOARD(line) ((line) / SX_NPORT)
#define SX_PORT(line) ((line) & (SX_NPORT - 1))
#define SX_DATA_REG 0 /* Base+0 : Data register */
#define SX_ADDR_REG 1 /* base+1 : Address register. */
#define MHz *1000000 /* I'm ashamed of myself. */
/* On-board oscillator frequency */
#define SX_OSCFREQ (25 MHz/2)
/* There is a 25MHz crystal on the board, but the chip is in /2 mode */
/* Ticks per sec. Used for setting receiver timeout and break length */
#define SPECIALIX_TPS 4000
/* Yeah, after heavy testing I decided it must be 6.
* Sure, You can change it if needed.
*/
#define SPECIALIX_RXFIFO 6 /* Max. receiver FIFO size (1-8) */
#define SPECIALIX_MAGIC 0x0907
#define SX_CCR_TIMEOUT 10000 /* CCR timeout. You may need to wait up to
10 milliseconds before the internal
processor is available again after
you give it a command */
#define SX_IOBASE1 0x100
#define SX_IOBASE2 0x180
#define SX_IOBASE3 0x250
#define SX_IOBASE4 0x260
struct specialix_board {
unsigned long flags;
unsigned short base;
unsigned char irq;
//signed char count;
int count;
unsigned char DTR;
int reg;
spinlock_t lock;
};
#define SX_BOARD_PRESENT 0x00000001
#define SX_BOARD_ACTIVE 0x00000002
#define SX_BOARD_IS_PCI 0x00000004
struct specialix_port {
int magic;
struct tty_port port;
int baud_base;
int flags;
int timeout;
unsigned char * xmit_buf;
int custom_divisor;
int xmit_head;
int xmit_tail;
int xmit_cnt;
short wakeup_chars;
short break_length;
unsigned char mark_mask;
unsigned char IER;
unsigned char MSVR;
unsigned char COR2;
unsigned long overrun;
unsigned long hits[10];
spinlock_t lock;
};
#endif /* __KERNEL__ */
#endif /* __LINUX_SPECIALIX_H */

4651
drivers/staging/tty/stallion.c
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