MIPS: Netlogic: SMP wakeup code update
Update for core intialization code. Initialize status register after receiving NMI for CPU wakeup. Add the low level L1D flush code before enabling threads in core. Also convert the ehb to _ehb so that it works under more GCC versions. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3755/ Patchwork: https://patchwork.linux-mips.org/patch/4095/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -47,7 +47,9 @@
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#define CPU_BLOCKID_MAP 10
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#define LSU_DEFEATURE 0x304
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#define LSU_CERRLOG_REGID 0x09
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#define LSU_DEBUG_ADDR 0x305
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#define LSU_DEBUG_DATA0 0x306
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#define LSU_CERRLOG_REGID 0x309
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#define SCHED_DEFEATURE 0x700
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/* Offsets of interest from the 'MAP' Block */
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@ -80,6 +80,38 @@
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* This is the code that will be copied to the reset entry point for
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* XLR and XLP. The XLP cores start here when they are woken up. This
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* is also the NMI entry point.
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*/
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.macro xlp_flush_l1_dcache
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li t0, LSU_DEBUG_DATA0
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li t1, LSU_DEBUG_ADDR
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li t2, 0 /* index */
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li t3, 0x1000 /* loop count */
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1:
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sll v0, t2, 5
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mtcr zero, t0
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ori v1, v0, 0x3 /* way0 | write_enable | write_active */
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mtcr v1, t1
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2:
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mfcr v1, t1
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andi v1, 0x1 /* wait for write_active == 0 */
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bnez v1, 2b
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nop
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mtcr zero, t0
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ori v1, v0, 0x7 /* way1 | write_enable | write_active */
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mtcr v1, t1
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3:
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mfcr v1, t1
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andi v1, 0x1 /* wait for write_active == 0 */
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bnez v1, 3b
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nop
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addi t2, 1
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bne t3, t2, 1b
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nop
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.endm
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/*
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* The cores can come start when they are woken up. This is also the NMI
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* entry, so check that first.
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*
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* The data corresponding to reset/NMI is stored at RESET_DATA_PHYS
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* location, this will have the thread mask (used when core is woken up)
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@ -138,6 +170,8 @@ FEXPORT(nlm_reset_entry)
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* a core.
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*/
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EXPORT(nlm_boot_siblings)
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/* core L1D flush before enable threads */
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xlp_flush_l1_dcache
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/* Enable hw threads by writing to MAP_THREADMODE of the core */
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li t0, CKSEG1ADDR(RESET_DATA_PHYS)
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lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
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@ -164,16 +198,13 @@ EXPORT(nlm_boot_siblings)
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li t0, MMU_SETUP
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li t1, 0
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mtcr t1, t0
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ehb
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_ehb
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2: beqz v0, 4f /* boot cpu (cpuid == 0)? */
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nop
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/* setup status reg */
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mfc0 t1, CP0_STATUS
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li t0, ST0_BEV
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or t1, t0
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xor t1, t0
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move t1, zero
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#ifdef CONFIG_64BIT
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ori t1, ST0_KX
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#endif
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@ -220,6 +251,12 @@ FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */
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__CPUINIT
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NESTED(nlm_boot_secondary_cpus, 16, sp)
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/* Initialize CP0 Status */
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move t1, zero
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#ifdef CONFIG_64BIT
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ori t1, ST0_KX
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#endif
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mtc0 t1, CP0_STATUS
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PTR_LA t1, nlm_next_sp
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PTR_L sp, 0(t1)
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PTR_LA t1, nlm_next_gp
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