dt-bindings: pci: tegra: Add Tegra210 support
Add support for the PCI host controller found on Tegra210 SoCs. It is very similar to the variant found on Tegra124, with a couple of small differences regarding the power supplies. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
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@ -110,6 +110,20 @@ Power supplies for Tegra124:
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- avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must
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supply 1.05 V.
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Power supplies for Tegra210:
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- Required:
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- avdd-pll-uerefe-supply: Power supply for PLLE (shared with USB3). Must
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supply 1.05 V.
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- hvddio-pex-supply: High-voltage supply for PCIe I/O and PCIe output
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clocks. Must supply 1.8 V.
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- dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
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- dvdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
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supply 1.05 V.
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- hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
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Must supply 3.3 V.
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- vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
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supply 1.8 V.
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Root ports are defined as subnodes of the PCIe controller node.
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Required properties:
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@ -436,3 +450,99 @@ Board DTS:
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status = "okay";
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};
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};
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Tegra210:
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---------
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SoC DTSI:
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pcie-controller@01003000 {
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compatible = "nvidia,tegra210-pcie";
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device_type = "pci";
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reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
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0x0 0x01003800 0x0 0x00000800 /* AFI registers */
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0x0 0x02000000 0x0 0x10000000>; /* configuration space */
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reg-names = "pads", "afi", "cs";
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
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0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
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0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
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0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
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0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
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clocks = <&tegra_car TEGRA210_CLK_PCIE>,
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<&tegra_car TEGRA210_CLK_AFI>,
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<&tegra_car TEGRA210_CLK_PLL_E>,
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<&tegra_car TEGRA210_CLK_CML0>;
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clock-names = "pex", "afi", "pll_e", "cml";
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resets = <&tegra_car 70>,
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<&tegra_car 72>,
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<&tegra_car 74>;
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reset-names = "pex", "afi", "pcie_x";
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status = "disabled";
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pci@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
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reg = <0x000800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <4>;
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};
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pci@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
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reg = <0x001000 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <1>;
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};
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};
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Board DTS:
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pcie-controller@01003000 {
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status = "okay";
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avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
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hvddio-pex-supply = <&vdd_1v8>;
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dvddio-pex-supply = <&vdd_pex_1v05>;
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dvdd-pex-pll-supply = <&vdd_pex_1v05>;
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hvdd-pex-pll-e-supply = <&vdd_1v8>;
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vddio-pex-ctl-supply = <&vdd_1v8>;
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pci@1,0 {
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phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
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<&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
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<&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
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<&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
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phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
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status = "okay";
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};
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pci@2,0 {
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phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
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phy-names = "pcie-0";
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status = "okay";
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};
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};
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