ixgbe: Fix backplane flow control autoneg
Backplane flow control autonegotiation is currently broken for ixgbe devices. This patch fixes the flow control issues with clause 37 autoneg. Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
84f62d4b58
commit
539e5f02c5
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@ -425,7 +425,7 @@ static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
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#endif /* CONFIG_DCB */
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#endif /* CONFIG_DCB */
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default:
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default:
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hw_dbg(hw, "Flow control param set incorrectly\n");
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hw_dbg(hw, "Flow control param set incorrectly\n");
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ret_val = -IXGBE_ERR_CONFIG;
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ret_val = IXGBE_ERR_CONFIG;
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goto out;
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goto out;
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break;
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break;
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}
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}
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@ -1663,7 +1663,7 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
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#endif /* CONFIG_DCB */
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#endif /* CONFIG_DCB */
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default:
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default:
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hw_dbg(hw, "Flow control param set incorrectly\n");
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hw_dbg(hw, "Flow control param set incorrectly\n");
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ret_val = -IXGBE_ERR_CONFIG;
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ret_val = IXGBE_ERR_CONFIG;
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goto out;
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goto out;
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break;
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break;
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}
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}
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@ -1734,40 +1734,63 @@ s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
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s32 ret_val = 0;
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s32 ret_val = 0;
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ixgbe_link_speed speed;
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ixgbe_link_speed speed;
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u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
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u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
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u32 links2, anlp1_reg, autoc_reg, links;
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bool link_up;
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bool link_up;
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/*
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/*
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* AN should have completed when the cable was plugged in.
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* AN should have completed when the cable was plugged in.
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* Look for reasons to bail out. Bail out if:
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* Look for reasons to bail out. Bail out if:
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* - FC autoneg is disabled, or if
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* - FC autoneg is disabled, or if
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* - we don't have multispeed fiber, or if
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* - link is not up.
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* - we're not running at 1G, or if
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* - link is not up, or if
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* - link is up but AN did not complete, or if
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* - link is up and AN completed but timed out
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*
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*
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* Since we're being called from an LSC, link is already know to be up.
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* Since we're being called from an LSC, link is already known to be up.
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* So use link_up_wait_to_complete=false.
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* So use link_up_wait_to_complete=false.
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*/
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*/
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hw->mac.ops.check_link(hw, &speed, &link_up, false);
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hw->mac.ops.check_link(hw, &speed, &link_up, false);
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linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
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if (hw->fc.disable_fc_autoneg ||
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if (hw->fc.disable_fc_autoneg || (!link_up)) {
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!hw->phy.multispeed_fiber ||
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hw->fc.fc_was_autonegged = false;
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(speed != IXGBE_LINK_SPEED_1GB_FULL) ||
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hw->fc.current_mode = hw->fc.requested_mode;
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!link_up ||
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goto out;
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((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
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}
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/*
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* On backplane, bail out if
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* - backplane autoneg was not completed, or if
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* - link partner is not AN enabled
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*/
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if (hw->phy.media_type == ixgbe_media_type_backplane) {
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links = IXGBE_READ_REG(hw, IXGBE_LINKS);
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links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
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if (((links & IXGBE_LINKS_KX_AN_COMP) == 0) ||
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((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)) {
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hw->fc.fc_was_autonegged = false;
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hw->fc.current_mode = hw->fc.requested_mode;
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goto out;
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}
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}
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/*
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* On multispeed fiber at 1g, bail out if
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* - link is up but AN did not complete, or if
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* - link is up and AN completed but timed out
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*/
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if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL)) {
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linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
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if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
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((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
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((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
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hw->fc.fc_was_autonegged = false;
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hw->fc.fc_was_autonegged = false;
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hw->fc.current_mode = hw->fc.requested_mode;
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hw->fc.current_mode = hw->fc.requested_mode;
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hw_dbg(hw, "Autoneg FC was skipped.\n");
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goto out;
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goto out;
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}
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}
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}
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/*
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/*
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* Read the AN advertisement and LP ability registers and resolve
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* Read the AN advertisement and LP ability registers and resolve
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* local flow control settings accordingly
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* local flow control settings accordingly
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*/
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*/
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if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
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(hw->phy.media_type != ixgbe_media_type_backplane)) {
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pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
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pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
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pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
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pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
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if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
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if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
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@ -1784,7 +1807,7 @@ s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
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hw_dbg(hw, "Flow Control = FULL.\n");
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hw_dbg(hw, "Flow Control = FULL.\n");
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} else {
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} else {
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hw->fc.current_mode = ixgbe_fc_rx_pause;
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hw->fc.current_mode = ixgbe_fc_rx_pause;
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hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
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hw_dbg(hw, "Flow Control=RX PAUSE only\n");
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}
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}
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} else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
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} else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
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(pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
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(pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
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@ -1802,7 +1825,49 @@ s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
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hw->fc.current_mode = ixgbe_fc_none;
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hw->fc.current_mode = ixgbe_fc_none;
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hw_dbg(hw, "Flow Control = NONE.\n");
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hw_dbg(hw, "Flow Control = NONE.\n");
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}
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}
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}
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if (hw->phy.media_type == ixgbe_media_type_backplane) {
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/*
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* Read the 10g AN autoc and LP ability registers and resolve
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* local flow control settings accordingly
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*/
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autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
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anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
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if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
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(anlp1_reg & IXGBE_ANLP1_SYM_PAUSE)) {
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/*
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* Now we need to check if the user selected Rx ONLY
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* of pause frames. In this case, we had to advertise
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* FULL flow control because we could not advertise RX
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* ONLY. Hence, we must now check to see if we need to
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* turn OFF the TRANSMISSION of PAUSE frames.
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*/
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if (hw->fc.requested_mode == ixgbe_fc_full) {
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hw->fc.current_mode = ixgbe_fc_full;
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hw_dbg(hw, "Flow Control = FULL.\n");
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} else {
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hw->fc.current_mode = ixgbe_fc_rx_pause;
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hw_dbg(hw, "Flow Control=RX PAUSE only\n");
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}
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} else if (!(autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
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(autoc_reg & IXGBE_AUTOC_ASM_PAUSE) &&
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(anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) &&
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(anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) {
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hw->fc.current_mode = ixgbe_fc_tx_pause;
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hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
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} else if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
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(autoc_reg & IXGBE_AUTOC_ASM_PAUSE) &&
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!(anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) &&
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(anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) {
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hw->fc.current_mode = ixgbe_fc_rx_pause;
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hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
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} else {
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hw->fc.current_mode = ixgbe_fc_none;
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hw_dbg(hw, "Flow Control = NONE.\n");
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}
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}
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/* Record that current_mode is the result of a successful autoneg */
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/* Record that current_mode is the result of a successful autoneg */
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hw->fc.fc_was_autonegged = true;
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hw->fc.fc_was_autonegged = true;
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@ -1919,7 +1984,7 @@ static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
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#endif /* CONFIG_DCB */
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#endif /* CONFIG_DCB */
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default:
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default:
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hw_dbg(hw, "Flow control param set incorrectly\n");
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hw_dbg(hw, "Flow control param set incorrectly\n");
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ret_val = -IXGBE_ERR_CONFIG;
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ret_val = IXGBE_ERR_CONFIG;
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goto out;
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goto out;
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break;
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break;
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}
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}
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@ -1927,9 +1992,6 @@ static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
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IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
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IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
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reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
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reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
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/* Enable and restart autoneg to inform the link partner */
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reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART;
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/* Disable AN timeout */
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/* Disable AN timeout */
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if (hw->fc.strict_ieee)
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if (hw->fc.strict_ieee)
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reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
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reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
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@ -1937,6 +1999,70 @@ static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
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IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
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IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
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hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
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hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
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/*
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* Set up the 10G flow control advertisement registers so the HW
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* can do fc autoneg once the cable is plugged in. If we end up
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* using 1g instead, this is harmless.
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*/
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reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
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/*
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* The possible values of fc.requested_mode are:
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* 0: Flow control is completely disabled
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* 1: Rx flow control is enabled (we can receive pause frames,
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* but not send pause frames).
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* 2: Tx flow control is enabled (we can send pause frames but
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* we do not support receiving pause frames).
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* 3: Both Rx and Tx flow control (symmetric) are enabled.
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* other: Invalid.
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*/
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switch (hw->fc.requested_mode) {
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case ixgbe_fc_none:
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/* Flow control completely disabled by software override. */
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reg &= ~(IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
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break;
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case ixgbe_fc_rx_pause:
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/*
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* Rx Flow control is enabled and Tx Flow control is
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* disabled by software override. Since there really
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* isn't a way to advertise that we are capable of RX
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* Pause ONLY, we will advertise that we support both
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* symmetric and asymmetric Rx PAUSE. Later, we will
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* disable the adapter's ability to send PAUSE frames.
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*/
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reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
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break;
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case ixgbe_fc_tx_pause:
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/*
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* Tx Flow control is enabled, and Rx Flow control is
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* disabled by software override.
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*/
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reg |= (IXGBE_AUTOC_ASM_PAUSE);
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reg &= ~(IXGBE_AUTOC_SYM_PAUSE);
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break;
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case ixgbe_fc_full:
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/* Flow control (both Rx and Tx) is enabled by SW override. */
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reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
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break;
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#ifdef CONFIG_DCB
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case ixgbe_fc_pfc:
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goto out;
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break;
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#endif /* CONFIG_DCB */
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default:
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hw_dbg(hw, "Flow control param set incorrectly\n");
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ret_val = IXGBE_ERR_CONFIG;
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goto out;
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break;
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}
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/*
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* AUTOC restart handles negotiation of 1G and 10G. There is
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* no need to set the PCS1GCTL register.
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*/
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reg |= IXGBE_AUTOC_AN_RESTART;
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IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg);
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hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
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out:
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out:
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return ret_val;
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return ret_val;
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}
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}
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@ -2000,7 +2126,7 @@ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
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while (timeout) {
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while (timeout) {
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if (ixgbe_get_eeprom_semaphore(hw))
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if (ixgbe_get_eeprom_semaphore(hw))
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return -IXGBE_ERR_SWFW_SYNC;
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return IXGBE_ERR_SWFW_SYNC;
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gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
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gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
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if (!(gssr & (fwmask | swmask)))
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if (!(gssr & (fwmask | swmask)))
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@ -2017,7 +2143,7 @@ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
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if (!timeout) {
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if (!timeout) {
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hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n");
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hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n");
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return -IXGBE_ERR_SWFW_SYNC;
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return IXGBE_ERR_SWFW_SYNC;
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}
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}
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gssr |= swmask;
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gssr |= swmask;
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@ -1336,6 +1336,8 @@
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#define IXGBE_AUTOC_KX4_SUPP 0x80000000
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#define IXGBE_AUTOC_KX4_SUPP 0x80000000
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#define IXGBE_AUTOC_KX_SUPP 0x40000000
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#define IXGBE_AUTOC_KX_SUPP 0x40000000
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#define IXGBE_AUTOC_PAUSE 0x30000000
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#define IXGBE_AUTOC_PAUSE 0x30000000
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#define IXGBE_AUTOC_ASM_PAUSE 0x20000000
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#define IXGBE_AUTOC_SYM_PAUSE 0x10000000
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#define IXGBE_AUTOC_RF 0x08000000
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#define IXGBE_AUTOC_RF 0x08000000
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#define IXGBE_AUTOC_PD_TMR 0x06000000
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#define IXGBE_AUTOC_PD_TMR 0x06000000
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#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
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#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
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@ -1404,6 +1406,8 @@
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#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
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#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
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#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
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#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
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#define IXGBE_LINKS2_AN_SUPPORTED 0x00000040
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/* PCS1GLSTA Bit Masks */
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/* PCS1GLSTA Bit Masks */
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#define IXGBE_PCS1GLSTA_LINK_OK 1
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#define IXGBE_PCS1GLSTA_LINK_OK 1
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#define IXGBE_PCS1GLSTA_SYNK_OK 0x10
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#define IXGBE_PCS1GLSTA_SYNK_OK 0x10
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@ -1424,6 +1428,11 @@
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#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
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#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
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#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
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#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
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/* ANLP1 Bit Masks */
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#define IXGBE_ANLP1_PAUSE 0x0C00
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#define IXGBE_ANLP1_SYM_PAUSE 0x0400
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#define IXGBE_ANLP1_ASM_PAUSE 0x0800
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/* SW Semaphore Register bitmasks */
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/* SW Semaphore Register bitmasks */
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||||||
#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
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#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
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||||||
#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
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#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
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||||||
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Loading…
Reference in a new issue