mfd: Modify samsung mfd header
As Prefix of Samsung pmic changed from s5m to s2m, To make common mfd driver for s2m and s5m series, This patch rename header of Samsung mfd and modify mfd driver. Signed-off-by: Sangbeom Kim <sbkim73@samsung.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
parent
63063bfbff
commit
54227bcf20
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@ -21,9 +21,9 @@
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#include <linux/pm_runtime.h>
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#include <linux/mutex.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/samsung/s5m-core.h>
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#include <linux/mfd/samsung/s5m-pmic.h>
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#include <linux/mfd/samsung/s5m-rtc.h>
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#include <linux/mfd/samsung/core.h>
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#include <linux/mfd/samsung/irq.h>
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#include <linux/mfd/samsung/rtc.h>
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#include <linux/regmap.h>
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static struct mfd_cell s5m8751_devs[] = {
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@ -14,7 +14,10 @@
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/mfd/samsung/s5m-core.h>
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#include <linux/mfd/samsung/core.h>
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#include <linux/mfd/samsung/irq.h>
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#include <linux/mfd/samsung/s5m8763.h>
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#include <linux/mfd/samsung/s5m8767.h>
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struct sec_irq_data {
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int reg;
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@ -19,8 +19,8 @@
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#include <linux/platform_device.h>
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#include <linux/regulator/driver.h>
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#include <linux/regulator/machine.h>
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#include <linux/mfd/samsung/s5m-core.h>
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#include <linux/mfd/samsung/s5m-pmic.h>
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#include <linux/mfd/samsung/core.h>
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#include <linux/mfd/samsung/s5m8767.h>
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struct s5m8767_info {
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struct device *dev;
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147
include/linux/mfd/samsung/core.h
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147
include/linux/mfd/samsung/core.h
Normal file
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@ -0,0 +1,147 @@
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/*
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* core.h
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*
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* copyright (c) 2011 Samsung Electronics Co., Ltd
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef __LINUX_MFD_SEC_CORE_H
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#define __LINUX_MFD_SEC_CORE_H
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#define NUM_IRQ_REGS 4
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enum sec_device_type {
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S5M8751X,
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S5M8763X,
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S5M8767X,
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};
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/**
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* struct sec_pmic_dev - s5m87xx master device for sub-drivers
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* @dev: master device of the chip (can be used to access platform data)
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* @i2c: i2c client private data for regulator
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* @rtc: i2c client private data for rtc
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* @iolock: mutex for serializing io access
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* @irqlock: mutex for buslock
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* @irq_base: base IRQ number for sec-pmic, required for IRQs
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* @irq: generic IRQ number for s5m87xx
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* @ono: power onoff IRQ number for s5m87xx
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* @irq_masks_cur: currently active value
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* @irq_masks_cache: cached hardware value
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* @type: indicate which s5m87xx "variant" is used
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*/
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struct sec_pmic_dev {
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struct device *dev;
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struct regmap *regmap;
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struct i2c_client *i2c;
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struct i2c_client *rtc;
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struct mutex iolock;
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struct mutex irqlock;
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int device_type;
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int irq_base;
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int irq;
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int ono;
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u8 irq_masks_cur[NUM_IRQ_REGS];
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u8 irq_masks_cache[NUM_IRQ_REGS];
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int type;
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bool wakeup;
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};
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int sec_irq_init(struct sec_pmic_dev *sec_pmic);
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void sec_irq_exit(struct sec_pmic_dev *sec_pmic);
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int sec_irq_resume(struct sec_pmic_dev *sec_pmic);
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extern int sec_reg_read(struct sec_pmic_dev *sec_pmic, u8 reg, void *dest);
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extern int sec_bulk_read(struct sec_pmic_dev *sec_pmic, u8 reg, int count, u8 *buf);
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extern int sec_reg_write(struct sec_pmic_dev *sec_pmic, u8 reg, u8 value);
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extern int sec_bulk_write(struct sec_pmic_dev *sec_pmic, u8 reg, int count, u8 *buf);
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extern int sec_reg_update(struct sec_pmic_dev *sec_pmic, u8 reg, u8 val, u8 mask);
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struct sec_platform_data {
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struct sec_regulator_data *regulators;
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struct sec_opmode_data *opmode;
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int device_type;
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int num_regulators;
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int irq_base;
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int (*cfg_pmic_irq)(void);
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int ono;
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bool wakeup;
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bool buck_voltage_lock;
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int buck_gpios[3];
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int buck_ds[3];
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int buck2_voltage[8];
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bool buck2_gpiodvs;
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int buck3_voltage[8];
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bool buck3_gpiodvs;
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int buck4_voltage[8];
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bool buck4_gpiodvs;
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int buck_set1;
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int buck_set2;
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int buck_set3;
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int buck2_enable;
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int buck3_enable;
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int buck4_enable;
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int buck_default_idx;
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int buck2_default_idx;
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int buck3_default_idx;
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int buck4_default_idx;
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int buck_ramp_delay;
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bool buck2_ramp_enable;
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bool buck3_ramp_enable;
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bool buck4_ramp_enable;
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int buck2_init;
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int buck3_init;
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int buck4_init;
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};
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/**
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* sec_regulator_data - regulator data
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* @id: regulator id
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* @initdata: regulator init data (contraints, supplies, ...)
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*/
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struct sec_regulator_data {
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int id;
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struct regulator_init_data *initdata;
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};
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/*
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* sec_opmode_data - regulator operation mode data
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* @id: regulator id
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* @mode: regulator operation mode
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*/
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struct sec_opmode_data {
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int id;
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int mode;
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};
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/*
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* samsung regulator operation mode
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* SEC_OPMODE_OFF Regulator always OFF
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* SEC_OPMODE_ON Regulator always ON
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* SEC_OPMODE_LOWPOWER Regulator is on in low-power mode
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* SEC_OPMODE_SUSPEND Regulator is changed by PWREN pin
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* If PWREN is high, regulator is on
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* If PWREN is low, regulator is off
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*/
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enum sec_opmode {
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SEC_OPMODE_OFF,
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SEC_OPMODE_ON,
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SEC_OPMODE_LOWPOWER,
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SEC_OPMODE_SUSPEND,
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};
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#endif /* __LINUX_MFD_SEC_CORE_H */
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110
include/linux/mfd/samsung/irq.h
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110
include/linux/mfd/samsung/irq.h
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/* irq.h
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef __LINUX_MFD_SEC_IRQ_H
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#define __LINUX_MFD_SEC_IRQ_H
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enum s5m8767_irq {
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S5M8767_IRQ_PWRR,
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S5M8767_IRQ_PWRF,
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S5M8767_IRQ_PWR1S,
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S5M8767_IRQ_JIGR,
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S5M8767_IRQ_JIGF,
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S5M8767_IRQ_LOWBAT2,
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S5M8767_IRQ_LOWBAT1,
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S5M8767_IRQ_MRB,
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S5M8767_IRQ_DVSOK2,
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S5M8767_IRQ_DVSOK3,
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S5M8767_IRQ_DVSOK4,
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S5M8767_IRQ_RTC60S,
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S5M8767_IRQ_RTCA1,
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S5M8767_IRQ_RTCA2,
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S5M8767_IRQ_SMPL,
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S5M8767_IRQ_RTC1S,
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S5M8767_IRQ_WTSR,
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S5M8767_IRQ_NR,
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};
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#define S5M8767_IRQ_PWRR_MASK (1 << 0)
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#define S5M8767_IRQ_PWRF_MASK (1 << 1)
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#define S5M8767_IRQ_PWR1S_MASK (1 << 3)
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#define S5M8767_IRQ_JIGR_MASK (1 << 4)
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#define S5M8767_IRQ_JIGF_MASK (1 << 5)
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#define S5M8767_IRQ_LOWBAT2_MASK (1 << 6)
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#define S5M8767_IRQ_LOWBAT1_MASK (1 << 7)
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#define S5M8767_IRQ_MRB_MASK (1 << 2)
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#define S5M8767_IRQ_DVSOK2_MASK (1 << 3)
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#define S5M8767_IRQ_DVSOK3_MASK (1 << 4)
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#define S5M8767_IRQ_DVSOK4_MASK (1 << 5)
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#define S5M8767_IRQ_RTC60S_MASK (1 << 0)
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#define S5M8767_IRQ_RTCA1_MASK (1 << 1)
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#define S5M8767_IRQ_RTCA2_MASK (1 << 2)
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#define S5M8767_IRQ_SMPL_MASK (1 << 3)
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#define S5M8767_IRQ_RTC1S_MASK (1 << 4)
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#define S5M8767_IRQ_WTSR_MASK (1 << 5)
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enum s5m8763_irq {
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S5M8763_IRQ_DCINF,
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S5M8763_IRQ_DCINR,
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S5M8763_IRQ_JIGF,
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S5M8763_IRQ_JIGR,
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S5M8763_IRQ_PWRONF,
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S5M8763_IRQ_PWRONR,
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S5M8763_IRQ_WTSREVNT,
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S5M8763_IRQ_SMPLEVNT,
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S5M8763_IRQ_ALARM1,
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S5M8763_IRQ_ALARM0,
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S5M8763_IRQ_ONKEY1S,
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S5M8763_IRQ_TOPOFFR,
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S5M8763_IRQ_DCINOVPR,
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S5M8763_IRQ_CHGRSTF,
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S5M8763_IRQ_DONER,
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S5M8763_IRQ_CHGFAULT,
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S5M8763_IRQ_LOBAT1,
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S5M8763_IRQ_LOBAT2,
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S5M8763_IRQ_NR,
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};
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#define S5M8763_IRQ_DCINF_MASK (1 << 2)
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#define S5M8763_IRQ_DCINR_MASK (1 << 3)
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#define S5M8763_IRQ_JIGF_MASK (1 << 4)
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#define S5M8763_IRQ_JIGR_MASK (1 << 5)
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#define S5M8763_IRQ_PWRONF_MASK (1 << 6)
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#define S5M8763_IRQ_PWRONR_MASK (1 << 7)
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#define S5M8763_IRQ_WTSREVNT_MASK (1 << 0)
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#define S5M8763_IRQ_SMPLEVNT_MASK (1 << 1)
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#define S5M8763_IRQ_ALARM1_MASK (1 << 2)
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#define S5M8763_IRQ_ALARM0_MASK (1 << 3)
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#define S5M8763_IRQ_ONKEY1S_MASK (1 << 0)
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#define S5M8763_IRQ_TOPOFFR_MASK (1 << 2)
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#define S5M8763_IRQ_DCINOVPR_MASK (1 << 3)
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#define S5M8763_IRQ_CHGRSTF_MASK (1 << 4)
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#define S5M8763_IRQ_DONER_MASK (1 << 5)
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#define S5M8763_IRQ_CHGFAULT_MASK (1 << 7)
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#define S5M8763_IRQ_LOBAT1_MASK (1 << 0)
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#define S5M8763_IRQ_LOBAT2_MASK (1 << 1)
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#define S5M8763_ENRAMP (1 << 4)
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#endif /* __LINUX_MFD_SEC_IRQ_H */
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@ -1,5 +1,4 @@
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/*
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* s5m-rtc.h
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/* rtc.h
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd
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* http://www.samsung.com
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*
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*/
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#ifndef __LINUX_MFD_S5M_RTC_H
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#define __LINUX_MFD_S5M_RTC_H
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#ifndef __LINUX_MFD_SEC_RTC_H
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#define __LINUX_MFD_SEC_RTC_H
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enum s5m87xx_rtc_reg {
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S5M87XX_RTC_SEC,
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S5M87XX_RTC_MIN,
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S5M87XX_RTC_HOUR,
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S5M87XX_RTC_WEEKDAY,
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S5M87XX_RTC_DATE,
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S5M87XX_RTC_MONTH,
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S5M87XX_RTC_YEAR1,
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S5M87XX_RTC_YEAR2,
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S5M87XX_ALARM0_SEC,
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S5M87XX_ALARM0_MIN,
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S5M87XX_ALARM0_HOUR,
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S5M87XX_ALARM0_WEEKDAY,
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S5M87XX_ALARM0_DATE,
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S5M87XX_ALARM0_MONTH,
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S5M87XX_ALARM0_YEAR1,
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S5M87XX_ALARM0_YEAR2,
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S5M87XX_ALARM1_SEC,
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S5M87XX_ALARM1_MIN,
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S5M87XX_ALARM1_HOUR,
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S5M87XX_ALARM1_WEEKDAY,
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S5M87XX_ALARM1_DATE,
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S5M87XX_ALARM1_MONTH,
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S5M87XX_ALARM1_YEAR1,
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S5M87XX_ALARM1_YEAR2,
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S5M87XX_ALARM0_CONF,
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S5M87XX_ALARM1_CONF,
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S5M87XX_RTC_STATUS,
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S5M87XX_WTSR_SMPL_CNTL,
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S5M87XX_RTC_UDR_CON,
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enum sec_rtc_reg {
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SEC_RTC_SEC,
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SEC_RTC_MIN,
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SEC_RTC_HOUR,
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SEC_RTC_WEEKDAY,
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SEC_RTC_DATE,
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SEC_RTC_MONTH,
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SEC_RTC_YEAR1,
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SEC_RTC_YEAR2,
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SEC_ALARM0_SEC,
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SEC_ALARM0_MIN,
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SEC_ALARM0_HOUR,
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SEC_ALARM0_WEEKDAY,
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SEC_ALARM0_DATE,
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SEC_ALARM0_MONTH,
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SEC_ALARM0_YEAR1,
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SEC_ALARM0_YEAR2,
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SEC_ALARM1_SEC,
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SEC_ALARM1_MIN,
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SEC_ALARM1_HOUR,
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SEC_ALARM1_WEEKDAY,
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SEC_ALARM1_DATE,
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SEC_ALARM1_MONTH,
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SEC_ALARM1_YEAR1,
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SEC_ALARM1_YEAR2,
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SEC_ALARM0_CONF,
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SEC_ALARM1_CONF,
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SEC_RTC_STATUS,
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SEC_WTSR_SMPL_CNTL,
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SEC_RTC_UDR_CON,
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};
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#define RTC_I2C_ADDR (0x0C >> 1)
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RTC_YEAR2,
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};
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#endif /* __LINUX_MFD_S5M_RTC_H */
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#endif /* __LINUX_MFD_SEC_RTC_H */
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@ -1,374 +0,0 @@
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/*
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* s5m-core.h
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef __LINUX_MFD_S5M_CORE_H
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#define __LINUX_MFD_S5M_CORE_H
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#define NUM_IRQ_REGS 4
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enum sec_device_type {
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S5M8751X,
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S5M8763X,
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S5M8767X,
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};
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/* S5M8767 registers */
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enum s5m8767_reg {
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S5M8767_REG_ID,
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S5M8767_REG_INT1,
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S5M8767_REG_INT2,
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S5M8767_REG_INT3,
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S5M8767_REG_INT1M,
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S5M8767_REG_INT2M,
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S5M8767_REG_INT3M,
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S5M8767_REG_STATUS1,
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S5M8767_REG_STATUS2,
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S5M8767_REG_STATUS3,
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S5M8767_REG_CTRL1,
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S5M8767_REG_CTRL2,
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S5M8767_REG_LOWBAT1,
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S5M8767_REG_LOWBAT2,
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S5M8767_REG_BUCHG,
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S5M8767_REG_DVSRAMP,
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S5M8767_REG_DVSTIMER2 = 0x10,
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S5M8767_REG_DVSTIMER3,
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S5M8767_REG_DVSTIMER4,
|
||||
S5M8767_REG_LDO1,
|
||||
S5M8767_REG_LDO2,
|
||||
S5M8767_REG_LDO3,
|
||||
S5M8767_REG_LDO4,
|
||||
S5M8767_REG_LDO5,
|
||||
S5M8767_REG_LDO6,
|
||||
S5M8767_REG_LDO7,
|
||||
S5M8767_REG_LDO8,
|
||||
S5M8767_REG_LDO9,
|
||||
S5M8767_REG_LDO10,
|
||||
S5M8767_REG_LDO11,
|
||||
S5M8767_REG_LDO12,
|
||||
S5M8767_REG_LDO13,
|
||||
S5M8767_REG_LDO14 = 0x20,
|
||||
S5M8767_REG_LDO15,
|
||||
S5M8767_REG_LDO16,
|
||||
S5M8767_REG_LDO17,
|
||||
S5M8767_REG_LDO18,
|
||||
S5M8767_REG_LDO19,
|
||||
S5M8767_REG_LDO20,
|
||||
S5M8767_REG_LDO21,
|
||||
S5M8767_REG_LDO22,
|
||||
S5M8767_REG_LDO23,
|
||||
S5M8767_REG_LDO24,
|
||||
S5M8767_REG_LDO25,
|
||||
S5M8767_REG_LDO26,
|
||||
S5M8767_REG_LDO27,
|
||||
S5M8767_REG_LDO28,
|
||||
S5M8767_REG_UVLO = 0x31,
|
||||
S5M8767_REG_BUCK1CTRL1,
|
||||
S5M8767_REG_BUCK1CTRL2,
|
||||
S5M8767_REG_BUCK2CTRL,
|
||||
S5M8767_REG_BUCK2DVS1,
|
||||
S5M8767_REG_BUCK2DVS2,
|
||||
S5M8767_REG_BUCK2DVS3,
|
||||
S5M8767_REG_BUCK2DVS4,
|
||||
S5M8767_REG_BUCK2DVS5,
|
||||
S5M8767_REG_BUCK2DVS6,
|
||||
S5M8767_REG_BUCK2DVS7,
|
||||
S5M8767_REG_BUCK2DVS8,
|
||||
S5M8767_REG_BUCK3CTRL,
|
||||
S5M8767_REG_BUCK3DVS1,
|
||||
S5M8767_REG_BUCK3DVS2,
|
||||
S5M8767_REG_BUCK3DVS3,
|
||||
S5M8767_REG_BUCK3DVS4,
|
||||
S5M8767_REG_BUCK3DVS5,
|
||||
S5M8767_REG_BUCK3DVS6,
|
||||
S5M8767_REG_BUCK3DVS7,
|
||||
S5M8767_REG_BUCK3DVS8,
|
||||
S5M8767_REG_BUCK4CTRL,
|
||||
S5M8767_REG_BUCK4DVS1,
|
||||
S5M8767_REG_BUCK4DVS2,
|
||||
S5M8767_REG_BUCK4DVS3,
|
||||
S5M8767_REG_BUCK4DVS4,
|
||||
S5M8767_REG_BUCK4DVS5,
|
||||
S5M8767_REG_BUCK4DVS6,
|
||||
S5M8767_REG_BUCK4DVS7,
|
||||
S5M8767_REG_BUCK4DVS8,
|
||||
S5M8767_REG_BUCK5CTRL1,
|
||||
S5M8767_REG_BUCK5CTRL2,
|
||||
S5M8767_REG_BUCK5CTRL3,
|
||||
S5M8767_REG_BUCK5CTRL4,
|
||||
S5M8767_REG_BUCK5CTRL5,
|
||||
S5M8767_REG_BUCK6CTRL1,
|
||||
S5M8767_REG_BUCK6CTRL2,
|
||||
S5M8767_REG_BUCK7CTRL1,
|
||||
S5M8767_REG_BUCK7CTRL2,
|
||||
S5M8767_REG_BUCK8CTRL1,
|
||||
S5M8767_REG_BUCK8CTRL2,
|
||||
S5M8767_REG_BUCK9CTRL1,
|
||||
S5M8767_REG_BUCK9CTRL2,
|
||||
S5M8767_REG_LDO1CTRL,
|
||||
S5M8767_REG_LDO2_1CTRL,
|
||||
S5M8767_REG_LDO2_2CTRL,
|
||||
S5M8767_REG_LDO2_3CTRL,
|
||||
S5M8767_REG_LDO2_4CTRL,
|
||||
S5M8767_REG_LDO3CTRL,
|
||||
S5M8767_REG_LDO4CTRL,
|
||||
S5M8767_REG_LDO5CTRL,
|
||||
S5M8767_REG_LDO6CTRL,
|
||||
S5M8767_REG_LDO7CTRL,
|
||||
S5M8767_REG_LDO8CTRL,
|
||||
S5M8767_REG_LDO9CTRL,
|
||||
S5M8767_REG_LDO10CTRL,
|
||||
S5M8767_REG_LDO11CTRL,
|
||||
S5M8767_REG_LDO12CTRL,
|
||||
S5M8767_REG_LDO13CTRL,
|
||||
S5M8767_REG_LDO14CTRL,
|
||||
S5M8767_REG_LDO15CTRL,
|
||||
S5M8767_REG_LDO16CTRL,
|
||||
S5M8767_REG_LDO17CTRL,
|
||||
S5M8767_REG_LDO18CTRL,
|
||||
S5M8767_REG_LDO19CTRL,
|
||||
S5M8767_REG_LDO20CTRL,
|
||||
S5M8767_REG_LDO21CTRL,
|
||||
S5M8767_REG_LDO22CTRL,
|
||||
S5M8767_REG_LDO23CTRL,
|
||||
S5M8767_REG_LDO24CTRL,
|
||||
S5M8767_REG_LDO25CTRL,
|
||||
S5M8767_REG_LDO26CTRL,
|
||||
S5M8767_REG_LDO27CTRL,
|
||||
S5M8767_REG_LDO28CTRL,
|
||||
};
|
||||
|
||||
/* S5M8763 registers */
|
||||
enum s5m8763_reg {
|
||||
S5M8763_REG_IRQ1,
|
||||
S5M8763_REG_IRQ2,
|
||||
S5M8763_REG_IRQ3,
|
||||
S5M8763_REG_IRQ4,
|
||||
S5M8763_REG_IRQM1,
|
||||
S5M8763_REG_IRQM2,
|
||||
S5M8763_REG_IRQM3,
|
||||
S5M8763_REG_IRQM4,
|
||||
S5M8763_REG_STATUS1,
|
||||
S5M8763_REG_STATUS2,
|
||||
S5M8763_REG_STATUSM1,
|
||||
S5M8763_REG_STATUSM2,
|
||||
S5M8763_REG_CHGR1,
|
||||
S5M8763_REG_CHGR2,
|
||||
S5M8763_REG_LDO_ACTIVE_DISCHARGE1,
|
||||
S5M8763_REG_LDO_ACTIVE_DISCHARGE2,
|
||||
S5M8763_REG_BUCK_ACTIVE_DISCHARGE3,
|
||||
S5M8763_REG_ONOFF1,
|
||||
S5M8763_REG_ONOFF2,
|
||||
S5M8763_REG_ONOFF3,
|
||||
S5M8763_REG_ONOFF4,
|
||||
S5M8763_REG_BUCK1_VOLTAGE1,
|
||||
S5M8763_REG_BUCK1_VOLTAGE2,
|
||||
S5M8763_REG_BUCK1_VOLTAGE3,
|
||||
S5M8763_REG_BUCK1_VOLTAGE4,
|
||||
S5M8763_REG_BUCK2_VOLTAGE1,
|
||||
S5M8763_REG_BUCK2_VOLTAGE2,
|
||||
S5M8763_REG_BUCK3,
|
||||
S5M8763_REG_BUCK4,
|
||||
S5M8763_REG_LDO1_LDO2,
|
||||
S5M8763_REG_LDO3,
|
||||
S5M8763_REG_LDO4,
|
||||
S5M8763_REG_LDO5,
|
||||
S5M8763_REG_LDO6,
|
||||
S5M8763_REG_LDO7,
|
||||
S5M8763_REG_LDO7_LDO8,
|
||||
S5M8763_REG_LDO9_LDO10,
|
||||
S5M8763_REG_LDO11,
|
||||
S5M8763_REG_LDO12,
|
||||
S5M8763_REG_LDO13,
|
||||
S5M8763_REG_LDO14,
|
||||
S5M8763_REG_LDO15,
|
||||
S5M8763_REG_LDO16,
|
||||
S5M8763_REG_BKCHR,
|
||||
S5M8763_REG_LBCNFG1,
|
||||
S5M8763_REG_LBCNFG2,
|
||||
};
|
||||
|
||||
enum s5m8767_irq {
|
||||
S5M8767_IRQ_PWRR,
|
||||
S5M8767_IRQ_PWRF,
|
||||
S5M8767_IRQ_PWR1S,
|
||||
S5M8767_IRQ_JIGR,
|
||||
S5M8767_IRQ_JIGF,
|
||||
S5M8767_IRQ_LOWBAT2,
|
||||
S5M8767_IRQ_LOWBAT1,
|
||||
|
||||
S5M8767_IRQ_MRB,
|
||||
S5M8767_IRQ_DVSOK2,
|
||||
S5M8767_IRQ_DVSOK3,
|
||||
S5M8767_IRQ_DVSOK4,
|
||||
|
||||
S5M8767_IRQ_RTC60S,
|
||||
S5M8767_IRQ_RTCA1,
|
||||
S5M8767_IRQ_RTCA2,
|
||||
S5M8767_IRQ_SMPL,
|
||||
S5M8767_IRQ_RTC1S,
|
||||
S5M8767_IRQ_WTSR,
|
||||
|
||||
S5M8767_IRQ_NR,
|
||||
};
|
||||
|
||||
#define S5M8767_IRQ_PWRR_MASK (1 << 0)
|
||||
#define S5M8767_IRQ_PWRF_MASK (1 << 1)
|
||||
#define S5M8767_IRQ_PWR1S_MASK (1 << 3)
|
||||
#define S5M8767_IRQ_JIGR_MASK (1 << 4)
|
||||
#define S5M8767_IRQ_JIGF_MASK (1 << 5)
|
||||
#define S5M8767_IRQ_LOWBAT2_MASK (1 << 6)
|
||||
#define S5M8767_IRQ_LOWBAT1_MASK (1 << 7)
|
||||
|
||||
#define S5M8767_IRQ_MRB_MASK (1 << 2)
|
||||
#define S5M8767_IRQ_DVSOK2_MASK (1 << 3)
|
||||
#define S5M8767_IRQ_DVSOK3_MASK (1 << 4)
|
||||
#define S5M8767_IRQ_DVSOK4_MASK (1 << 5)
|
||||
|
||||
#define S5M8767_IRQ_RTC60S_MASK (1 << 0)
|
||||
#define S5M8767_IRQ_RTCA1_MASK (1 << 1)
|
||||
#define S5M8767_IRQ_RTCA2_MASK (1 << 2)
|
||||
#define S5M8767_IRQ_SMPL_MASK (1 << 3)
|
||||
#define S5M8767_IRQ_RTC1S_MASK (1 << 4)
|
||||
#define S5M8767_IRQ_WTSR_MASK (1 << 5)
|
||||
|
||||
enum s5m8763_irq {
|
||||
S5M8763_IRQ_DCINF,
|
||||
S5M8763_IRQ_DCINR,
|
||||
S5M8763_IRQ_JIGF,
|
||||
S5M8763_IRQ_JIGR,
|
||||
S5M8763_IRQ_PWRONF,
|
||||
S5M8763_IRQ_PWRONR,
|
||||
|
||||
S5M8763_IRQ_WTSREVNT,
|
||||
S5M8763_IRQ_SMPLEVNT,
|
||||
S5M8763_IRQ_ALARM1,
|
||||
S5M8763_IRQ_ALARM0,
|
||||
|
||||
S5M8763_IRQ_ONKEY1S,
|
||||
S5M8763_IRQ_TOPOFFR,
|
||||
S5M8763_IRQ_DCINOVPR,
|
||||
S5M8763_IRQ_CHGRSTF,
|
||||
S5M8763_IRQ_DONER,
|
||||
S5M8763_IRQ_CHGFAULT,
|
||||
|
||||
S5M8763_IRQ_LOBAT1,
|
||||
S5M8763_IRQ_LOBAT2,
|
||||
|
||||
S5M8763_IRQ_NR,
|
||||
};
|
||||
|
||||
#define S5M8763_IRQ_DCINF_MASK (1 << 2)
|
||||
#define S5M8763_IRQ_DCINR_MASK (1 << 3)
|
||||
#define S5M8763_IRQ_JIGF_MASK (1 << 4)
|
||||
#define S5M8763_IRQ_JIGR_MASK (1 << 5)
|
||||
#define S5M8763_IRQ_PWRONF_MASK (1 << 6)
|
||||
#define S5M8763_IRQ_PWRONR_MASK (1 << 7)
|
||||
|
||||
#define S5M8763_IRQ_WTSREVNT_MASK (1 << 0)
|
||||
#define S5M8763_IRQ_SMPLEVNT_MASK (1 << 1)
|
||||
#define S5M8763_IRQ_ALARM1_MASK (1 << 2)
|
||||
#define S5M8763_IRQ_ALARM0_MASK (1 << 3)
|
||||
|
||||
#define S5M8763_IRQ_ONKEY1S_MASK (1 << 0)
|
||||
#define S5M8763_IRQ_TOPOFFR_MASK (1 << 2)
|
||||
#define S5M8763_IRQ_DCINOVPR_MASK (1 << 3)
|
||||
#define S5M8763_IRQ_CHGRSTF_MASK (1 << 4)
|
||||
#define S5M8763_IRQ_DONER_MASK (1 << 5)
|
||||
#define S5M8763_IRQ_CHGFAULT_MASK (1 << 7)
|
||||
|
||||
#define S5M8763_IRQ_LOBAT1_MASK (1 << 0)
|
||||
#define S5M8763_IRQ_LOBAT2_MASK (1 << 1)
|
||||
|
||||
#define S5M8763_ENRAMP (1 << 4)
|
||||
|
||||
/**
|
||||
* struct sec_pmic_dev - sec_pmic master device for sub-drivers
|
||||
* @dev: master device of the chip (can be used to access platform data)
|
||||
* @i2c: i2c client private data for regulator
|
||||
* @rtc: i2c client private data for rtc
|
||||
* @iolock: mutex for serializing io access
|
||||
* @irqlock: mutex for buslock
|
||||
* @irq_base: base IRQ number for sec_pmic, required for IRQs
|
||||
* @irq: generic IRQ number for s5m87xx
|
||||
* @ono: power onoff IRQ number for s5m87xx
|
||||
* @irq_masks_cur: currently active value
|
||||
* @irq_masks_cache: cached hardware value
|
||||
* @type: indicate which s5m87xx "variant" is used
|
||||
*/
|
||||
struct sec_pmic_dev {
|
||||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
struct i2c_client *i2c;
|
||||
struct i2c_client *rtc;
|
||||
struct mutex iolock;
|
||||
struct mutex irqlock;
|
||||
|
||||
int device_type;
|
||||
int irq_base;
|
||||
int irq;
|
||||
int ono;
|
||||
u8 irq_masks_cur[NUM_IRQ_REGS];
|
||||
u8 irq_masks_cache[NUM_IRQ_REGS];
|
||||
int type;
|
||||
bool wakeup;
|
||||
};
|
||||
|
||||
int sec_irq_init(struct sec_pmic_dev *sec_pmic);
|
||||
void sec_irq_exit(struct sec_pmic_dev *sec_pmic);
|
||||
int sec_irq_resume(struct sec_pmic_dev *sec_pmic);
|
||||
|
||||
extern int sec_reg_read(struct sec_pmic_dev *sec_pmic, u8 reg, void *dest);
|
||||
extern int sec_bulk_read(struct sec_pmic_dev *sec_pmic, u8 reg, int count, u8 *buf);
|
||||
extern int sec_reg_write(struct sec_pmic_dev *sec_pmic, u8 reg, u8 value);
|
||||
extern int sec_bulk_write(struct sec_pmic_dev *sec_pmic, u8 reg, int count, u8 *buf);
|
||||
extern int sec_reg_update(struct sec_pmic_dev *sec_pmic, u8 reg, u8 val, u8 mask);
|
||||
|
||||
struct sec_platform_data {
|
||||
struct sec_regulator_data *regulators;
|
||||
struct sec_opmode_data *opmode;
|
||||
int device_type;
|
||||
int num_regulators;
|
||||
|
||||
int irq_base;
|
||||
int (*cfg_pmic_irq)(void);
|
||||
|
||||
int ono;
|
||||
bool wakeup;
|
||||
bool buck_voltage_lock;
|
||||
|
||||
int buck_gpios[3];
|
||||
int buck2_voltage[8];
|
||||
bool buck2_gpiodvs;
|
||||
int buck3_voltage[8];
|
||||
bool buck3_gpiodvs;
|
||||
int buck4_voltage[8];
|
||||
bool buck4_gpiodvs;
|
||||
|
||||
int buck_set1;
|
||||
int buck_set2;
|
||||
int buck_set3;
|
||||
int buck2_enable;
|
||||
int buck3_enable;
|
||||
int buck4_enable;
|
||||
int buck_default_idx;
|
||||
int buck2_default_idx;
|
||||
int buck3_default_idx;
|
||||
int buck4_default_idx;
|
||||
|
||||
int buck_ramp_delay;
|
||||
bool buck2_ramp_enable;
|
||||
bool buck3_ramp_enable;
|
||||
bool buck4_ramp_enable;
|
||||
};
|
||||
|
||||
#endif /* __LINUX_MFD_S5M_CORE_H */
|
|
@ -1,129 +0,0 @@
|
|||
/* s5m87xx.h
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_S5M_PMIC_H
|
||||
#define __LINUX_MFD_S5M_PMIC_H
|
||||
|
||||
#include <linux/regulator/machine.h>
|
||||
|
||||
/* S5M8767 regulator ids */
|
||||
enum s5m8767_regulators {
|
||||
S5M8767_LDO1,
|
||||
S5M8767_LDO2,
|
||||
S5M8767_LDO3,
|
||||
S5M8767_LDO4,
|
||||
S5M8767_LDO5,
|
||||
S5M8767_LDO6,
|
||||
S5M8767_LDO7,
|
||||
S5M8767_LDO8,
|
||||
S5M8767_LDO9,
|
||||
S5M8767_LDO10,
|
||||
S5M8767_LDO11,
|
||||
S5M8767_LDO12,
|
||||
S5M8767_LDO13,
|
||||
S5M8767_LDO14,
|
||||
S5M8767_LDO15,
|
||||
S5M8767_LDO16,
|
||||
S5M8767_LDO17,
|
||||
S5M8767_LDO18,
|
||||
S5M8767_LDO19,
|
||||
S5M8767_LDO20,
|
||||
S5M8767_LDO21,
|
||||
S5M8767_LDO22,
|
||||
S5M8767_LDO23,
|
||||
S5M8767_LDO24,
|
||||
S5M8767_LDO25,
|
||||
S5M8767_LDO26,
|
||||
S5M8767_LDO27,
|
||||
S5M8767_LDO28,
|
||||
S5M8767_BUCK1,
|
||||
S5M8767_BUCK2,
|
||||
S5M8767_BUCK3,
|
||||
S5M8767_BUCK4,
|
||||
S5M8767_BUCK5,
|
||||
S5M8767_BUCK6,
|
||||
S5M8767_BUCK7,
|
||||
S5M8767_BUCK8,
|
||||
S5M8767_BUCK9,
|
||||
S5M8767_AP_EN32KHZ,
|
||||
S5M8767_CP_EN32KHZ,
|
||||
|
||||
S5M8767_REG_MAX,
|
||||
};
|
||||
|
||||
#define S5M8767_ENCTRL_SHIFT 6
|
||||
|
||||
/* S5M8763 regulator ids */
|
||||
enum s5m8763_regulators {
|
||||
S5M8763_LDO1,
|
||||
S5M8763_LDO2,
|
||||
S5M8763_LDO3,
|
||||
S5M8763_LDO4,
|
||||
S5M8763_LDO5,
|
||||
S5M8763_LDO6,
|
||||
S5M8763_LDO7,
|
||||
S5M8763_LDO8,
|
||||
S5M8763_LDO9,
|
||||
S5M8763_LDO10,
|
||||
S5M8763_LDO11,
|
||||
S5M8763_LDO12,
|
||||
S5M8763_LDO13,
|
||||
S5M8763_LDO14,
|
||||
S5M8763_LDO15,
|
||||
S5M8763_LDO16,
|
||||
S5M8763_BUCK1,
|
||||
S5M8763_BUCK2,
|
||||
S5M8763_BUCK3,
|
||||
S5M8763_BUCK4,
|
||||
S5M8763_AP_EN32KHZ,
|
||||
S5M8763_CP_EN32KHZ,
|
||||
S5M8763_ENCHGVI,
|
||||
S5M8763_ESAFEUSB1,
|
||||
S5M8763_ESAFEUSB2,
|
||||
};
|
||||
|
||||
/**
|
||||
* s5m87xx_regulator_data - regulator data
|
||||
* @id: regulator id
|
||||
* @initdata: regulator init data (contraints, supplies, ...)
|
||||
*/
|
||||
struct sec_regulator_data {
|
||||
int id;
|
||||
struct regulator_init_data *initdata;
|
||||
};
|
||||
|
||||
/*
|
||||
* s5m_opmode_data - regulator operation mode data
|
||||
* @id: regulator id
|
||||
* @mode: regulator operation mode
|
||||
*/
|
||||
struct sec_opmode_data {
|
||||
int id;
|
||||
int mode;
|
||||
};
|
||||
|
||||
/*
|
||||
* samsung regulator operation mode
|
||||
* SEC_OPMODE_OFF Regulator always OFF
|
||||
* SEC_OPMODE_ON Regulator always ON
|
||||
* SEC_OPMODE_LOWPOWER Regulator is on in low-power mode
|
||||
* SEC_OPMODE_SUSPEND Regulator is changed by PWREN pin
|
||||
* If PWREN is high, regulator is on
|
||||
* If PWREN is low, regulator is off
|
||||
*/
|
||||
|
||||
enum sec_opmode {
|
||||
SEC_OPMODE_OFF,
|
||||
SEC_OPMODE_ON,
|
||||
SEC_OPMODE_LOWPOWER,
|
||||
SEC_OPMODE_SUSPEND,
|
||||
};
|
||||
|
||||
#endif /* __LINUX_MFD_S5M_PMIC_H */
|
96
include/linux/mfd/samsung/s5m8763.h
Normal file
96
include/linux/mfd/samsung/s5m8763.h
Normal file
|
@ -0,0 +1,96 @@
|
|||
/* s5m8763.h
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_S5M8763_H
|
||||
#define __LINUX_MFD_S5M8763_H
|
||||
|
||||
/* S5M8763 registers */
|
||||
enum s5m8763_reg {
|
||||
S5M8763_REG_IRQ1,
|
||||
S5M8763_REG_IRQ2,
|
||||
S5M8763_REG_IRQ3,
|
||||
S5M8763_REG_IRQ4,
|
||||
S5M8763_REG_IRQM1,
|
||||
S5M8763_REG_IRQM2,
|
||||
S5M8763_REG_IRQM3,
|
||||
S5M8763_REG_IRQM4,
|
||||
S5M8763_REG_STATUS1,
|
||||
S5M8763_REG_STATUS2,
|
||||
S5M8763_REG_STATUSM1,
|
||||
S5M8763_REG_STATUSM2,
|
||||
S5M8763_REG_CHGR1,
|
||||
S5M8763_REG_CHGR2,
|
||||
S5M8763_REG_LDO_ACTIVE_DISCHARGE1,
|
||||
S5M8763_REG_LDO_ACTIVE_DISCHARGE2,
|
||||
S5M8763_REG_BUCK_ACTIVE_DISCHARGE3,
|
||||
S5M8763_REG_ONOFF1,
|
||||
S5M8763_REG_ONOFF2,
|
||||
S5M8763_REG_ONOFF3,
|
||||
S5M8763_REG_ONOFF4,
|
||||
S5M8763_REG_BUCK1_VOLTAGE1,
|
||||
S5M8763_REG_BUCK1_VOLTAGE2,
|
||||
S5M8763_REG_BUCK1_VOLTAGE3,
|
||||
S5M8763_REG_BUCK1_VOLTAGE4,
|
||||
S5M8763_REG_BUCK2_VOLTAGE1,
|
||||
S5M8763_REG_BUCK2_VOLTAGE2,
|
||||
S5M8763_REG_BUCK3,
|
||||
S5M8763_REG_BUCK4,
|
||||
S5M8763_REG_LDO1_LDO2,
|
||||
S5M8763_REG_LDO3,
|
||||
S5M8763_REG_LDO4,
|
||||
S5M8763_REG_LDO5,
|
||||
S5M8763_REG_LDO6,
|
||||
S5M8763_REG_LDO7,
|
||||
S5M8763_REG_LDO7_LDO8,
|
||||
S5M8763_REG_LDO9_LDO10,
|
||||
S5M8763_REG_LDO11,
|
||||
S5M8763_REG_LDO12,
|
||||
S5M8763_REG_LDO13,
|
||||
S5M8763_REG_LDO14,
|
||||
S5M8763_REG_LDO15,
|
||||
S5M8763_REG_LDO16,
|
||||
S5M8763_REG_BKCHR,
|
||||
S5M8763_REG_LBCNFG1,
|
||||
S5M8763_REG_LBCNFG2,
|
||||
};
|
||||
|
||||
/* S5M8763 regulator ids */
|
||||
enum s5m8763_regulators {
|
||||
S5M8763_LDO1,
|
||||
S5M8763_LDO2,
|
||||
S5M8763_LDO3,
|
||||
S5M8763_LDO4,
|
||||
S5M8763_LDO5,
|
||||
S5M8763_LDO6,
|
||||
S5M8763_LDO7,
|
||||
S5M8763_LDO8,
|
||||
S5M8763_LDO9,
|
||||
S5M8763_LDO10,
|
||||
S5M8763_LDO11,
|
||||
S5M8763_LDO12,
|
||||
S5M8763_LDO13,
|
||||
S5M8763_LDO14,
|
||||
S5M8763_LDO15,
|
||||
S5M8763_LDO16,
|
||||
S5M8763_BUCK1,
|
||||
S5M8763_BUCK2,
|
||||
S5M8763_BUCK3,
|
||||
S5M8763_BUCK4,
|
||||
S5M8763_AP_EN32KHZ,
|
||||
S5M8763_CP_EN32KHZ,
|
||||
S5M8763_ENCHGVI,
|
||||
S5M8763_ESAFEUSB1,
|
||||
S5M8763_ESAFEUSB2,
|
||||
};
|
||||
|
||||
#define S5M8763_ENRAMP (1 << 4)
|
||||
#endif /* __LINUX_MFD_S5M8763_H */
|
188
include/linux/mfd/samsung/s5m8767.h
Normal file
188
include/linux/mfd/samsung/s5m8767.h
Normal file
|
@ -0,0 +1,188 @@
|
|||
/* s5m8767.h
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_S5M8767_H
|
||||
#define __LINUX_MFD_S5M8767_H
|
||||
|
||||
/* S5M8767 registers */
|
||||
enum s5m8767_reg {
|
||||
S5M8767_REG_ID,
|
||||
S5M8767_REG_INT1,
|
||||
S5M8767_REG_INT2,
|
||||
S5M8767_REG_INT3,
|
||||
S5M8767_REG_INT1M,
|
||||
S5M8767_REG_INT2M,
|
||||
S5M8767_REG_INT3M,
|
||||
S5M8767_REG_STATUS1,
|
||||
S5M8767_REG_STATUS2,
|
||||
S5M8767_REG_STATUS3,
|
||||
S5M8767_REG_CTRL1,
|
||||
S5M8767_REG_CTRL2,
|
||||
S5M8767_REG_LOWBAT1,
|
||||
S5M8767_REG_LOWBAT2,
|
||||
S5M8767_REG_BUCHG,
|
||||
S5M8767_REG_DVSRAMP,
|
||||
S5M8767_REG_DVSTIMER2 = 0x10,
|
||||
S5M8767_REG_DVSTIMER3,
|
||||
S5M8767_REG_DVSTIMER4,
|
||||
S5M8767_REG_LDO1,
|
||||
S5M8767_REG_LDO2,
|
||||
S5M8767_REG_LDO3,
|
||||
S5M8767_REG_LDO4,
|
||||
S5M8767_REG_LDO5,
|
||||
S5M8767_REG_LDO6,
|
||||
S5M8767_REG_LDO7,
|
||||
S5M8767_REG_LDO8,
|
||||
S5M8767_REG_LDO9,
|
||||
S5M8767_REG_LDO10,
|
||||
S5M8767_REG_LDO11,
|
||||
S5M8767_REG_LDO12,
|
||||
S5M8767_REG_LDO13,
|
||||
S5M8767_REG_LDO14 = 0x20,
|
||||
S5M8767_REG_LDO15,
|
||||
S5M8767_REG_LDO16,
|
||||
S5M8767_REG_LDO17,
|
||||
S5M8767_REG_LDO18,
|
||||
S5M8767_REG_LDO19,
|
||||
S5M8767_REG_LDO20,
|
||||
S5M8767_REG_LDO21,
|
||||
S5M8767_REG_LDO22,
|
||||
S5M8767_REG_LDO23,
|
||||
S5M8767_REG_LDO24,
|
||||
S5M8767_REG_LDO25,
|
||||
S5M8767_REG_LDO26,
|
||||
S5M8767_REG_LDO27,
|
||||
S5M8767_REG_LDO28,
|
||||
S5M8767_REG_UVLO = 0x31,
|
||||
S5M8767_REG_BUCK1CTRL1,
|
||||
S5M8767_REG_BUCK1CTRL2,
|
||||
S5M8767_REG_BUCK2CTRL,
|
||||
S5M8767_REG_BUCK2DVS1,
|
||||
S5M8767_REG_BUCK2DVS2,
|
||||
S5M8767_REG_BUCK2DVS3,
|
||||
S5M8767_REG_BUCK2DVS4,
|
||||
S5M8767_REG_BUCK2DVS5,
|
||||
S5M8767_REG_BUCK2DVS6,
|
||||
S5M8767_REG_BUCK2DVS7,
|
||||
S5M8767_REG_BUCK2DVS8,
|
||||
S5M8767_REG_BUCK3CTRL,
|
||||
S5M8767_REG_BUCK3DVS1,
|
||||
S5M8767_REG_BUCK3DVS2,
|
||||
S5M8767_REG_BUCK3DVS3,
|
||||
S5M8767_REG_BUCK3DVS4,
|
||||
S5M8767_REG_BUCK3DVS5,
|
||||
S5M8767_REG_BUCK3DVS6,
|
||||
S5M8767_REG_BUCK3DVS7,
|
||||
S5M8767_REG_BUCK3DVS8,
|
||||
S5M8767_REG_BUCK4CTRL,
|
||||
S5M8767_REG_BUCK4DVS1,
|
||||
S5M8767_REG_BUCK4DVS2,
|
||||
S5M8767_REG_BUCK4DVS3,
|
||||
S5M8767_REG_BUCK4DVS4,
|
||||
S5M8767_REG_BUCK4DVS5,
|
||||
S5M8767_REG_BUCK4DVS6,
|
||||
S5M8767_REG_BUCK4DVS7,
|
||||
S5M8767_REG_BUCK4DVS8,
|
||||
S5M8767_REG_BUCK5CTRL1,
|
||||
S5M8767_REG_BUCK5CTRL2,
|
||||
S5M8767_REG_BUCK5CTRL3,
|
||||
S5M8767_REG_BUCK5CTRL4,
|
||||
S5M8767_REG_BUCK5CTRL5,
|
||||
S5M8767_REG_BUCK6CTRL1,
|
||||
S5M8767_REG_BUCK6CTRL2,
|
||||
S5M8767_REG_BUCK7CTRL1,
|
||||
S5M8767_REG_BUCK7CTRL2,
|
||||
S5M8767_REG_BUCK8CTRL1,
|
||||
S5M8767_REG_BUCK8CTRL2,
|
||||
S5M8767_REG_BUCK9CTRL1,
|
||||
S5M8767_REG_BUCK9CTRL2,
|
||||
S5M8767_REG_LDO1CTRL,
|
||||
S5M8767_REG_LDO2_1CTRL,
|
||||
S5M8767_REG_LDO2_2CTRL,
|
||||
S5M8767_REG_LDO2_3CTRL,
|
||||
S5M8767_REG_LDO2_4CTRL,
|
||||
S5M8767_REG_LDO3CTRL,
|
||||
S5M8767_REG_LDO4CTRL,
|
||||
S5M8767_REG_LDO5CTRL,
|
||||
S5M8767_REG_LDO6CTRL,
|
||||
S5M8767_REG_LDO7CTRL,
|
||||
S5M8767_REG_LDO8CTRL,
|
||||
S5M8767_REG_LDO9CTRL,
|
||||
S5M8767_REG_LDO10CTRL,
|
||||
S5M8767_REG_LDO11CTRL,
|
||||
S5M8767_REG_LDO12CTRL,
|
||||
S5M8767_REG_LDO13CTRL,
|
||||
S5M8767_REG_LDO14CTRL,
|
||||
S5M8767_REG_LDO15CTRL,
|
||||
S5M8767_REG_LDO16CTRL,
|
||||
S5M8767_REG_LDO17CTRL,
|
||||
S5M8767_REG_LDO18CTRL,
|
||||
S5M8767_REG_LDO19CTRL,
|
||||
S5M8767_REG_LDO20CTRL,
|
||||
S5M8767_REG_LDO21CTRL,
|
||||
S5M8767_REG_LDO22CTRL,
|
||||
S5M8767_REG_LDO23CTRL,
|
||||
S5M8767_REG_LDO24CTRL,
|
||||
S5M8767_REG_LDO25CTRL,
|
||||
S5M8767_REG_LDO26CTRL,
|
||||
S5M8767_REG_LDO27CTRL,
|
||||
S5M8767_REG_LDO28CTRL,
|
||||
};
|
||||
|
||||
/* S5M8767 regulator ids */
|
||||
enum s5m8767_regulators {
|
||||
S5M8767_LDO1,
|
||||
S5M8767_LDO2,
|
||||
S5M8767_LDO3,
|
||||
S5M8767_LDO4,
|
||||
S5M8767_LDO5,
|
||||
S5M8767_LDO6,
|
||||
S5M8767_LDO7,
|
||||
S5M8767_LDO8,
|
||||
S5M8767_LDO9,
|
||||
S5M8767_LDO10,
|
||||
S5M8767_LDO11,
|
||||
S5M8767_LDO12,
|
||||
S5M8767_LDO13,
|
||||
S5M8767_LDO14,
|
||||
S5M8767_LDO15,
|
||||
S5M8767_LDO16,
|
||||
S5M8767_LDO17,
|
||||
S5M8767_LDO18,
|
||||
S5M8767_LDO19,
|
||||
S5M8767_LDO20,
|
||||
S5M8767_LDO21,
|
||||
S5M8767_LDO22,
|
||||
S5M8767_LDO23,
|
||||
S5M8767_LDO24,
|
||||
S5M8767_LDO25,
|
||||
S5M8767_LDO26,
|
||||
S5M8767_LDO27,
|
||||
S5M8767_LDO28,
|
||||
S5M8767_BUCK1,
|
||||
S5M8767_BUCK2,
|
||||
S5M8767_BUCK3,
|
||||
S5M8767_BUCK4,
|
||||
S5M8767_BUCK5,
|
||||
S5M8767_BUCK6,
|
||||
S5M8767_BUCK7,
|
||||
S5M8767_BUCK8,
|
||||
S5M8767_BUCK9,
|
||||
S5M8767_AP_EN32KHZ,
|
||||
S5M8767_CP_EN32KHZ,
|
||||
|
||||
S5M8767_REG_MAX,
|
||||
};
|
||||
|
||||
#define S5M8767_ENCTRL_SHIFT 6
|
||||
|
||||
#endif /* __LINUX_MFD_S5M8767_H */
|
Loading…
Reference in a new issue