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MLK-18241-1 ARM64: dts: freescale: imx8qxp: correct edma index 

Correct edma index for imx8qxp to mach the right rsrc id of scfw.

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
pull/10/head
Robin Gong 2018-05-08 23:58:46 +08:00 committed by Jason Liu
parent 02c1772cc9
commit 544928ede7
1 changed files with 37 additions and 37 deletions
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74
arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
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@ -2220,8 +2220,8 @@
assigned-clock-rates = <80000000>;
power-domains = <&pd_dma_lpuart1>;
dma-names = "tx","rx";
dmas = <&edma0 11 0 0>,
<&edma0 10 0 1>;
dmas = <&edma2 11 0 0>,
<&edma2 10 0 1>;
status = "disabled";
};
@ -2237,8 +2237,8 @@
assigned-clock-rates = <80000000>;
power-domains = <&pd_dma_lpuart2>;
dma-names = "tx","rx";
dmas = <&edma0 13 0 0>,
<&edma0 12 0 1>;
dmas = <&edma2 13 0 0>,
<&edma2 12 0 1>;
status = "disabled";
};
@ -2254,12 +2254,12 @@
assigned-clock-rates = <80000000>;
power-domains = <&pd_dma_lpuart3>;
dma-names = "tx","rx";
dmas = <&edma0 15 0 0>,
<&edma0 14 0 1>;
dmas = <&edma2 15 0 0>,
<&edma2 14 0 1>;
status = "disabled";
};
edma0: dma-controller@5a1f0000 {
edma2: dma-controller@5a1f0000 {
compatible = "fsl,imx8qm-edma";
reg = <0x0 0x5a280000 0x0 0x10000>, /* channel8 UART0 rx */
<0x0 0x5a290000 0x0 0x10000>, /* channel9 UART0 tx */
@ -2279,14 +2279,14 @@
<GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma0-chan8-rx", "edma0-chan9-tx",
"edma0-chan10-rx", "edma0-chan11-tx",
"edma0-chan12-rx", "edma0-chan13-tx",
"edma0-chan14-rx", "edma0-chan15-tx";
interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx",
"edma2-chan10-rx", "edma2-chan11-tx",
"edma2-chan12-rx", "edma2-chan13-tx",
"edma2-chan14-rx", "edma2-chan15-tx";
status = "okay";
};
edma2: dma-controller@591F0000 {
edma0: dma-controller@591F0000 {
compatible = "fsl,imx8qm-edma";
reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */
<0x0 0x59210000 0x0 0x10000>,
@ -2323,19 +2323,19 @@
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma2-chan0-rx", "edma2-chan1-rx", /* asrc0 */
"edma2-chan2-rx", "edma2-chan3-tx",
"edma2-chan4-tx", "edma2-chan5-tx",
"edma2-chan6-rx", "edma2-chan7-tx", /* esai0 */
"edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */
"edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */
"edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */
"edma2-chan21-tx", /* gpt5 */
"edma2-chan23-rx"; /* gpt7 */
interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */
"edma0-chan2-rx", "edma0-chan3-tx",
"edma0-chan4-tx", "edma0-chan5-tx",
"edma0-chan6-rx", "edma0-chan7-tx", /* esai0 */
"edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */
"edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */
"edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */
"edma0-chan21-tx", /* gpt5 */
"edma0-chan23-rx"; /* gpt7 */
status = "okay";
};
edma3: dma-controller@599F0000 {
edma1: dma-controller@599F0000 {
compatible = "fsl,imx8qm-edma";
reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */
<0x0 0x59A10000 0x0 0x10000>,
@ -2358,11 +2358,11 @@
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
interrupt-names = "edma3-chan0-rx", "edma3-chan1-rx", /* asrc1 */
"edma3-chan2-rx", "edma3-chan3-tx",
"edma3-chan4-tx", "edma3-chan5-tx",
"edma3-chan8-rx", "edma3-chan9-tx", /* sai4 */
"edma3-chan10-tx"; /* sai5 */
interrupt-names = "edma1-chan0-rx", "edma1-chan1-rx", /* asrc1 */
"edma1-chan2-rx", "edma1-chan3-tx",
"edma1-chan4-tx", "edma1-chan5-tx",
"edma1-chan8-rx", "edma1-chan9-tx", /* sai4 */
"edma1-chan10-tx"; /* sai5 */
status = "okay";
};
@ -2383,7 +2383,7 @@
<&clk IMX8QXP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dma-names = "rx", "tx";
dmas = <&edma2 12 0 1>, <&edma2 13 0 0>;
dmas = <&edma0 12 0 1>, <&edma0 13 0 0>;
status = "disabled";
power-domains = <&pd_sai0>;
};
@ -2399,7 +2399,7 @@
<&clk IMX8QXP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dma-names = "rx", "tx";
dmas = <&edma2 14 0 1>, <&edma2 15 0 0>;
dmas = <&edma0 14 0 1>, <&edma0 15 0 0>;
status = "disabled";
power-domains = <&pd_sai1>;
};
@ -2413,7 +2413,7 @@
<&clk IMX8QXP_AUD_SAI_4_MCLK>,
<&clk IMX8QXP_CLK_DUMMY>,
<&clk IMX8QXP_CLK_DUMMY>;
dmas = <&edma3 8 0 1>, <&edma3 9 0 0>;
dmas = <&edma1 8 0 1>, <&edma1 9 0 0>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dma-names = "rx", "tx";
status = "disabled";
@ -2431,7 +2431,7 @@
<&clk IMX8QXP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dma-names = "tx";
dmas = <&edma3 10 0 0>;
dmas = <&edma1 10 0 0>;
status = "disabled";
power-domains = <&pd_sai5>;
};
@ -2475,8 +2475,8 @@
"asrck_8", "asrck_9", "asrck_a", "asrck_b",
"asrck_c", "asrck_d", "asrck_e", "asrck_f",
"spba";
dmas = <&edma2 0 0 0>, <&edma2 1 0 0>, <&edma2 2 0 0>,
<&edma2 3 0 1>, <&edma2 4 0 1>, <&edma2 5 0 1>;
dmas = <&edma0 0 0 0>, <&edma0 1 0 0>, <&edma0 2 0 0>,
<&edma0 3 0 1>, <&edma0 4 0 1>, <&edma0 5 0 1>;
dma-names = "rxa", "rxb", "rxc",
"txa", "txb", "txc";
fsl,asrc-rate = <8000>;
@ -2515,8 +2515,8 @@
"asrck_8", "asrck_9", "asrck_a", "asrck_b",
"asrck_c", "asrck_d", "asrck_e", "asrck_f",
"spba";
dmas = <&edma3 0 0 0>, <&edma3 1 0 0>, <&edma3 2 0 0>,
<&edma3 3 0 1>, <&edma3 4 0 1>, <&edma3 5 0 1>;
dmas = <&edma1 0 0 0>, <&edma1 1 0 0>, <&edma1 2 0 0>,
<&edma1 3 0 1>, <&edma1 4 0 1>, <&edma1 5 0 1>;
dma-names = "rxa", "rxb", "rxc",
"txa", "txb", "txc";
fsl,asrc-rate = <8000>;
@ -2663,7 +2663,7 @@
<&clk IMX8QXP_AUD_ESAI_0_IPG>,
<&clk IMX8QXP_CLK_DUMMY>;
clock-names = "core", "extal", "fsys", "spba";
dmas = <&edma2 6 0 1>, <&edma2 7 0 0>;
dmas = <&edma0 6 0 1>, <&edma0 7 0 0>;
dma-names = "rx", "tx";
power-domains = <&pd_esai0>;
status = "disabled";
@ -2689,7 +2689,7 @@
"rxtx3", "rxtx4",
"rxtx5", "rxtx6",
"rxtx7", "spba";
dmas = <&edma2 8 0 5>, <&edma2 9 0 4>;
dmas = <&edma0 8 0 5>, <&edma0 9 0 4>;
dma-names = "rx", "tx";
power-domains = <&pd_spdif0>;
status = "disabled";