libnvdimm, pmem: Do not flush power-fail protected CPU caches
This commit:5fdf8e5ba5
("libnvdimm: re-enable deep flush for pmem devices via fsync()") intended to make sure that deep flush was always available even on platforms which support a power-fail protected CPU cache. An unintended side effect of this change was that we also lost the ability to skip flushing CPU caches on those power-fail protected CPU cache. Fix this by skipping the low level cache flushing in dax_flush() if we have CPU caches which are power-fail protected. The user can still override this behavior by manually setting the write_cache state of a namespace. See libndctl's ndctl_namespace_write_cache_is_enabled(), ndctl_namespace_enable_write_cache() and ndctl_namespace_disable_write_cache() functions. Cc: <stable@vger.kernel.org> Fixes:5fdf8e5ba5
("libnvdimm: re-enable deep flush for pmem devices via fsync()") Signed-off-by: Ross Zwisler <ross.zwisler@linux.intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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@ -1132,7 +1132,8 @@ EXPORT_SYMBOL_GPL(nvdimm_has_flush);
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int nvdimm_has_cache(struct nd_region *nd_region)
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{
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return is_nd_pmem(&nd_region->dev);
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return is_nd_pmem(&nd_region->dev) &&
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!test_bit(ND_REGION_PERSIST_CACHE, &nd_region->flags);
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}
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EXPORT_SYMBOL_GPL(nvdimm_has_cache);
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