Merge branch for-rmk-devel of git://aeryn.fluff.org.uk/bjdooks/linux into devel
This commit is contained in:
commit
547c32aeb5
|
@ -51,7 +51,7 @@ PIN Numbers
|
|||
-----------
|
||||
|
||||
Each pin has an unique number associated with it in regs-gpio.h,
|
||||
eg S3C2410_GPA0 or S3C2410_GPF1. These defines are used to tell
|
||||
eg S3C2410_GPA(0) or S3C2410_GPF(1). These defines are used to tell
|
||||
the GPIO functions which pin is to be used.
|
||||
|
||||
|
||||
|
@ -65,11 +65,11 @@ Configuring a pin
|
|||
|
||||
Eg:
|
||||
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
|
||||
|
||||
which would turn GPA0 into the lowest Address line A0, and set
|
||||
GPE8 to be connected to the SDIO/MMC controller's SDDAT1 line.
|
||||
which would turn GPA(0) into the lowest Address line A0, and set
|
||||
GPE(8) to be connected to the SDIO/MMC controller's SDDAT1 line.
|
||||
|
||||
|
||||
Reading the current configuration
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||||
|
|
|
@ -4,6 +4,13 @@ config ARM_GIC
|
|||
config ARM_VIC
|
||||
bool
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||||
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||||
config ARM_VIC_NR
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||||
int
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||||
default 2
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||||
help
|
||||
The maximum number of VICs available in the system, for
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||||
power management.
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||||
|
||||
config ICST525
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||||
bool
|
||||
|
||||
|
|
|
@ -21,6 +21,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/list.h>
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||||
#include <linux/io.h>
|
||||
#include <linux/sysdev.h>
|
||||
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
|
@ -39,11 +40,219 @@ static void vic_unmask_irq(unsigned int irq)
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|||
writel(1 << irq, base + VIC_INT_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
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* vic_init2 - common initialisation code
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* @base: Base of the VIC.
|
||||
*
|
||||
* Common initialisation code for registeration
|
||||
* and resume.
|
||||
*/
|
||||
static void vic_init2(void __iomem *base)
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||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
|
||||
writel(VIC_VECT_CNTL_ENABLE | i, reg);
|
||||
}
|
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|
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writel(32, base + VIC_PL190_DEF_VECT_ADDR);
|
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}
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|
||||
#if defined(CONFIG_PM)
|
||||
/**
|
||||
* struct vic_device - VIC PM device
|
||||
* @sysdev: The system device which is registered.
|
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* @irq: The IRQ number for the base of the VIC.
|
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* @base: The register base for the VIC.
|
||||
* @resume_sources: A bitmask of interrupts for resume.
|
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* @resume_irqs: The IRQs enabled for resume.
|
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* @int_select: Save for VIC_INT_SELECT.
|
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* @int_enable: Save for VIC_INT_ENABLE.
|
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* @soft_int: Save for VIC_INT_SOFT.
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* @protect: Save for VIC_PROTECT.
|
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*/
|
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struct vic_device {
|
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struct sys_device sysdev;
|
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|
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void __iomem *base;
|
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int irq;
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u32 resume_sources;
|
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u32 resume_irqs;
|
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u32 int_select;
|
||||
u32 int_enable;
|
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u32 soft_int;
|
||||
u32 protect;
|
||||
};
|
||||
|
||||
/* we cannot allocate memory when VICs are initially registered */
|
||||
static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
|
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|
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static inline struct vic_device *to_vic(struct sys_device *sys)
|
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{
|
||||
return container_of(sys, struct vic_device, sysdev);
|
||||
}
|
||||
|
||||
static int vic_id;
|
||||
|
||||
static int vic_class_resume(struct sys_device *dev)
|
||||
{
|
||||
struct vic_device *vic = to_vic(dev);
|
||||
void __iomem *base = vic->base;
|
||||
|
||||
printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
|
||||
|
||||
/* re-initialise static settings */
|
||||
vic_init2(base);
|
||||
|
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writel(vic->int_select, base + VIC_INT_SELECT);
|
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writel(vic->protect, base + VIC_PROTECT);
|
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|
||||
/* set the enabled ints and then clear the non-enabled */
|
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writel(vic->int_enable, base + VIC_INT_ENABLE);
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writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
|
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|
||||
/* and the same for the soft-int register */
|
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|
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writel(vic->soft_int, base + VIC_INT_SOFT);
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writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
|
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|
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return 0;
|
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}
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|
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static int vic_class_suspend(struct sys_device *dev, pm_message_t state)
|
||||
{
|
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struct vic_device *vic = to_vic(dev);
|
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void __iomem *base = vic->base;
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|
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printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
|
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|
||||
vic->int_select = readl(base + VIC_INT_SELECT);
|
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vic->int_enable = readl(base + VIC_INT_ENABLE);
|
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vic->soft_int = readl(base + VIC_INT_SOFT);
|
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vic->protect = readl(base + VIC_PROTECT);
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|
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/* set the interrupts (if any) that are used for
|
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* resuming the system */
|
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|
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writel(vic->resume_irqs, base + VIC_INT_ENABLE);
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writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
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return 0;
|
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}
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|
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struct sysdev_class vic_class = {
|
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.name = "vic",
|
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.suspend = vic_class_suspend,
|
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.resume = vic_class_resume,
|
||||
};
|
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|
||||
/**
|
||||
* vic_pm_register - Register a VIC for later power management control
|
||||
* @base: The base address of the VIC.
|
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* @irq: The base IRQ for the VIC.
|
||||
* @resume_sources: bitmask of interrupts allowed for resume sources.
|
||||
*
|
||||
* Register the VIC with the system device tree so that it can be notified
|
||||
* of suspend and resume requests and ensure that the correct actions are
|
||||
* taken to re-instate the settings on resume.
|
||||
*/
|
||||
static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
|
||||
{
|
||||
struct vic_device *v;
|
||||
|
||||
if (vic_id >= ARRAY_SIZE(vic_devices))
|
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printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
|
||||
else {
|
||||
v = &vic_devices[vic_id];
|
||||
v->base = base;
|
||||
v->resume_sources = resume_sources;
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||||
v->irq = irq;
|
||||
vic_id++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* vic_pm_init - initicall to register VIC pm
|
||||
*
|
||||
* This is called via late_initcall() to register
|
||||
* the resources for the VICs due to the early
|
||||
* nature of the VIC's registration.
|
||||
*/
|
||||
static int __init vic_pm_init(void)
|
||||
{
|
||||
struct vic_device *dev = vic_devices;
|
||||
int err;
|
||||
int id;
|
||||
|
||||
if (vic_id == 0)
|
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return 0;
|
||||
|
||||
err = sysdev_class_register(&vic_class);
|
||||
if (err) {
|
||||
printk(KERN_ERR "%s: cannot register class\n", __func__);
|
||||
return err;
|
||||
}
|
||||
|
||||
for (id = 0; id < vic_id; id++, dev++) {
|
||||
dev->sysdev.id = id;
|
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dev->sysdev.cls = &vic_class;
|
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|
||||
err = sysdev_register(&dev->sysdev);
|
||||
if (err) {
|
||||
printk(KERN_ERR "%s: failed to register device\n",
|
||||
__func__);
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||||
return err;
|
||||
}
|
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}
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||||
|
||||
return 0;
|
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}
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|
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late_initcall(vic_pm_init);
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static struct vic_device *vic_from_irq(unsigned int irq)
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{
|
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struct vic_device *v = vic_devices;
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unsigned int base_irq = irq & ~31;
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int id;
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|
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for (id = 0; id < vic_id; id++, v++) {
|
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if (v->irq == base_irq)
|
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return v;
|
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}
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|
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return NULL;
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}
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|
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static int vic_set_wake(unsigned int irq, unsigned int on)
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{
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struct vic_device *v = vic_from_irq(irq);
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unsigned int off = irq & 31;
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|
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if (!v)
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return -EINVAL;
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|
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if (on)
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v->resume_irqs |= 1 << off;
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else
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v->resume_irqs &= ~(1 << off);
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|
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return 0;
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}
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#else
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static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
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|
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#define vic_set_wake NULL
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#endif /* CONFIG_PM */
|
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|
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static struct irq_chip vic_chip = {
|
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.name = "VIC",
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.ack = vic_mask_irq,
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.mask = vic_mask_irq,
|
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.unmask = vic_unmask_irq,
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.set_wake = vic_set_wake,
|
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};
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|
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/**
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|
@ -51,9 +260,10 @@ static struct irq_chip vic_chip = {
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|||
* @base: iomem base address
|
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* @irq_start: starting interrupt number, must be muliple of 32
|
||||
* @vic_sources: bitmask of interrupt sources to allow
|
||||
* @resume_sources: bitmask of interrupt sources to allow for resume
|
||||
*/
|
||||
void __init vic_init(void __iomem *base, unsigned int irq_start,
|
||||
u32 vic_sources)
|
||||
u32 vic_sources, u32 resume_sources)
|
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{
|
||||
unsigned int i;
|
||||
|
||||
|
@ -77,12 +287,7 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
|
|||
writel(value, base + VIC_PL190_VECT_ADDR);
|
||||
}
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
|
||||
writel(VIC_VECT_CNTL_ENABLE | i, reg);
|
||||
}
|
||||
|
||||
writel(32, base + VIC_PL190_DEF_VECT_ADDR);
|
||||
vic_init2(base);
|
||||
|
||||
for (i = 0; i < 32; i++) {
|
||||
if (vic_sources & (1 << i)) {
|
||||
|
@ -94,4 +299,6 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
|
|||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
}
|
||||
|
||||
vic_pm_register(base, irq_start, resume_sources);
|
||||
}
|
||||
|
|
138
arch/arm/include/asm/hardware/pl080.h
Normal file
138
arch/arm/include/asm/hardware/pl080.h
Normal file
|
@ -0,0 +1,138 @@
|
|||
/* arch/arm/include/asm/hardware/pl080.h
|
||||
*
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* http://armlinux.simtec.co.uk/
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* ARM PrimeCell PL080 DMA controller
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/* Note, there are some Samsung updates to this controller block which
|
||||
* make it not entierly compatible with the PL080 specification from
|
||||
* ARM. When in doubt, check the Samsung documentation first.
|
||||
*
|
||||
* The Samsung defines are PL080S, and add an extra controll register,
|
||||
* the ability to move more than 2^11 counts of data and some extra
|
||||
* OneNAND features.
|
||||
*/
|
||||
|
||||
#define PL080_INT_STATUS (0x00)
|
||||
#define PL080_TC_STATUS (0x04)
|
||||
#define PL080_TC_CLEAR (0x08)
|
||||
#define PL080_ERR_STATUS (0x0C)
|
||||
#define PL080_ERR_CLEAR (0x10)
|
||||
#define PL080_RAW_TC_STATUS (0x14)
|
||||
#define PL080_RAW_ERR_STATUS (0x18)
|
||||
#define PL080_EN_CHAN (0x1c)
|
||||
#define PL080_SOFT_BREQ (0x20)
|
||||
#define PL080_SOFT_SREQ (0x24)
|
||||
#define PL080_SOFT_LBREQ (0x28)
|
||||
#define PL080_SOFT_LSREQ (0x2C)
|
||||
|
||||
#define PL080_CONFIG (0x30)
|
||||
#define PL080_CONFIG_M2_BE (1 << 2)
|
||||
#define PL080_CONFIG_M1_BE (1 << 1)
|
||||
#define PL080_CONFIG_ENABLE (1 << 0)
|
||||
|
||||
#define PL080_SYNC (0x34)
|
||||
|
||||
/* Per channel configuration registers */
|
||||
|
||||
#define PL008_Cx_STRIDE (0x20)
|
||||
#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20)))
|
||||
#define PL080_Cx_SRC_ADDR(x) ((0x100 + (x * 0x20)))
|
||||
#define PL080_Cx_DST_ADDR(x) ((0x104 + (x * 0x20)))
|
||||
#define PL080_Cx_LLI(x) ((0x108 + (x * 0x20)))
|
||||
#define PL080_Cx_CONTROL(x) ((0x10C + (x * 0x20)))
|
||||
#define PL080_Cx_CONFIG(x) ((0x110 + (x * 0x20)))
|
||||
#define PL080S_Cx_CONTROL2(x) ((0x110 + (x * 0x20)))
|
||||
#define PL080S_Cx_CONFIG(x) ((0x114 + (x * 0x20)))
|
||||
|
||||
#define PL080_CH_SRC_ADDR (0x00)
|
||||
#define PL080_CH_DST_ADDR (0x04)
|
||||
#define PL080_CH_LLI (0x08)
|
||||
#define PL080_CH_CONTROL (0x0C)
|
||||
#define PL080_CH_CONFIG (0x10)
|
||||
#define PL080S_CH_CONTROL2 (0x10)
|
||||
#define PL080S_CH_CONFIG (0x14)
|
||||
|
||||
#define PL080_LLI_ADDR_MASK (0x3fffffff << 2)
|
||||
#define PL080_LLI_ADDR_SHIFT (2)
|
||||
#define PL080_LLI_LM_AHB2 (1 << 0)
|
||||
|
||||
#define PL080_CONTROL_TC_IRQ_EN (1 << 31)
|
||||
#define PL080_CONTROL_PROT_MASK (0x7 << 28)
|
||||
#define PL080_CONTROL_PROT_SHIFT (28)
|
||||
#define PL080_CONTROL_PROT_SYS (1 << 28)
|
||||
#define PL080_CONTROL_DST_INCR (1 << 27)
|
||||
#define PL080_CONTROL_SRC_INCR (1 << 26)
|
||||
#define PL080_CONTROL_DST_AHB2 (1 << 25)
|
||||
#define PL080_CONTROL_SRC_AHB2 (1 << 24)
|
||||
#define PL080_CONTROL_DWIDTH_MASK (0x7 << 21)
|
||||
#define PL080_CONTROL_DWIDTH_SHIFT (21)
|
||||
#define PL080_CONTROL_SWIDTH_MASK (0x7 << 18)
|
||||
#define PL080_CONTROL_SWIDTH_SHIFT (18)
|
||||
#define PL080_CONTROL_DB_SIZE_MASK (0x7 << 15)
|
||||
#define PL080_CONTROL_DB_SIZE_SHIFT (15)
|
||||
#define PL080_CONTROL_SB_SIZE_MASK (0x7 << 12)
|
||||
#define PL080_CONTROL_SB_SIZE_SHIFT (12)
|
||||
#define PL080_CONTROL_TRANSFER_SIZE_MASK (0xfff << 0)
|
||||
#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0)
|
||||
|
||||
#define PL080_BSIZE_1 (0x0)
|
||||
#define PL080_BSIZE_4 (0x1)
|
||||
#define PL080_BSIZE_8 (0x2)
|
||||
#define PL080_BSIZE_16 (0x3)
|
||||
#define PL080_BSIZE_32 (0x4)
|
||||
#define PL080_BSIZE_64 (0x5)
|
||||
#define PL080_BSIZE_128 (0x6)
|
||||
#define PL080_BSIZE_256 (0x7)
|
||||
|
||||
#define PL080_WIDTH_8BIT (0x0)
|
||||
#define PL080_WIDTH_16BIT (0x1)
|
||||
#define PL080_WIDTH_32BIT (0x2)
|
||||
|
||||
#define PL080_CONFIG_HALT (1 << 18)
|
||||
#define PL080_CONFIG_ACTIVE (1 << 17) /* RO */
|
||||
#define PL080_CONFIG_LOCK (1 << 16)
|
||||
#define PL080_CONFIG_TC_IRQ_MASK (1 << 15)
|
||||
#define PL080_CONFIG_ERR_IRQ_MASK (1 << 14)
|
||||
#define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11)
|
||||
#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11)
|
||||
#define PL080_CONFIG_DST_SEL_MASK (0xf << 6)
|
||||
#define PL080_CONFIG_DST_SEL_SHIFT (6)
|
||||
#define PL080_CONFIG_SRC_SEL_MASK (0xf << 1)
|
||||
#define PL080_CONFIG_SRC_SEL_SHIFT (1)
|
||||
#define PL080_CONFIG_ENABLE (1 << 0)
|
||||
|
||||
#define PL080_FLOW_MEM2MEM (0x0)
|
||||
#define PL080_FLOW_MEM2PER (0x1)
|
||||
#define PL080_FLOW_PER2MEM (0x2)
|
||||
#define PL080_FLOW_SRC2DST (0x3)
|
||||
#define PL080_FLOW_SRC2DST_DST (0x4)
|
||||
#define PL080_FLOW_MEM2PER_PER (0x5)
|
||||
#define PL080_FLOW_PER2MEM_PER (0x6)
|
||||
#define PL080_FLOW_SRC2DST_SRC (0x7)
|
||||
|
||||
/* DMA linked list chain structure */
|
||||
|
||||
struct pl080_lli {
|
||||
u32 src_addr;
|
||||
u32 dst_addr;
|
||||
u32 next_lli;
|
||||
u32 control0;
|
||||
};
|
||||
|
||||
struct pl080s_lli {
|
||||
u32 src_addr;
|
||||
u32 dst_addr;
|
||||
u32 next_lli;
|
||||
u32 control0;
|
||||
u32 control1;
|
||||
};
|
||||
|
|
@ -41,7 +41,7 @@
|
|||
#define VIC_PL192_VECT_ADDR 0xF00
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources);
|
||||
void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
@ -362,8 +362,8 @@ void __init ep93xx_init_irq(void)
|
|||
{
|
||||
int gpio_irq;
|
||||
|
||||
vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK);
|
||||
vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK);
|
||||
vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
|
||||
vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
|
||||
|
||||
for (gpio_irq = gpio_to_irq(0);
|
||||
gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
|
||||
|
|
|
@ -168,7 +168,7 @@ void __init netx_init_irq(void)
|
|||
{
|
||||
int irq;
|
||||
|
||||
vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0);
|
||||
vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0);
|
||||
|
||||
for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
|
||||
set_irq_chip(irq, &netx_hif_chip);
|
||||
|
|
|
@ -33,10 +33,10 @@
|
|||
|
||||
int s3c2400_gpio_getirq(unsigned int pin)
|
||||
{
|
||||
if (pin < S3C2410_GPE0 || pin > S3C2400_GPE7_EINT7)
|
||||
return -1; /* not valid interrupts */
|
||||
if (pin < S3C2410_GPE(0) || pin > S3C2400_GPE(7))
|
||||
return -EINVAL; /* not valid interrupts */
|
||||
|
||||
return (pin - S3C2410_GPE0) + IRQ_EINT0;
|
||||
return (pin - S3C2410_GPE(0)) + IRQ_EINT0;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(s3c2400_gpio_getirq);
|
||||
|
|
|
@ -59,6 +59,7 @@ config ARCH_H1940
|
|||
bool "IPAQ H1940"
|
||||
select CPU_S3C2410
|
||||
select PM_H1940 if PM
|
||||
select S3C_DEV_USB_HOST
|
||||
help
|
||||
Say Y here if you are using the HP IPAQ H1940
|
||||
|
||||
|
@ -70,6 +71,7 @@ config PM_H1940
|
|||
config MACH_N30
|
||||
bool "Acer N30 family"
|
||||
select CPU_S3C2410
|
||||
select S3C_DEV_USB_HOST
|
||||
help
|
||||
Say Y here if you want suppt for the Acer N30, Acer N35,
|
||||
Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs.
|
||||
|
@ -82,6 +84,7 @@ config ARCH_BAST
|
|||
select MACH_BAST_IDE
|
||||
select S3C24XX_DCLK
|
||||
select ISA
|
||||
select S3C_DEV_USB_HOST
|
||||
help
|
||||
Say Y here if you are using the Simtec Electronics EB2410ITX
|
||||
development board (also known as BAST)
|
||||
|
@ -89,6 +92,7 @@ config ARCH_BAST
|
|||
config MACH_OTOM
|
||||
bool "NexVision OTOM Board"
|
||||
select CPU_S3C2410
|
||||
select S3C_DEV_USB_HOST
|
||||
help
|
||||
Say Y here if you are using the Nex Vision OTOM board
|
||||
|
||||
|
@ -96,6 +100,7 @@ config MACH_AML_M5900
|
|||
bool "AML M5900 Series"
|
||||
select CPU_S3C2410
|
||||
select PM_SIMTEC if PM
|
||||
select S3C_DEV_USB_HOST
|
||||
help
|
||||
Say Y here if you are using the American Microsystems M5900 Series
|
||||
<http://www.amltd.com>
|
||||
|
@ -111,6 +116,7 @@ config BAST_PC104_IRQ
|
|||
config MACH_TCT_HAMMER
|
||||
bool "TCT Hammer Board"
|
||||
select CPU_S3C2410
|
||||
select S3C_DEV_USB_HOST
|
||||
help
|
||||
Say Y here if you are using the TinCanTools Hammer Board
|
||||
<http://www.tincantools.com>
|
||||
|
@ -122,12 +128,14 @@ config MACH_VR1000
|
|||
select SIMTEC_NOR
|
||||
select MACH_BAST_IDE
|
||||
select CPU_S3C2410
|
||||
select S3C_DEV_USB_HOST
|
||||
help
|
||||
Say Y here if you are using the Thorcom VR1000 board.
|
||||
|
||||
config MACH_QT2410
|
||||
bool "QT2410"
|
||||
select CPU_S3C2410
|
||||
select S3C_DEV_USB_HOST
|
||||
help
|
||||
Say Y here if you are using the Armzone QT2410
|
||||
|
||||
|
|
|
@ -17,14 +17,16 @@
|
|||
#include <linux/sysdev.h>
|
||||
#include <linux/serial_core.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/dma.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/dma.h>
|
||||
#include <plat/dma-plat.h>
|
||||
|
||||
#include <plat/regs-serial.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <plat/regs-ac97.h>
|
||||
#include <plat/regs-dma.h>
|
||||
#include <mach/regs-mem.h>
|
||||
#include <mach/regs-lcd.h>
|
||||
#include <mach/regs-sdi.h>
|
||||
|
|
|
@ -39,12 +39,12 @@ int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
|
|||
unsigned long flags;
|
||||
unsigned long val;
|
||||
|
||||
if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15)
|
||||
return -1;
|
||||
if (pin < S3C2410_GPG(8) || pin > S3C2410_GPG(15))
|
||||
return -EINVAL;
|
||||
|
||||
config &= 0xff;
|
||||
|
||||
pin -= S3C2410_GPG8;
|
||||
pin -= S3C2410_GPG(8);
|
||||
reg += pin & ~3;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
|
|
@ -16,6 +16,8 @@
|
|||
#include <linux/string.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/h1940-latch.h>
|
||||
|
@ -41,9 +43,9 @@ static void h1940bt_enable(int on)
|
|||
h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER);
|
||||
/* Reset the chip */
|
||||
mdelay(10);
|
||||
s3c2410_gpio_setpin(S3C2410_GPH1, 1);
|
||||
s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
|
||||
mdelay(10);
|
||||
s3c2410_gpio_setpin(S3C2410_GPH1, 0);
|
||||
s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
|
||||
|
||||
state = 1;
|
||||
}
|
||||
|
@ -52,9 +54,9 @@ static void h1940bt_enable(int on)
|
|||
led_trigger_event(bt_led_trigger, 0);
|
||||
#endif
|
||||
|
||||
s3c2410_gpio_setpin(S3C2410_GPH1, 1);
|
||||
s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
|
||||
mdelay(10);
|
||||
s3c2410_gpio_setpin(S3C2410_GPH1, 0);
|
||||
s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
|
||||
mdelay(10);
|
||||
h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0);
|
||||
|
||||
|
@ -87,14 +89,14 @@ static DEVICE_ATTR(enable, 0644,
|
|||
static int __init h1940bt_probe(struct platform_device *pdev)
|
||||
{
|
||||
/* Configures BT serial port GPIOs */
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPH0, S3C2410_GPH0_nCTS0);
|
||||
s3c2410_gpio_pullup(S3C2410_GPH0, 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPH1, S3C2410_GPH1_OUTP);
|
||||
s3c2410_gpio_pullup(S3C2410_GPH1, 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPH2, S3C2410_GPH2_TXD0);
|
||||
s3c2410_gpio_pullup(S3C2410_GPH2, 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPH3, S3C2410_GPH3_RXD0);
|
||||
s3c2410_gpio_pullup(S3C2410_GPH3, 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0);
|
||||
s3c2410_gpio_pullup(S3C2410_GPH(0), 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT);
|
||||
s3c2410_gpio_pullup(S3C2410_GPH(1), 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0);
|
||||
s3c2410_gpio_pullup(S3C2410_GPH(2), 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0);
|
||||
s3c2410_gpio_pullup(S3C2410_GPH(3), 1);
|
||||
|
||||
#ifdef CONFIG_LEDS_H1940
|
||||
led_trigger_register_simple("h1940-bluetooth", &bt_led_trigger);
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
* Copyright (C) 2003,2004,2006 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* Samsung S3C241XX DMA support
|
||||
* Samsung S3C24XX DMA support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
@ -13,8 +13,8 @@
|
|||
#ifndef __ASM_ARCH_DMA_H
|
||||
#define __ASM_ARCH_DMA_H __FILE__
|
||||
|
||||
#include <plat/dma.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
|
||||
|
||||
|
@ -55,9 +55,9 @@ enum dma_ch {
|
|||
|
||||
/* we have 4 dma channels */
|
||||
#ifndef CONFIG_CPU_S3C2443
|
||||
#define S3C2410_DMA_CHANNELS (4)
|
||||
#define S3C_DMA_CHANNELS (4)
|
||||
#else
|
||||
#define S3C2410_DMA_CHANNELS (6)
|
||||
#define S3C_DMA_CHANNELS (6)
|
||||
#endif
|
||||
|
||||
/* types */
|
||||
|
@ -68,7 +68,6 @@ enum s3c2410_dma_state {
|
|||
S3C2410_DMA_PAUSED
|
||||
};
|
||||
|
||||
|
||||
/* enum s3c2410_dma_loadst
|
||||
*
|
||||
* This represents the state of the DMA engine, wrt to the loaded / running
|
||||
|
@ -104,32 +103,6 @@ enum s3c2410_dma_loadst {
|
|||
S3C2410_DMALOAD_1LOADED_1RUNNING,
|
||||
};
|
||||
|
||||
enum s3c2410_dma_buffresult {
|
||||
S3C2410_RES_OK,
|
||||
S3C2410_RES_ERR,
|
||||
S3C2410_RES_ABORT
|
||||
};
|
||||
|
||||
enum s3c2410_dmasrc {
|
||||
S3C2410_DMASRC_HW, /* source is memory */
|
||||
S3C2410_DMASRC_MEM /* source is hardware */
|
||||
};
|
||||
|
||||
/* enum s3c2410_chan_op
|
||||
*
|
||||
* operation codes passed to the DMA code by the user, and also used
|
||||
* to inform the current channel owner of any changes to the system state
|
||||
*/
|
||||
|
||||
enum s3c2410_chan_op {
|
||||
S3C2410_DMAOP_START,
|
||||
S3C2410_DMAOP_STOP,
|
||||
S3C2410_DMAOP_PAUSE,
|
||||
S3C2410_DMAOP_RESUME,
|
||||
S3C2410_DMAOP_FLUSH,
|
||||
S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
|
||||
S3C2410_DMAOP_STARTED, /* indicate channel started */
|
||||
};
|
||||
|
||||
/* flags */
|
||||
|
||||
|
@ -139,17 +112,14 @@ enum s3c2410_chan_op {
|
|||
|
||||
/* dma buffer */
|
||||
|
||||
struct s3c2410_dma_client {
|
||||
char *name;
|
||||
};
|
||||
struct s3c2410_dma_buf;
|
||||
|
||||
/* s3c2410_dma_buf_s
|
||||
/* s3c2410_dma_buf
|
||||
*
|
||||
* internally used buffer structure to describe a queued or running
|
||||
* buffer.
|
||||
*/
|
||||
|
||||
struct s3c2410_dma_buf;
|
||||
struct s3c2410_dma_buf {
|
||||
struct s3c2410_dma_buf *next;
|
||||
int magic; /* magic */
|
||||
|
@ -161,20 +131,6 @@ struct s3c2410_dma_buf {
|
|||
|
||||
/* [1] is this updated for both recv/send modes? */
|
||||
|
||||
struct s3c2410_dma_chan;
|
||||
|
||||
/* s3c2410_dma_cbfn_t
|
||||
*
|
||||
* buffer callback routine type
|
||||
*/
|
||||
|
||||
typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
|
||||
void *buf, int size,
|
||||
enum s3c2410_dma_buffresult result);
|
||||
|
||||
typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
|
||||
enum s3c2410_chan_op );
|
||||
|
||||
struct s3c2410_dma_stats {
|
||||
unsigned long loads;
|
||||
unsigned long timeout_longest;
|
||||
|
@ -206,10 +162,10 @@ struct s3c2410_dma_chan {
|
|||
|
||||
/* channel configuration */
|
||||
enum s3c2410_dmasrc source;
|
||||
enum dma_ch req_ch;
|
||||
unsigned long dev_addr;
|
||||
unsigned long load_timeout;
|
||||
unsigned int flags; /* channel flags */
|
||||
unsigned int hw_cfg; /* last hw config */
|
||||
|
||||
struct s3c24xx_dma_map *map; /* channel hw maps */
|
||||
|
||||
|
@ -236,213 +192,6 @@ struct s3c2410_dma_chan {
|
|||
struct sys_device dev;
|
||||
};
|
||||
|
||||
/* the currently allocated channel information */
|
||||
extern struct s3c2410_dma_chan s3c2410_chans[];
|
||||
|
||||
/* note, we don't really use dma_device_t at the moment */
|
||||
typedef unsigned long dma_device_t;
|
||||
|
||||
/* functions --------------------------------------------------------------- */
|
||||
|
||||
/* s3c2410_dma_request
|
||||
*
|
||||
* request a dma channel exclusivley
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_request(unsigned int channel,
|
||||
struct s3c2410_dma_client *, void *dev);
|
||||
|
||||
|
||||
/* s3c2410_dma_ctrl
|
||||
*
|
||||
* change the state of the dma channel
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
|
||||
|
||||
/* s3c2410_dma_setflags
|
||||
*
|
||||
* set the channel's flags to a given state
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_setflags(unsigned int channel,
|
||||
unsigned int flags);
|
||||
|
||||
/* s3c2410_dma_free
|
||||
*
|
||||
* free the dma channel (will also abort any outstanding operations)
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
|
||||
|
||||
/* s3c2410_dma_enqueue
|
||||
*
|
||||
* place the given buffer onto the queue of operations for the channel.
|
||||
* The buffer must be allocated from dma coherent memory, or the Dcache/WB
|
||||
* drained before the buffer is given to the DMA system.
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
|
||||
dma_addr_t data, int size);
|
||||
|
||||
/* s3c2410_dma_config
|
||||
*
|
||||
* configure the dma channel
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_config(unsigned int channel, int xferunit, int dcon);
|
||||
|
||||
/* s3c2410_dma_devconfig
|
||||
*
|
||||
* configure the device we're talking to
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
|
||||
int hwcfg, unsigned long devaddr);
|
||||
|
||||
/* s3c2410_dma_getposition
|
||||
*
|
||||
* get the position that the dma transfer is currently at
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_getposition(unsigned int channel,
|
||||
dma_addr_t *src, dma_addr_t *dest);
|
||||
|
||||
extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
|
||||
extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
|
||||
|
||||
/* DMA Register definitions */
|
||||
|
||||
#define S3C2410_DMA_DISRC (0x00)
|
||||
#define S3C2410_DMA_DISRCC (0x04)
|
||||
#define S3C2410_DMA_DIDST (0x08)
|
||||
#define S3C2410_DMA_DIDSTC (0x0C)
|
||||
#define S3C2410_DMA_DCON (0x10)
|
||||
#define S3C2410_DMA_DSTAT (0x14)
|
||||
#define S3C2410_DMA_DCSRC (0x18)
|
||||
#define S3C2410_DMA_DCDST (0x1C)
|
||||
#define S3C2410_DMA_DMASKTRIG (0x20)
|
||||
#define S3C2412_DMA_DMAREQSEL (0x24)
|
||||
#define S3C2443_DMA_DMAREQSEL (0x24)
|
||||
|
||||
#define S3C2410_DISRCC_INC (1<<0)
|
||||
#define S3C2410_DISRCC_APB (1<<1)
|
||||
|
||||
#define S3C2410_DMASKTRIG_STOP (1<<2)
|
||||
#define S3C2410_DMASKTRIG_ON (1<<1)
|
||||
#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
|
||||
|
||||
#define S3C2410_DCON_DEMAND (0<<31)
|
||||
#define S3C2410_DCON_HANDSHAKE (1<<31)
|
||||
#define S3C2410_DCON_SYNC_PCLK (0<<30)
|
||||
#define S3C2410_DCON_SYNC_HCLK (1<<30)
|
||||
|
||||
#define S3C2410_DCON_INTREQ (1<<29)
|
||||
|
||||
#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
|
||||
#define S3C2410_DCON_CH0_UART0 (1<<24)
|
||||
#define S3C2410_DCON_CH0_SDI (2<<24)
|
||||
#define S3C2410_DCON_CH0_TIMER (3<<24)
|
||||
#define S3C2410_DCON_CH0_USBEP1 (4<<24)
|
||||
|
||||
#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
|
||||
#define S3C2410_DCON_CH1_UART1 (1<<24)
|
||||
#define S3C2410_DCON_CH1_I2SSDI (2<<24)
|
||||
#define S3C2410_DCON_CH1_SPI (3<<24)
|
||||
#define S3C2410_DCON_CH1_USBEP2 (4<<24)
|
||||
|
||||
#define S3C2410_DCON_CH2_I2SSDO (0<<24)
|
||||
#define S3C2410_DCON_CH2_I2SSDI (1<<24)
|
||||
#define S3C2410_DCON_CH2_SDI (2<<24)
|
||||
#define S3C2410_DCON_CH2_TIMER (3<<24)
|
||||
#define S3C2410_DCON_CH2_USBEP3 (4<<24)
|
||||
|
||||
#define S3C2410_DCON_CH3_UART2 (0<<24)
|
||||
#define S3C2410_DCON_CH3_SDI (1<<24)
|
||||
#define S3C2410_DCON_CH3_SPI (2<<24)
|
||||
#define S3C2410_DCON_CH3_TIMER (3<<24)
|
||||
#define S3C2410_DCON_CH3_USBEP4 (4<<24)
|
||||
|
||||
#define S3C2410_DCON_SRCSHIFT (24)
|
||||
#define S3C2410_DCON_SRCMASK (7<<24)
|
||||
|
||||
#define S3C2410_DCON_BYTE (0<<20)
|
||||
#define S3C2410_DCON_HALFWORD (1<<20)
|
||||
#define S3C2410_DCON_WORD (2<<20)
|
||||
|
||||
#define S3C2410_DCON_AUTORELOAD (0<<22)
|
||||
#define S3C2410_DCON_NORELOAD (1<<22)
|
||||
#define S3C2410_DCON_HWTRIG (1<<23)
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2440
|
||||
#define S3C2440_DIDSTC_CHKINT (1<<2)
|
||||
|
||||
#define S3C2440_DCON_CH0_I2SSDO (5<<24)
|
||||
#define S3C2440_DCON_CH0_PCMIN (6<<24)
|
||||
|
||||
#define S3C2440_DCON_CH1_PCMOUT (5<<24)
|
||||
#define S3C2440_DCON_CH1_SDI (6<<24)
|
||||
|
||||
#define S3C2440_DCON_CH2_PCMIN (5<<24)
|
||||
#define S3C2440_DCON_CH2_MICIN (6<<24)
|
||||
|
||||
#define S3C2440_DCON_CH3_MICIN (5<<24)
|
||||
#define S3C2440_DCON_CH3_PCMOUT (6<<24)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2412
|
||||
|
||||
#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
|
||||
|
||||
#define S3C2412_DMAREQSEL_HW (1)
|
||||
|
||||
#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
|
||||
#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
|
||||
#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
|
||||
#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
|
||||
#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
|
||||
#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
|
||||
#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
|
||||
#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
|
||||
#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
|
||||
#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
|
||||
#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
|
||||
#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
|
||||
#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
|
||||
#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
|
||||
#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
|
||||
#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
|
||||
#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
|
||||
#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
|
||||
#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
|
||||
#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
|
||||
|
||||
#endif
|
||||
|
||||
#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1)
|
||||
|
||||
#define S3C2443_DMAREQSEL_HW (1)
|
||||
|
||||
#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
|
||||
#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
|
||||
#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
|
||||
#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
|
||||
#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
|
||||
#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
|
||||
#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
|
||||
#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
|
||||
#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
|
||||
#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
|
||||
#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
|
||||
#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
|
||||
#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
|
||||
#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
|
||||
#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
|
||||
#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
|
||||
#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
|
||||
#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
|
||||
#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
|
||||
#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
|
||||
#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
|
||||
|
||||
#endif /* __ASM_ARCH_DMA_H */
|
||||
|
|
|
@ -24,7 +24,7 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
|
|||
{
|
||||
struct s3c_gpio_chip *chip;
|
||||
|
||||
if (pin > S3C2410_GPG10)
|
||||
if (pin > S3C2410_GPG(10))
|
||||
return NULL;
|
||||
|
||||
chip = &s3c24xx_gpios[pin/32];
|
||||
|
|
103
arch/arm/mach-s3c2410/include/mach/gpio-fns.h
Normal file
103
arch/arm/mach-s3c2410/include/mach/gpio-fns.h
Normal file
|
@ -0,0 +1,103 @@
|
|||
/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
|
||||
*
|
||||
* Copyright (c) 2003,2009 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* S3C2410 - hardware
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/* These functions are in the to-be-removed category and it is strongly
|
||||
* encouraged not to use these in new code. They will be marked deprecated
|
||||
* very soon.
|
||||
*
|
||||
* Most of the functionality can be either replaced by the gpiocfg calls
|
||||
* for the s3c platform or by the generic GPIOlib API.
|
||||
*/
|
||||
|
||||
/* external functions for GPIO support
|
||||
*
|
||||
* These allow various different clients to access the same GPIO
|
||||
* registers without conflicting. If your driver only owns the entire
|
||||
* GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
|
||||
*/
|
||||
|
||||
/* s3c2410_gpio_cfgpin
|
||||
*
|
||||
* set the configuration of the given pin to the value passed.
|
||||
*
|
||||
* eg:
|
||||
* s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0);
|
||||
* s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
|
||||
*/
|
||||
|
||||
extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
|
||||
|
||||
extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
|
||||
|
||||
/* s3c2410_gpio_getirq
|
||||
*
|
||||
* turn the given pin number into the corresponding IRQ number
|
||||
*
|
||||
* returns:
|
||||
* < 0 = no interrupt for this pin
|
||||
* >=0 = interrupt number for the pin
|
||||
*/
|
||||
|
||||
extern int s3c2410_gpio_getirq(unsigned int pin);
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2400
|
||||
|
||||
extern int s3c2400_gpio_getirq(unsigned int pin);
|
||||
|
||||
#endif /* CONFIG_CPU_S3C2400 */
|
||||
|
||||
/* s3c2410_gpio_irqfilter
|
||||
*
|
||||
* set the irq filtering on the given pin
|
||||
*
|
||||
* on = 0 => disable filtering
|
||||
* 1 => enable filtering
|
||||
*
|
||||
* config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
|
||||
* width of filter (0 through 63)
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
|
||||
unsigned int config);
|
||||
|
||||
/* s3c2410_gpio_pullup
|
||||
*
|
||||
* configure the pull-up control on the given pin
|
||||
*
|
||||
* to = 1 => disable the pull-up
|
||||
* 0 => enable the pull-up
|
||||
*
|
||||
* eg;
|
||||
*
|
||||
* s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
|
||||
* s3c2410_gpio_pullup(S3C2410_GPE(8), 0);
|
||||
*/
|
||||
|
||||
extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
|
||||
|
||||
/* s3c2410_gpio_getpull
|
||||
*
|
||||
* Read the state of the pull-up on a given pin
|
||||
*
|
||||
* return:
|
||||
* < 0 => error code
|
||||
* 0 => enabled
|
||||
* 1 => disabled
|
||||
*/
|
||||
|
||||
extern int s3c2410_gpio_getpull(unsigned int pin);
|
||||
|
||||
extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
|
||||
|
||||
extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
|
|
@ -11,6 +11,9 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_GPIONRS_H
|
||||
#define __MACH_GPIONRS_H
|
||||
|
||||
#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
|
||||
|
||||
#define S3C2410_GPIO_BANKA (32*0)
|
||||
|
@ -21,3 +24,70 @@
|
|||
#define S3C2410_GPIO_BANKF (32*5)
|
||||
#define S3C2410_GPIO_BANKG (32*6)
|
||||
#define S3C2410_GPIO_BANKH (32*7)
|
||||
|
||||
/* GPIO bank sizes */
|
||||
#define S3C2410_GPIO_A_NR (32)
|
||||
#define S3C2410_GPIO_B_NR (32)
|
||||
#define S3C2410_GPIO_C_NR (32)
|
||||
#define S3C2410_GPIO_D_NR (32)
|
||||
#define S3C2410_GPIO_E_NR (32)
|
||||
#define S3C2410_GPIO_F_NR (32)
|
||||
#define S3C2410_GPIO_G_NR (32)
|
||||
#define S3C2410_GPIO_H_NR (32)
|
||||
|
||||
#if CONFIG_S3C_GPIO_SPACE != 0
|
||||
#error CONFIG_S3C_GPIO_SPACE cannot be zero at the moment
|
||||
#endif
|
||||
|
||||
#define S3C2410_GPIO_NEXT(__gpio) \
|
||||
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
enum s3c_gpio_number {
|
||||
S3C2410_GPIO_A_START = 0,
|
||||
S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A),
|
||||
S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B),
|
||||
S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C),
|
||||
S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D),
|
||||
S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
|
||||
S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
|
||||
S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
|
||||
};
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/* S3C2410 GPIO number definitions. */
|
||||
|
||||
#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr))
|
||||
#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr))
|
||||
#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr))
|
||||
#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr))
|
||||
#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr))
|
||||
#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr))
|
||||
#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr))
|
||||
#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr))
|
||||
|
||||
/* compatibility until drivers can be modified */
|
||||
|
||||
#define S3C2410_GPA0 S3C2410_GPA(0)
|
||||
#define S3C2410_GPA1 S3C2410_GPA(1)
|
||||
#define S3C2410_GPA3 S3C2410_GPA(3)
|
||||
#define S3C2410_GPA7 S3C2410_GPA(7)
|
||||
|
||||
#define S3C2410_GPE0 S3C2410_GPE(0)
|
||||
#define S3C2410_GPE1 S3C2410_GPE(1)
|
||||
#define S3C2410_GPE2 S3C2410_GPE(2)
|
||||
#define S3C2410_GPE3 S3C2410_GPE(3)
|
||||
#define S3C2410_GPE4 S3C2410_GPE(4)
|
||||
#define S3C2410_GPE5 S3C2410_GPE(5)
|
||||
#define S3C2410_GPE6 S3C2410_GPE(6)
|
||||
#define S3C2410_GPE7 S3C2410_GPE(7)
|
||||
#define S3C2410_GPE8 S3C2410_GPE(8)
|
||||
#define S3C2410_GPE9 S3C2410_GPE(9)
|
||||
#define S3C2410_GPE10 S3C2410_GPE(10)
|
||||
|
||||
#define S3C2410_GPH10 S3C2410_GPH(10)
|
||||
|
||||
#endif /* __MACH_GPIONRS_H */
|
||||
|
||||
|
|
|
@ -24,5 +24,6 @@
|
|||
|
||||
#include <asm-generic/gpio.h>
|
||||
#include <mach/gpio-nrs.h>
|
||||
#include <mach/gpio-fns.h>
|
||||
|
||||
#define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32)
|
||||
|
|
|
@ -15,101 +15,6 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* external functions for GPIO support
|
||||
*
|
||||
* These allow various different clients to access the same GPIO
|
||||
* registers without conflicting. If your driver only owns the entire
|
||||
* GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
|
||||
*/
|
||||
|
||||
/* s3c2410_gpio_cfgpin
|
||||
*
|
||||
* set the configuration of the given pin to the value passed.
|
||||
*
|
||||
* eg:
|
||||
* s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0);
|
||||
* s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
|
||||
*/
|
||||
|
||||
extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
|
||||
|
||||
extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
|
||||
|
||||
/* s3c2410_gpio_getirq
|
||||
*
|
||||
* turn the given pin number into the corresponding IRQ number
|
||||
*
|
||||
* returns:
|
||||
* < 0 = no interrupt for this pin
|
||||
* >=0 = interrupt number for the pin
|
||||
*/
|
||||
|
||||
extern int s3c2410_gpio_getirq(unsigned int pin);
|
||||
|
||||
/* s3c2410_gpio_irq2pin
|
||||
*
|
||||
* turn the given irq number into the corresponding GPIO number
|
||||
*
|
||||
* returns:
|
||||
* < 0 = no pin
|
||||
* >=0 = gpio pin number
|
||||
*/
|
||||
|
||||
extern int s3c2410_gpio_irq2pin(unsigned int irq);
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2400
|
||||
|
||||
extern int s3c2400_gpio_getirq(unsigned int pin);
|
||||
|
||||
#endif /* CONFIG_CPU_S3C2400 */
|
||||
|
||||
/* s3c2410_gpio_irqfilter
|
||||
*
|
||||
* set the irq filtering on the given pin
|
||||
*
|
||||
* on = 0 => disable filtering
|
||||
* 1 => enable filtering
|
||||
*
|
||||
* config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
|
||||
* width of filter (0 through 63)
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
|
||||
unsigned int config);
|
||||
|
||||
/* s3c2410_gpio_pullup
|
||||
*
|
||||
* configure the pull-up control on the given pin
|
||||
*
|
||||
* to = 1 => disable the pull-up
|
||||
* 0 => enable the pull-up
|
||||
*
|
||||
* eg;
|
||||
*
|
||||
* s3c2410_gpio_pullup(S3C2410_GPB0, 0);
|
||||
* s3c2410_gpio_pullup(S3C2410_GPE8, 0);
|
||||
*/
|
||||
|
||||
extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
|
||||
|
||||
/* s3c2410_gpio_getpull
|
||||
*
|
||||
* Read the state of the pull-up on a given pin
|
||||
*
|
||||
* return:
|
||||
* < 0 => error code
|
||||
* 0 => enabled
|
||||
* 1 => disabled
|
||||
*/
|
||||
|
||||
extern int s3c2410_gpio_getpull(unsigned int pin);
|
||||
|
||||
extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
|
||||
|
||||
extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
|
||||
|
||||
extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2440
|
||||
|
|
|
@ -84,7 +84,6 @@
|
|||
|
||||
#define S3C24XX_PA_IRQ S3C2410_PA_IRQ
|
||||
#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
|
||||
#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST
|
||||
#define S3C24XX_PA_DMA S3C2410_PA_DMA
|
||||
#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
|
||||
#define S3C24XX_PA_LCD S3C2410_PA_LCD
|
||||
|
@ -102,6 +101,7 @@
|
|||
|
||||
#define S3C_PA_IIC S3C2410_PA_IIC
|
||||
#define S3C_PA_UART S3C24XX_PA_UART
|
||||
#define S3C_PA_USBHOST S3C2410_PA_USBHOST
|
||||
#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC
|
||||
|
||||
#endif /* __ASM_ARCH_MAP_H */
|
||||
|
|
|
@ -69,104 +69,58 @@
|
|||
#define S3C2400_GPACON S3C2410_GPIOREG(0x00)
|
||||
#define S3C2400_GPADAT S3C2410_GPIOREG(0x04)
|
||||
|
||||
#define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)
|
||||
#define S3C2410_GPA0_OUT (0<<0)
|
||||
#define S3C2410_GPA0_ADDR0 (1<<0)
|
||||
|
||||
#define S3C2410_GPA1 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1)
|
||||
#define S3C2410_GPA1_OUT (0<<1)
|
||||
#define S3C2410_GPA1_ADDR16 (1<<1)
|
||||
|
||||
#define S3C2410_GPA2 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2)
|
||||
#define S3C2410_GPA2_OUT (0<<2)
|
||||
#define S3C2410_GPA2_ADDR17 (1<<2)
|
||||
|
||||
#define S3C2410_GPA3 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3)
|
||||
#define S3C2410_GPA3_OUT (0<<3)
|
||||
#define S3C2410_GPA3_ADDR18 (1<<3)
|
||||
|
||||
#define S3C2410_GPA4 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4)
|
||||
#define S3C2410_GPA4_OUT (0<<4)
|
||||
#define S3C2410_GPA4_ADDR19 (1<<4)
|
||||
|
||||
#define S3C2410_GPA5 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5)
|
||||
#define S3C2410_GPA5_OUT (0<<5)
|
||||
#define S3C2410_GPA5_ADDR20 (1<<5)
|
||||
|
||||
#define S3C2410_GPA6 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6)
|
||||
#define S3C2410_GPA6_OUT (0<<6)
|
||||
#define S3C2410_GPA6_ADDR21 (1<<6)
|
||||
|
||||
#define S3C2410_GPA7 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7)
|
||||
#define S3C2410_GPA7_OUT (0<<7)
|
||||
#define S3C2410_GPA7_ADDR22 (1<<7)
|
||||
|
||||
#define S3C2410_GPA8 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8)
|
||||
#define S3C2410_GPA8_OUT (0<<8)
|
||||
#define S3C2410_GPA8_ADDR23 (1<<8)
|
||||
|
||||
#define S3C2410_GPA9 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9)
|
||||
#define S3C2410_GPA9_OUT (0<<9)
|
||||
#define S3C2410_GPA9_ADDR24 (1<<9)
|
||||
|
||||
#define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)
|
||||
#define S3C2410_GPA10_OUT (0<<10)
|
||||
#define S3C2410_GPA10_ADDR25 (1<<10)
|
||||
#define S3C2400_GPA10_SCKE (1<<10)
|
||||
|
||||
#define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)
|
||||
#define S3C2410_GPA11_OUT (0<<11)
|
||||
#define S3C2410_GPA11_ADDR26 (1<<11)
|
||||
#define S3C2400_GPA11_nCAS0 (1<<11)
|
||||
|
||||
#define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)
|
||||
#define S3C2410_GPA12_OUT (0<<12)
|
||||
#define S3C2410_GPA12_nGCS1 (1<<12)
|
||||
#define S3C2400_GPA12_nCAS1 (1<<12)
|
||||
|
||||
#define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)
|
||||
#define S3C2410_GPA13_OUT (0<<13)
|
||||
#define S3C2410_GPA13_nGCS2 (1<<13)
|
||||
#define S3C2400_GPA13_nGCS1 (1<<13)
|
||||
|
||||
#define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)
|
||||
#define S3C2410_GPA14_OUT (0<<14)
|
||||
#define S3C2410_GPA14_nGCS3 (1<<14)
|
||||
#define S3C2400_GPA14_nGCS2 (1<<14)
|
||||
|
||||
#define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)
|
||||
#define S3C2410_GPA15_OUT (0<<15)
|
||||
#define S3C2410_GPA15_nGCS4 (1<<15)
|
||||
#define S3C2400_GPA15_nGCS3 (1<<15)
|
||||
|
||||
#define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)
|
||||
#define S3C2410_GPA16_OUT (0<<16)
|
||||
#define S3C2410_GPA16_nGCS5 (1<<16)
|
||||
#define S3C2400_GPA16_nGCS4 (1<<16)
|
||||
|
||||
#define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)
|
||||
#define S3C2410_GPA17_OUT (0<<17)
|
||||
#define S3C2410_GPA17_CLE (1<<17)
|
||||
#define S3C2400_GPA17_nGCS5 (1<<17)
|
||||
|
||||
#define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)
|
||||
#define S3C2410_GPA18_OUT (0<<18)
|
||||
#define S3C2410_GPA18_ALE (1<<18)
|
||||
|
||||
#define S3C2410_GPA19 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19)
|
||||
#define S3C2410_GPA19_OUT (0<<19)
|
||||
#define S3C2410_GPA19_nFWE (1<<19)
|
||||
|
||||
#define S3C2410_GPA20 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20)
|
||||
#define S3C2410_GPA20_OUT (0<<20)
|
||||
#define S3C2410_GPA20_nFRE (1<<20)
|
||||
|
||||
#define S3C2410_GPA21 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21)
|
||||
#define S3C2410_GPA21_OUT (0<<21)
|
||||
#define S3C2410_GPA21_nRSTOUT (1<<21)
|
||||
|
||||
#define S3C2410_GPA22 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22)
|
||||
#define S3C2410_GPA22_OUT (0<<22)
|
||||
#define S3C2410_GPA22_nFCE (1<<22)
|
||||
|
||||
/* 0x08 and 0x0c are reserved on S3C2410 */
|
||||
|
@ -194,107 +148,69 @@
|
|||
|
||||
/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
|
||||
|
||||
#define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
|
||||
#define S3C2410_GPB0_INP (0x00 << 0)
|
||||
#define S3C2410_GPB0_OUTP (0x01 << 0)
|
||||
#define S3C2410_GPB0_TOUT0 (0x02 << 0)
|
||||
#define S3C2400_GPB0_DATA16 (0x02 << 0)
|
||||
|
||||
#define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)
|
||||
#define S3C2410_GPB1_INP (0x00 << 2)
|
||||
#define S3C2410_GPB1_OUTP (0x01 << 2)
|
||||
#define S3C2410_GPB1_TOUT1 (0x02 << 2)
|
||||
#define S3C2400_GPB1_DATA17 (0x02 << 2)
|
||||
|
||||
#define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)
|
||||
#define S3C2410_GPB2_INP (0x00 << 4)
|
||||
#define S3C2410_GPB2_OUTP (0x01 << 4)
|
||||
#define S3C2410_GPB2_TOUT2 (0x02 << 4)
|
||||
#define S3C2400_GPB2_DATA18 (0x02 << 4)
|
||||
#define S3C2400_GPB2_TCLK1 (0x03 << 4)
|
||||
|
||||
#define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)
|
||||
#define S3C2410_GPB3_INP (0x00 << 6)
|
||||
#define S3C2410_GPB3_OUTP (0x01 << 6)
|
||||
#define S3C2410_GPB3_TOUT3 (0x02 << 6)
|
||||
#define S3C2400_GPB3_DATA19 (0x02 << 6)
|
||||
#define S3C2400_GPB3_TXD1 (0x03 << 6)
|
||||
|
||||
#define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)
|
||||
#define S3C2410_GPB4_INP (0x00 << 8)
|
||||
#define S3C2410_GPB4_OUTP (0x01 << 8)
|
||||
#define S3C2410_GPB4_TCLK0 (0x02 << 8)
|
||||
#define S3C2400_GPB4_DATA20 (0x02 << 8)
|
||||
#define S3C2410_GPB4_MASK (0x03 << 8)
|
||||
#define S3C2400_GPB4_RXD1 (0x03 << 8)
|
||||
#define S3C2400_GPB4_MASK (0x03 << 8)
|
||||
|
||||
#define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)
|
||||
#define S3C2410_GPB5_INP (0x00 << 10)
|
||||
#define S3C2410_GPB5_OUTP (0x01 << 10)
|
||||
#define S3C2410_GPB5_nXBACK (0x02 << 10)
|
||||
#define S3C2443_GPB5_XBACK (0x03 << 10)
|
||||
#define S3C2400_GPB5_DATA21 (0x02 << 10)
|
||||
#define S3C2400_GPB5_nCTS1 (0x03 << 10)
|
||||
|
||||
#define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)
|
||||
#define S3C2410_GPB6_INP (0x00 << 12)
|
||||
#define S3C2410_GPB6_OUTP (0x01 << 12)
|
||||
#define S3C2410_GPB6_nXBREQ (0x02 << 12)
|
||||
#define S3C2443_GPB6_XBREQ (0x03 << 12)
|
||||
#define S3C2400_GPB6_DATA22 (0x02 << 12)
|
||||
#define S3C2400_GPB6_nRTS1 (0x03 << 12)
|
||||
|
||||
#define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)
|
||||
#define S3C2410_GPB7_INP (0x00 << 14)
|
||||
#define S3C2410_GPB7_OUTP (0x01 << 14)
|
||||
#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
|
||||
#define S3C2443_GPB7_XDACK1 (0x03 << 14)
|
||||
#define S3C2400_GPB7_DATA23 (0x02 << 14)
|
||||
|
||||
#define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
|
||||
#define S3C2410_GPB8_INP (0x00 << 16)
|
||||
#define S3C2410_GPB8_OUTP (0x01 << 16)
|
||||
#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
|
||||
#define S3C2400_GPB8_DATA24 (0x02 << 16)
|
||||
|
||||
#define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)
|
||||
#define S3C2410_GPB9_INP (0x00 << 18)
|
||||
#define S3C2410_GPB9_OUTP (0x01 << 18)
|
||||
#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
|
||||
#define S3C2443_GPB9_XDACK0 (0x03 << 18)
|
||||
#define S3C2400_GPB9_DATA25 (0x02 << 18)
|
||||
#define S3C2400_GPB9_I2SSDI (0x03 << 18)
|
||||
|
||||
#define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)
|
||||
#define S3C2410_GPB10_INP (0x00 << 20)
|
||||
#define S3C2410_GPB10_OUTP (0x01 << 20)
|
||||
#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
|
||||
#define S3C2443_GPB10_XDREQ0 (0x03 << 20)
|
||||
#define S3C2400_GPB10_DATA26 (0x02 << 20)
|
||||
#define S3C2400_GPB10_nSS (0x03 << 20)
|
||||
|
||||
#define S3C2400_GPB11 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11)
|
||||
#define S3C2400_GPB11_INP (0x00 << 22)
|
||||
#define S3C2400_GPB11_OUTP (0x01 << 22)
|
||||
#define S3C2400_GPB11_DATA27 (0x02 << 22)
|
||||
|
||||
#define S3C2400_GPB12 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12)
|
||||
#define S3C2400_GPB12_INP (0x00 << 24)
|
||||
#define S3C2400_GPB12_OUTP (0x01 << 24)
|
||||
#define S3C2400_GPB12_DATA28 (0x02 << 24)
|
||||
|
||||
#define S3C2400_GPB13 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13)
|
||||
#define S3C2400_GPB13_INP (0x00 << 26)
|
||||
#define S3C2400_GPB13_OUTP (0x01 << 26)
|
||||
#define S3C2400_GPB13_DATA29 (0x02 << 26)
|
||||
|
||||
#define S3C2400_GPB14 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14)
|
||||
#define S3C2400_GPB14_INP (0x00 << 28)
|
||||
#define S3C2400_GPB14_OUTP (0x01 << 28)
|
||||
#define S3C2400_GPB14_DATA30 (0x02 << 28)
|
||||
|
||||
#define S3C2400_GPB15 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15)
|
||||
#define S3C2400_GPB15_INP (0x00 << 30)
|
||||
#define S3C2400_GPB15_OUTP (0x01 << 30)
|
||||
#define S3C2400_GPB15_DATA31 (0x02 << 30)
|
||||
|
@ -315,99 +231,51 @@
|
|||
#define S3C2400_GPCDAT S3C2410_GPIOREG(0x18)
|
||||
#define S3C2400_GPCUP S3C2410_GPIOREG(0x1C)
|
||||
|
||||
#define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)
|
||||
#define S3C2410_GPC0_INP (0x00 << 0)
|
||||
#define S3C2410_GPC0_OUTP (0x01 << 0)
|
||||
#define S3C2410_GPC0_LEND (0x02 << 0)
|
||||
#define S3C2400_GPC0_VD0 (0x02 << 0)
|
||||
|
||||
#define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)
|
||||
#define S3C2410_GPC1_INP (0x00 << 2)
|
||||
#define S3C2410_GPC1_OUTP (0x01 << 2)
|
||||
#define S3C2410_GPC1_VCLK (0x02 << 2)
|
||||
#define S3C2400_GPC1_VD1 (0x02 << 2)
|
||||
|
||||
#define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)
|
||||
#define S3C2410_GPC2_INP (0x00 << 4)
|
||||
#define S3C2410_GPC2_OUTP (0x01 << 4)
|
||||
#define S3C2410_GPC2_VLINE (0x02 << 4)
|
||||
#define S3C2400_GPC2_VD2 (0x02 << 4)
|
||||
|
||||
#define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)
|
||||
#define S3C2410_GPC3_INP (0x00 << 6)
|
||||
#define S3C2410_GPC3_OUTP (0x01 << 6)
|
||||
#define S3C2410_GPC3_VFRAME (0x02 << 6)
|
||||
#define S3C2400_GPC3_VD3 (0x02 << 6)
|
||||
|
||||
#define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)
|
||||
#define S3C2410_GPC4_INP (0x00 << 8)
|
||||
#define S3C2410_GPC4_OUTP (0x01 << 8)
|
||||
#define S3C2410_GPC4_VM (0x02 << 8)
|
||||
#define S3C2400_GPC4_VD4 (0x02 << 8)
|
||||
|
||||
#define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)
|
||||
#define S3C2410_GPC5_INP (0x00 << 10)
|
||||
#define S3C2410_GPC5_OUTP (0x01 << 10)
|
||||
#define S3C2410_GPC5_LCDVF0 (0x02 << 10)
|
||||
#define S3C2400_GPC5_VD5 (0x02 << 10)
|
||||
|
||||
#define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)
|
||||
#define S3C2410_GPC6_INP (0x00 << 12)
|
||||
#define S3C2410_GPC6_OUTP (0x01 << 12)
|
||||
#define S3C2410_GPC6_LCDVF1 (0x02 << 12)
|
||||
#define S3C2400_GPC6_VD6 (0x02 << 12)
|
||||
|
||||
#define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)
|
||||
#define S3C2410_GPC7_INP (0x00 << 14)
|
||||
#define S3C2410_GPC7_OUTP (0x01 << 14)
|
||||
#define S3C2410_GPC7_LCDVF2 (0x02 << 14)
|
||||
#define S3C2400_GPC7_VD7 (0x02 << 14)
|
||||
|
||||
#define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)
|
||||
#define S3C2410_GPC8_INP (0x00 << 16)
|
||||
#define S3C2410_GPC8_OUTP (0x01 << 16)
|
||||
#define S3C2410_GPC8_VD0 (0x02 << 16)
|
||||
#define S3C2400_GPC8_VD8 (0x02 << 16)
|
||||
|
||||
#define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)
|
||||
#define S3C2410_GPC9_INP (0x00 << 18)
|
||||
#define S3C2410_GPC9_OUTP (0x01 << 18)
|
||||
#define S3C2410_GPC9_VD1 (0x02 << 18)
|
||||
#define S3C2400_GPC9_VD9 (0x02 << 18)
|
||||
|
||||
#define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)
|
||||
#define S3C2410_GPC10_INP (0x00 << 20)
|
||||
#define S3C2410_GPC10_OUTP (0x01 << 20)
|
||||
#define S3C2410_GPC10_VD2 (0x02 << 20)
|
||||
#define S3C2400_GPC10_VD10 (0x02 << 20)
|
||||
|
||||
#define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)
|
||||
#define S3C2410_GPC11_INP (0x00 << 22)
|
||||
#define S3C2410_GPC11_OUTP (0x01 << 22)
|
||||
#define S3C2410_GPC11_VD3 (0x02 << 22)
|
||||
#define S3C2400_GPC11_VD11 (0x02 << 22)
|
||||
|
||||
#define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)
|
||||
#define S3C2410_GPC12_INP (0x00 << 24)
|
||||
#define S3C2410_GPC12_OUTP (0x01 << 24)
|
||||
#define S3C2410_GPC12_VD4 (0x02 << 24)
|
||||
#define S3C2400_GPC12_VD12 (0x02 << 24)
|
||||
|
||||
#define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)
|
||||
#define S3C2410_GPC13_INP (0x00 << 26)
|
||||
#define S3C2410_GPC13_OUTP (0x01 << 26)
|
||||
#define S3C2410_GPC13_VD5 (0x02 << 26)
|
||||
#define S3C2400_GPC13_VD13 (0x02 << 26)
|
||||
|
||||
#define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)
|
||||
#define S3C2410_GPC14_INP (0x00 << 28)
|
||||
#define S3C2410_GPC14_OUTP (0x01 << 28)
|
||||
#define S3C2410_GPC14_VD6 (0x02 << 28)
|
||||
#define S3C2400_GPC14_VD14 (0x02 << 28)
|
||||
|
||||
#define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)
|
||||
#define S3C2410_GPC15_INP (0x00 << 30)
|
||||
#define S3C2410_GPC15_OUTP (0x01 << 30)
|
||||
#define S3C2410_GPC15_VD7 (0x02 << 30)
|
||||
#define S3C2400_GPC15_VD15 (0x02 << 30)
|
||||
|
||||
|
@ -432,99 +300,51 @@
|
|||
#define S3C2400_GPDDAT S3C2410_GPIOREG(0x24)
|
||||
#define S3C2400_GPDUP S3C2410_GPIOREG(0x28)
|
||||
|
||||
#define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)
|
||||
#define S3C2410_GPD0_INP (0x00 << 0)
|
||||
#define S3C2410_GPD0_OUTP (0x01 << 0)
|
||||
#define S3C2410_GPD0_VD8 (0x02 << 0)
|
||||
#define S3C2400_GPD0_VFRAME (0x02 << 0)
|
||||
#define S3C2442_GPD0_nSPICS1 (0x03 << 0)
|
||||
|
||||
#define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
|
||||
#define S3C2410_GPD1_INP (0x00 << 2)
|
||||
#define S3C2410_GPD1_OUTP (0x01 << 2)
|
||||
#define S3C2410_GPD1_VD9 (0x02 << 2)
|
||||
#define S3C2400_GPD1_VM (0x02 << 2)
|
||||
#define S3C2442_GPD1_SPICLK1 (0x03 << 2)
|
||||
|
||||
#define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
|
||||
#define S3C2410_GPD2_INP (0x00 << 4)
|
||||
#define S3C2410_GPD2_OUTP (0x01 << 4)
|
||||
#define S3C2410_GPD2_VD10 (0x02 << 4)
|
||||
#define S3C2400_GPD2_VLINE (0x02 << 4)
|
||||
|
||||
#define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)
|
||||
#define S3C2410_GPD3_INP (0x00 << 6)
|
||||
#define S3C2410_GPD3_OUTP (0x01 << 6)
|
||||
#define S3C2410_GPD3_VD11 (0x02 << 6)
|
||||
#define S3C2400_GPD3_VCLK (0x02 << 6)
|
||||
|
||||
#define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)
|
||||
#define S3C2410_GPD4_INP (0x00 << 8)
|
||||
#define S3C2410_GPD4_OUTP (0x01 << 8)
|
||||
#define S3C2410_GPD4_VD12 (0x02 << 8)
|
||||
#define S3C2400_GPD4_LEND (0x02 << 8)
|
||||
|
||||
#define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)
|
||||
#define S3C2410_GPD5_INP (0x00 << 10)
|
||||
#define S3C2410_GPD5_OUTP (0x01 << 10)
|
||||
#define S3C2410_GPD5_VD13 (0x02 << 10)
|
||||
#define S3C2400_GPD5_TOUT0 (0x02 << 10)
|
||||
|
||||
#define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)
|
||||
#define S3C2410_GPD6_INP (0x00 << 12)
|
||||
#define S3C2410_GPD6_OUTP (0x01 << 12)
|
||||
#define S3C2410_GPD6_VD14 (0x02 << 12)
|
||||
#define S3C2400_GPD6_TOUT1 (0x02 << 12)
|
||||
|
||||
#define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)
|
||||
#define S3C2410_GPD7_INP (0x00 << 14)
|
||||
#define S3C2410_GPD7_OUTP (0x01 << 14)
|
||||
#define S3C2410_GPD7_VD15 (0x02 << 14)
|
||||
#define S3C2400_GPD7_TOUT2 (0x02 << 14)
|
||||
|
||||
#define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)
|
||||
#define S3C2410_GPD8_INP (0x00 << 16)
|
||||
#define S3C2410_GPD8_OUTP (0x01 << 16)
|
||||
#define S3C2410_GPD8_VD16 (0x02 << 16)
|
||||
#define S3C2400_GPD8_TOUT3 (0x02 << 16)
|
||||
|
||||
#define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)
|
||||
#define S3C2410_GPD9_INP (0x00 << 18)
|
||||
#define S3C2410_GPD9_OUTP (0x01 << 18)
|
||||
#define S3C2410_GPD9_VD17 (0x02 << 18)
|
||||
#define S3C2400_GPD9_TCLK0 (0x02 << 18)
|
||||
#define S3C2410_GPD9_MASK (0x03 << 18)
|
||||
|
||||
#define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)
|
||||
#define S3C2410_GPD10_INP (0x00 << 20)
|
||||
#define S3C2410_GPD10_OUTP (0x01 << 20)
|
||||
#define S3C2410_GPD10_VD18 (0x02 << 20)
|
||||
#define S3C2400_GPD10_nWAIT (0x02 << 20)
|
||||
|
||||
#define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)
|
||||
#define S3C2410_GPD11_INP (0x00 << 22)
|
||||
#define S3C2410_GPD11_OUTP (0x01 << 22)
|
||||
#define S3C2410_GPD11_VD19 (0x02 << 22)
|
||||
|
||||
#define S3C2410_GPD12 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12)
|
||||
#define S3C2410_GPD12_INP (0x00 << 24)
|
||||
#define S3C2410_GPD12_OUTP (0x01 << 24)
|
||||
#define S3C2410_GPD12_VD20 (0x02 << 24)
|
||||
|
||||
#define S3C2410_GPD13 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13)
|
||||
#define S3C2410_GPD13_INP (0x00 << 26)
|
||||
#define S3C2410_GPD13_OUTP (0x01 << 26)
|
||||
#define S3C2410_GPD13_VD21 (0x02 << 26)
|
||||
|
||||
#define S3C2410_GPD14 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14)
|
||||
#define S3C2410_GPD14_INP (0x00 << 28)
|
||||
#define S3C2410_GPD14_OUTP (0x01 << 28)
|
||||
#define S3C2410_GPD14_VD22 (0x02 << 28)
|
||||
#define S3C2410_GPD14_nSS1 (0x03 << 28)
|
||||
|
||||
#define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)
|
||||
#define S3C2410_GPD15_INP (0x00 << 30)
|
||||
#define S3C2410_GPD15_OUTP (0x01 << 30)
|
||||
#define S3C2410_GPD15_VD23 (0x02 << 30)
|
||||
#define S3C2410_GPD15_nSS0 (0x03 << 30)
|
||||
|
||||
|
@ -550,34 +370,22 @@
|
|||
#define S3C2400_GPEDAT S3C2410_GPIOREG(0x30)
|
||||
#define S3C2400_GPEUP S3C2410_GPIOREG(0x34)
|
||||
|
||||
#define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
|
||||
#define S3C2410_GPE0_INP (0x00 << 0)
|
||||
#define S3C2410_GPE0_OUTP (0x01 << 0)
|
||||
#define S3C2410_GPE0_I2SLRCK (0x02 << 0)
|
||||
#define S3C2443_GPE0_AC_nRESET (0x03 << 0)
|
||||
#define S3C2400_GPE0_EINT0 (0x02 << 0)
|
||||
#define S3C2410_GPE0_MASK (0x03 << 0)
|
||||
|
||||
#define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)
|
||||
#define S3C2410_GPE1_INP (0x00 << 2)
|
||||
#define S3C2410_GPE1_OUTP (0x01 << 2)
|
||||
#define S3C2410_GPE1_I2SSCLK (0x02 << 2)
|
||||
#define S3C2443_GPE1_AC_SYNC (0x03 << 2)
|
||||
#define S3C2400_GPE1_EINT1 (0x02 << 2)
|
||||
#define S3C2400_GPE1_nSS (0x03 << 2)
|
||||
#define S3C2410_GPE1_MASK (0x03 << 2)
|
||||
|
||||
#define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)
|
||||
#define S3C2410_GPE2_INP (0x00 << 4)
|
||||
#define S3C2410_GPE2_OUTP (0x01 << 4)
|
||||
#define S3C2410_GPE2_CDCLK (0x02 << 4)
|
||||
#define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
|
||||
#define S3C2400_GPE2_EINT2 (0x02 << 4)
|
||||
#define S3C2400_GPE2_I2SSDI (0x03 << 4)
|
||||
|
||||
#define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)
|
||||
#define S3C2410_GPE3_INP (0x00 << 6)
|
||||
#define S3C2410_GPE3_OUTP (0x01 << 6)
|
||||
#define S3C2410_GPE3_I2SSDI (0x02 << 6)
|
||||
#define S3C2443_GPE3_AC_SDI (0x03 << 6)
|
||||
#define S3C2400_GPE3_EINT3 (0x02 << 6)
|
||||
|
@ -585,9 +393,6 @@
|
|||
#define S3C2410_GPE3_nSS0 (0x03 << 6)
|
||||
#define S3C2410_GPE3_MASK (0x03 << 6)
|
||||
|
||||
#define S3C2410_GPE4 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4)
|
||||
#define S3C2410_GPE4_INP (0x00 << 8)
|
||||
#define S3C2410_GPE4_OUTP (0x01 << 8)
|
||||
#define S3C2410_GPE4_I2SSDO (0x02 << 8)
|
||||
#define S3C2443_GPE4_AC_SDO (0x03 << 8)
|
||||
#define S3C2400_GPE4_EINT4 (0x02 << 8)
|
||||
|
@ -595,81 +400,48 @@
|
|||
#define S3C2410_GPE4_I2SSDI (0x03 << 8)
|
||||
#define S3C2410_GPE4_MASK (0x03 << 8)
|
||||
|
||||
#define S3C2410_GPE5 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5)
|
||||
#define S3C2410_GPE5_INP (0x00 << 10)
|
||||
#define S3C2410_GPE5_OUTP (0x01 << 10)
|
||||
#define S3C2410_GPE5_SDCLK (0x02 << 10)
|
||||
#define S3C2443_GPE5_SD1_CLK (0x02 << 10)
|
||||
#define S3C2400_GPE5_EINT5 (0x02 << 10)
|
||||
#define S3C2400_GPE5_TCLK1 (0x03 << 10)
|
||||
|
||||
#define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
|
||||
#define S3C2410_GPE6_INP (0x00 << 12)
|
||||
#define S3C2410_GPE6_OUTP (0x01 << 12)
|
||||
#define S3C2410_GPE6_SDCMD (0x02 << 12)
|
||||
#define S3C2443_GPE6_SD1_CMD (0x02 << 12)
|
||||
#define S3C2443_GPE6_AC_BITCLK (0x03 << 12)
|
||||
#define S3C2400_GPE6_EINT6 (0x02 << 12)
|
||||
|
||||
#define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
|
||||
#define S3C2410_GPE7_INP (0x00 << 14)
|
||||
#define S3C2410_GPE7_OUTP (0x01 << 14)
|
||||
#define S3C2410_GPE7_SDDAT0 (0x02 << 14)
|
||||
#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14)
|
||||
#define S3C2443_GPE7_AC_SDI (0x03 << 14)
|
||||
#define S3C2400_GPE7_EINT7 (0x02 << 14)
|
||||
|
||||
#define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
|
||||
#define S3C2410_GPE8_INP (0x00 << 16)
|
||||
#define S3C2410_GPE8_OUTP (0x01 << 16)
|
||||
#define S3C2410_GPE8_SDDAT1 (0x02 << 16)
|
||||
#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16)
|
||||
#define S3C2443_GPE8_AC_SDO (0x03 << 16)
|
||||
#define S3C2400_GPE8_nXDACK0 (0x02 << 16)
|
||||
|
||||
#define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
|
||||
#define S3C2410_GPE9_INP (0x00 << 18)
|
||||
#define S3C2410_GPE9_OUTP (0x01 << 18)
|
||||
#define S3C2410_GPE9_SDDAT2 (0x02 << 18)
|
||||
#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18)
|
||||
#define S3C2443_GPE9_AC_SYNC (0x03 << 18)
|
||||
#define S3C2400_GPE9_nXDACK1 (0x02 << 18)
|
||||
#define S3C2400_GPE9_nXBACK (0x03 << 18)
|
||||
|
||||
#define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)
|
||||
#define S3C2410_GPE10_INP (0x00 << 20)
|
||||
#define S3C2410_GPE10_OUTP (0x01 << 20)
|
||||
#define S3C2410_GPE10_SDDAT3 (0x02 << 20)
|
||||
#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
|
||||
#define S3C2443_GPE10_AC_nRESET (0x03 << 20)
|
||||
#define S3C2400_GPE10_nXDREQ0 (0x02 << 20)
|
||||
|
||||
#define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
|
||||
#define S3C2410_GPE11_INP (0x00 << 22)
|
||||
#define S3C2410_GPE11_OUTP (0x01 << 22)
|
||||
#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
|
||||
#define S3C2400_GPE11_nXDREQ1 (0x02 << 22)
|
||||
#define S3C2400_GPE11_nXBREQ (0x03 << 22)
|
||||
|
||||
#define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)
|
||||
#define S3C2410_GPE12_INP (0x00 << 24)
|
||||
#define S3C2410_GPE12_OUTP (0x01 << 24)
|
||||
#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
|
||||
|
||||
#define S3C2410_GPE13 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13)
|
||||
#define S3C2410_GPE13_INP (0x00 << 26)
|
||||
#define S3C2410_GPE13_OUTP (0x01 << 26)
|
||||
#define S3C2410_GPE13_SPICLK0 (0x02 << 26)
|
||||
|
||||
#define S3C2410_GPE14 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14)
|
||||
#define S3C2410_GPE14_INP (0x00 << 28)
|
||||
#define S3C2410_GPE14_OUTP (0x01 << 28)
|
||||
#define S3C2410_GPE14_IICSCL (0x02 << 28)
|
||||
#define S3C2410_GPE14_MASK (0x03 << 28)
|
||||
|
||||
#define S3C2410_GPE15 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15)
|
||||
#define S3C2410_GPE15_INP (0x00 << 30)
|
||||
#define S3C2410_GPE15_OUTP (0x01 << 30)
|
||||
#define S3C2410_GPE15_IICSDA (0x02 << 30)
|
||||
#define S3C2410_GPE15_MASK (0x03 << 30)
|
||||
|
||||
|
@ -705,55 +477,31 @@
|
|||
#define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C)
|
||||
#define S3C2400_GPFUP S3C2410_GPIOREG(0x40)
|
||||
|
||||
#define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)
|
||||
#define S3C2410_GPF0_INP (0x00 << 0)
|
||||
#define S3C2410_GPF0_OUTP (0x01 << 0)
|
||||
#define S3C2410_GPF0_EINT0 (0x02 << 0)
|
||||
#define S3C2400_GPF0_RXD0 (0x02 << 0)
|
||||
|
||||
#define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)
|
||||
#define S3C2410_GPF1_INP (0x00 << 2)
|
||||
#define S3C2410_GPF1_OUTP (0x01 << 2)
|
||||
#define S3C2410_GPF1_EINT1 (0x02 << 2)
|
||||
#define S3C2400_GPF1_RXD1 (0x02 << 2)
|
||||
#define S3C2400_GPF1_IICSDA (0x03 << 2)
|
||||
|
||||
#define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)
|
||||
#define S3C2410_GPF2_INP (0x00 << 4)
|
||||
#define S3C2410_GPF2_OUTP (0x01 << 4)
|
||||
#define S3C2410_GPF2_EINT2 (0x02 << 4)
|
||||
#define S3C2400_GPF2_TXD0 (0x02 << 4)
|
||||
|
||||
#define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)
|
||||
#define S3C2410_GPF3_INP (0x00 << 6)
|
||||
#define S3C2410_GPF3_OUTP (0x01 << 6)
|
||||
#define S3C2410_GPF3_EINT3 (0x02 << 6)
|
||||
#define S3C2400_GPF3_TXD1 (0x02 << 6)
|
||||
#define S3C2400_GPF3_IICSCL (0x03 << 6)
|
||||
|
||||
#define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)
|
||||
#define S3C2410_GPF4_INP (0x00 << 8)
|
||||
#define S3C2410_GPF4_OUTP (0x01 << 8)
|
||||
#define S3C2410_GPF4_EINT4 (0x02 << 8)
|
||||
#define S3C2400_GPF4_nRTS0 (0x02 << 8)
|
||||
#define S3C2400_GPF4_nXBACK (0x03 << 8)
|
||||
|
||||
#define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)
|
||||
#define S3C2410_GPF5_INP (0x00 << 10)
|
||||
#define S3C2410_GPF5_OUTP (0x01 << 10)
|
||||
#define S3C2410_GPF5_EINT5 (0x02 << 10)
|
||||
#define S3C2400_GPF5_nCTS0 (0x02 << 10)
|
||||
#define S3C2400_GPF5_nXBREQ (0x03 << 10)
|
||||
|
||||
#define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)
|
||||
#define S3C2410_GPF6_INP (0x00 << 12)
|
||||
#define S3C2410_GPF6_OUTP (0x01 << 12)
|
||||
#define S3C2410_GPF6_EINT6 (0x02 << 12)
|
||||
#define S3C2400_GPF6_CLKOUT (0x02 << 12)
|
||||
|
||||
#define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)
|
||||
#define S3C2410_GPF7_INP (0x00 << 14)
|
||||
#define S3C2410_GPF7_OUTP (0x01 << 14)
|
||||
#define S3C2410_GPF7_EINT7 (0x02 << 14)
|
||||
|
||||
#define S3C2410_GPF_PUPDIS(x) (1<<(x))
|
||||
|
@ -778,117 +526,69 @@
|
|||
#define S3C2400_GPGDAT S3C2410_GPIOREG(0x48)
|
||||
#define S3C2400_GPGUP S3C2410_GPIOREG(0x4C)
|
||||
|
||||
#define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)
|
||||
#define S3C2410_GPG0_INP (0x00 << 0)
|
||||
#define S3C2410_GPG0_OUTP (0x01 << 0)
|
||||
#define S3C2410_GPG0_EINT8 (0x02 << 0)
|
||||
#define S3C2400_GPG0_I2SLRCK (0x02 << 0)
|
||||
|
||||
#define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)
|
||||
#define S3C2410_GPG1_INP (0x00 << 2)
|
||||
#define S3C2410_GPG1_OUTP (0x01 << 2)
|
||||
#define S3C2410_GPG1_EINT9 (0x02 << 2)
|
||||
#define S3C2400_GPG1_I2SSCLK (0x02 << 2)
|
||||
|
||||
#define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)
|
||||
#define S3C2410_GPG2_INP (0x00 << 4)
|
||||
#define S3C2410_GPG2_OUTP (0x01 << 4)
|
||||
#define S3C2410_GPG2_EINT10 (0x02 << 4)
|
||||
#define S3C2410_GPG2_nSS0 (0x03 << 4)
|
||||
#define S3C2400_GPG2_CDCLK (0x02 << 4)
|
||||
|
||||
#define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
|
||||
#define S3C2410_GPG3_INP (0x00 << 6)
|
||||
#define S3C2410_GPG3_OUTP (0x01 << 6)
|
||||
#define S3C2410_GPG3_EINT11 (0x02 << 6)
|
||||
#define S3C2410_GPG3_nSS1 (0x03 << 6)
|
||||
#define S3C2400_GPG3_I2SSDO (0x02 << 6)
|
||||
#define S3C2400_GPG3_I2SSDI (0x03 << 6)
|
||||
|
||||
#define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)
|
||||
#define S3C2410_GPG4_INP (0x00 << 8)
|
||||
#define S3C2410_GPG4_OUTP (0x01 << 8)
|
||||
#define S3C2410_GPG4_EINT12 (0x02 << 8)
|
||||
#define S3C2400_GPG4_MMCCLK (0x02 << 8)
|
||||
#define S3C2400_GPG4_I2SSDI (0x03 << 8)
|
||||
#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
|
||||
#define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
|
||||
|
||||
#define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
|
||||
#define S3C2410_GPG5_INP (0x00 << 10)
|
||||
#define S3C2410_GPG5_OUTP (0x01 << 10)
|
||||
#define S3C2410_GPG5_EINT13 (0x02 << 10)
|
||||
#define S3C2400_GPG5_MMCCMD (0x02 << 10)
|
||||
#define S3C2400_GPG5_IICSDA (0x03 << 10)
|
||||
#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */
|
||||
|
||||
#define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
|
||||
#define S3C2410_GPG6_INP (0x00 << 12)
|
||||
#define S3C2410_GPG6_OUTP (0x01 << 12)
|
||||
#define S3C2410_GPG6_EINT14 (0x02 << 12)
|
||||
#define S3C2400_GPG6_MMCDAT (0x02 << 12)
|
||||
#define S3C2400_GPG6_IICSCL (0x03 << 12)
|
||||
#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
|
||||
|
||||
#define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)
|
||||
#define S3C2410_GPG7_INP (0x00 << 14)
|
||||
#define S3C2410_GPG7_OUTP (0x01 << 14)
|
||||
#define S3C2410_GPG7_EINT15 (0x02 << 14)
|
||||
#define S3C2410_GPG7_SPICLK1 (0x03 << 14)
|
||||
#define S3C2400_GPG7_SPIMISO (0x02 << 14)
|
||||
#define S3C2400_GPG7_IICSDA (0x03 << 14)
|
||||
|
||||
#define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)
|
||||
#define S3C2410_GPG8_INP (0x00 << 16)
|
||||
#define S3C2410_GPG8_OUTP (0x01 << 16)
|
||||
#define S3C2410_GPG8_EINT16 (0x02 << 16)
|
||||
#define S3C2400_GPG8_SPIMOSI (0x02 << 16)
|
||||
#define S3C2400_GPG8_IICSCL (0x03 << 16)
|
||||
|
||||
#define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)
|
||||
#define S3C2410_GPG9_INP (0x00 << 18)
|
||||
#define S3C2410_GPG9_OUTP (0x01 << 18)
|
||||
#define S3C2410_GPG9_EINT17 (0x02 << 18)
|
||||
#define S3C2400_GPG9_SPICLK (0x02 << 18)
|
||||
#define S3C2400_GPG9_MMCCLK (0x03 << 18)
|
||||
|
||||
#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
|
||||
#define S3C2410_GPG10_INP (0x00 << 20)
|
||||
#define S3C2410_GPG10_OUTP (0x01 << 20)
|
||||
#define S3C2410_GPG10_EINT18 (0x02 << 20)
|
||||
|
||||
#define S3C2410_GPG11 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11)
|
||||
#define S3C2410_GPG11_INP (0x00 << 22)
|
||||
#define S3C2410_GPG11_OUTP (0x01 << 22)
|
||||
#define S3C2410_GPG11_EINT19 (0x02 << 22)
|
||||
#define S3C2410_GPG11_TCLK1 (0x03 << 22)
|
||||
#define S3C2443_GPG11_CF_nIREQ (0x03 << 22)
|
||||
|
||||
#define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12)
|
||||
#define S3C2410_GPG12_INP (0x00 << 24)
|
||||
#define S3C2410_GPG12_OUTP (0x01 << 24)
|
||||
#define S3C2410_GPG12_EINT20 (0x02 << 24)
|
||||
#define S3C2410_GPG12_XMON (0x03 << 24)
|
||||
#define S3C2442_GPG12_nSPICS0 (0x03 << 24)
|
||||
#define S3C2443_GPG12_nINPACK (0x03 << 24)
|
||||
|
||||
#define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
|
||||
#define S3C2410_GPG13_INP (0x00 << 26)
|
||||
#define S3C2410_GPG13_OUTP (0x01 << 26)
|
||||
#define S3C2410_GPG13_EINT21 (0x02 << 26)
|
||||
#define S3C2410_GPG13_nXPON (0x03 << 26)
|
||||
#define S3C2443_GPG13_CF_nREG (0x03 << 26)
|
||||
|
||||
#define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14)
|
||||
#define S3C2410_GPG14_INP (0x00 << 28)
|
||||
#define S3C2410_GPG14_OUTP (0x01 << 28)
|
||||
#define S3C2410_GPG14_EINT22 (0x02 << 28)
|
||||
#define S3C2410_GPG14_YMON (0x03 << 28)
|
||||
#define S3C2443_GPG14_CF_RESET (0x03 << 28)
|
||||
|
||||
#define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15)
|
||||
#define S3C2410_GPG15_INP (0x00 << 30)
|
||||
#define S3C2410_GPG15_OUTP (0x01 << 30)
|
||||
#define S3C2410_GPG15_EINT23 (0x02 << 30)
|
||||
#define S3C2410_GPG15_nYPON (0x03 << 30)
|
||||
#define S3C2443_GPG15_CF_PWR (0x03 << 30)
|
||||
|
@ -907,62 +607,29 @@
|
|||
#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74)
|
||||
#define S3C2410_GPHUP S3C2410_GPIOREG(0x78)
|
||||
|
||||
#define S3C2410_GPH0 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0)
|
||||
#define S3C2410_GPH0_INP (0x00 << 0)
|
||||
#define S3C2410_GPH0_OUTP (0x01 << 0)
|
||||
#define S3C2410_GPH0_nCTS0 (0x02 << 0)
|
||||
|
||||
#define S3C2410_GPH1 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1)
|
||||
#define S3C2410_GPH1_INP (0x00 << 2)
|
||||
#define S3C2410_GPH1_OUTP (0x01 << 2)
|
||||
#define S3C2410_GPH1_nRTS0 (0x02 << 2)
|
||||
|
||||
#define S3C2410_GPH2 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2)
|
||||
#define S3C2410_GPH2_INP (0x00 << 4)
|
||||
#define S3C2410_GPH2_OUTP (0x01 << 4)
|
||||
#define S3C2410_GPH2_TXD0 (0x02 << 4)
|
||||
|
||||
#define S3C2410_GPH3 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3)
|
||||
#define S3C2410_GPH3_INP (0x00 << 6)
|
||||
#define S3C2410_GPH3_OUTP (0x01 << 6)
|
||||
#define S3C2410_GPH3_RXD0 (0x02 << 6)
|
||||
|
||||
#define S3C2410_GPH4 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4)
|
||||
#define S3C2410_GPH4_INP (0x00 << 8)
|
||||
#define S3C2410_GPH4_OUTP (0x01 << 8)
|
||||
#define S3C2410_GPH4_TXD1 (0x02 << 8)
|
||||
|
||||
#define S3C2410_GPH5 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5)
|
||||
#define S3C2410_GPH5_INP (0x00 << 10)
|
||||
#define S3C2410_GPH5_OUTP (0x01 << 10)
|
||||
#define S3C2410_GPH5_RXD1 (0x02 << 10)
|
||||
|
||||
#define S3C2410_GPH6 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6)
|
||||
#define S3C2410_GPH6_INP (0x00 << 12)
|
||||
#define S3C2410_GPH6_OUTP (0x01 << 12)
|
||||
#define S3C2410_GPH6_TXD2 (0x02 << 12)
|
||||
#define S3C2410_GPH6_nRTS1 (0x03 << 12)
|
||||
|
||||
#define S3C2410_GPH7 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7)
|
||||
#define S3C2410_GPH7_INP (0x00 << 14)
|
||||
#define S3C2410_GPH7_OUTP (0x01 << 14)
|
||||
#define S3C2410_GPH7_RXD2 (0x02 << 14)
|
||||
#define S3C2410_GPH7_nCTS1 (0x03 << 14)
|
||||
|
||||
#define S3C2410_GPH8 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8)
|
||||
#define S3C2410_GPH8_INP (0x00 << 16)
|
||||
#define S3C2410_GPH8_OUTP (0x01 << 16)
|
||||
#define S3C2410_GPH8_UCLK (0x02 << 16)
|
||||
|
||||
#define S3C2410_GPH9 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9)
|
||||
#define S3C2410_GPH9_INP (0x00 << 18)
|
||||
#define S3C2410_GPH9_OUTP (0x01 << 18)
|
||||
#define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
|
||||
#define S3C2442_GPH9_nSPICS0 (0x03 << 18)
|
||||
|
||||
#define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
|
||||
#define S3C2410_GPH10_INP (0x00 << 20)
|
||||
#define S3C2410_GPH10_OUTP (0x01 << 20)
|
||||
#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
|
||||
|
||||
/* The S3C2412 and S3C2413 move the GPJ register set to after
|
||||
|
|
|
@ -11,21 +11,13 @@
|
|||
*/
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <plat/regs-watchdog.h>
|
||||
#include <mach/regs-clock.h>
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <plat/watchdog-reset.h>
|
||||
|
||||
extern void (*s3c24xx_reset_hook)(void);
|
||||
|
||||
static void
|
||||
arch_reset(char mode, const char *cmd)
|
||||
{
|
||||
struct clk *wdtclk;
|
||||
|
||||
if (mode == 's') {
|
||||
cpu_reset(0);
|
||||
}
|
||||
|
@ -33,31 +25,7 @@ arch_reset(char mode, const char *cmd)
|
|||
if (s3c24xx_reset_hook)
|
||||
s3c24xx_reset_hook();
|
||||
|
||||
printk("arch_reset: attempting watchdog reset\n");
|
||||
|
||||
__raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
|
||||
|
||||
wdtclk = clk_get(NULL, "watchdog");
|
||||
if (!IS_ERR(wdtclk)) {
|
||||
clk_enable(wdtclk);
|
||||
} else
|
||||
printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
|
||||
|
||||
/* put initial values into count and data */
|
||||
__raw_writel(0x80, S3C2410_WTCNT);
|
||||
__raw_writel(0x80, S3C2410_WTDAT);
|
||||
|
||||
/* set the watchdog to go and reset... */
|
||||
__raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
|
||||
S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
|
||||
|
||||
/* wait for reset to assert... */
|
||||
mdelay(500);
|
||||
|
||||
printk(KERN_ERR "Watchdog reset failed to assert reset\n");
|
||||
|
||||
/* delay to allow the serial port to show the message */
|
||||
mdelay(50);
|
||||
arch_wdt_reset();
|
||||
|
||||
/* we'll take a jump through zero as a poor second */
|
||||
cpu_reset(0);
|
||||
|
|
|
@ -32,6 +32,7 @@
|
|||
#include <linux/list.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/proc_fs.h>
|
||||
|
@ -224,8 +225,8 @@ static void amlm5900_init_pm(void)
|
|||
} else {
|
||||
enable_irq_wake(IRQ_EINT9);
|
||||
/* configure the suspend/resume status pin */
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_OUTP);
|
||||
s3c2410_gpio_pullup(S3C2410_GPF2, 0);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
|
||||
s3c2410_gpio_pullup(S3C2410_GPF(2), 0);
|
||||
}
|
||||
}
|
||||
static void __init amlm5900_init(void)
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
#include <linux/list.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
@ -212,15 +213,15 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
|
|||
static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
|
||||
{
|
||||
/* ensure that an nRESET is not generated on resume. */
|
||||
s3c2410_gpio_setpin(S3C2410_GPA21, 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);
|
||||
s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bast_pm_resume(struct sys_device *sd)
|
||||
{
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -591,8 +592,6 @@ static void __init bast_map_io(void)
|
|||
s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
|
||||
s3c24xx_init_clocks(0);
|
||||
s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
|
||||
|
||||
usb_simtec_init();
|
||||
}
|
||||
|
||||
static void __init bast_init(void)
|
||||
|
@ -607,6 +606,7 @@ static void __init bast_init(void)
|
|||
i2c_register_board_info(0, bast_i2c_devs,
|
||||
ARRAY_SIZE(bast_i2c_devs));
|
||||
|
||||
usb_simtec_init();
|
||||
nor_simtec_init();
|
||||
}
|
||||
|
||||
|
|
|
@ -127,7 +127,7 @@ static void h1940_udc_pullup(enum s3c2410_udc_cmd_e cmd)
|
|||
|
||||
static struct s3c2410_udc_mach_info h1940_udc_cfg __initdata = {
|
||||
.udc_command = h1940_udc_pullup,
|
||||
.vbus_pin = S3C2410_GPG5,
|
||||
.vbus_pin = S3C2410_GPG(5),
|
||||
.vbus_pin_inverted = 1,
|
||||
};
|
||||
|
||||
|
|
|
@ -19,6 +19,7 @@
|
|||
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
@ -85,10 +86,10 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
|
|||
{
|
||||
switch (cmd) {
|
||||
case S3C2410_UDC_P_ENABLE :
|
||||
s3c2410_gpio_setpin(S3C2410_GPB3, 1);
|
||||
s3c2410_gpio_setpin(S3C2410_GPB(3), 1);
|
||||
break;
|
||||
case S3C2410_UDC_P_DISABLE :
|
||||
s3c2410_gpio_setpin(S3C2410_GPB3, 0);
|
||||
s3c2410_gpio_setpin(S3C2410_GPB(3), 0);
|
||||
break;
|
||||
case S3C2410_UDC_P_RESET :
|
||||
break;
|
||||
|
@ -99,55 +100,55 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
|
|||
|
||||
static struct s3c2410_udc_mach_info n30_udc_cfg __initdata = {
|
||||
.udc_command = n30_udc_pullup,
|
||||
.vbus_pin = S3C2410_GPG1,
|
||||
.vbus_pin = S3C2410_GPG(1),
|
||||
.vbus_pin_inverted = 0,
|
||||
};
|
||||
|
||||
static struct gpio_keys_button n30_buttons[] = {
|
||||
{
|
||||
.gpio = S3C2410_GPF0,
|
||||
.gpio = S3C2410_GPF(0),
|
||||
.code = KEY_POWER,
|
||||
.desc = "Power",
|
||||
.active_low = 0,
|
||||
},
|
||||
{
|
||||
.gpio = S3C2410_GPG9,
|
||||
.gpio = S3C2410_GPG(9),
|
||||
.code = KEY_UP,
|
||||
.desc = "Thumbwheel Up",
|
||||
.active_low = 0,
|
||||
},
|
||||
{
|
||||
.gpio = S3C2410_GPG8,
|
||||
.gpio = S3C2410_GPG(8),
|
||||
.code = KEY_DOWN,
|
||||
.desc = "Thumbwheel Down",
|
||||
.active_low = 0,
|
||||
},
|
||||
{
|
||||
.gpio = S3C2410_GPG7,
|
||||
.gpio = S3C2410_GPG(7),
|
||||
.code = KEY_ENTER,
|
||||
.desc = "Thumbwheel Press",
|
||||
.active_low = 0,
|
||||
},
|
||||
{
|
||||
.gpio = S3C2410_GPF7,
|
||||
.gpio = S3C2410_GPF(7),
|
||||
.code = KEY_HOMEPAGE,
|
||||
.desc = "Home",
|
||||
.active_low = 0,
|
||||
},
|
||||
{
|
||||
.gpio = S3C2410_GPF6,
|
||||
.gpio = S3C2410_GPF(6),
|
||||
.code = KEY_CALENDAR,
|
||||
.desc = "Calendar",
|
||||
.active_low = 0,
|
||||
},
|
||||
{
|
||||
.gpio = S3C2410_GPF5,
|
||||
.gpio = S3C2410_GPF(5),
|
||||
.code = KEY_ADDRESSBOOK,
|
||||
.desc = "Contacts",
|
||||
.active_low = 0,
|
||||
},
|
||||
{
|
||||
.gpio = S3C2410_GPF4,
|
||||
.gpio = S3C2410_GPF(4),
|
||||
.code = KEY_MAIL,
|
||||
.desc = "Mail",
|
||||
.active_low = 0,
|
||||
|
@ -169,73 +170,73 @@ static struct platform_device n30_button_device = {
|
|||
|
||||
static struct gpio_keys_button n35_buttons[] = {
|
||||
{
|
||||
.gpio = S3C2410_GPF0,
|
||||
.gpio = S3C2410_GPF(0),
|
||||
.code = KEY_POWER,
|
||||
.desc = "Power",
|
||||
.active_low = 0,
|
||||
},
|
||||
{
|
||||
.gpio = S3C2410_GPG9,
|
||||
.gpio = S3C2410_GPG(9),
|
||||
.code = KEY_UP,
|
||||
.desc = "Joystick Up",
|
||||
.active_low = 0,
|
||||
},
|
||||
{
|
||||
.gpio = S3C2410_GPG8,
|
||||
.gpio = S3C2410_GPG(8),
|
||||
.code = KEY_DOWN,
|
||||
.desc = "Joystick Down",
|
||||
.active_low = 0,
|
||||
},
|
||||
{
|
||||
.gpio = S3C2410_GPG6,
|
||||
.gpio = S3C2410_GPG(6),
|
||||
.code = KEY_DOWN,
|
||||
.desc = "Joystick Left",
|
||||
.active_low = 0,
|
||||
},
|
||||
{
|
||||
.gpio = S3C2410_GPG5,
|
||||
.gpio = S3C2410_GPG(5),
|
||||
.code = KEY_DOWN,
|
||||
.desc = "Joystick Right",
|
||||
.active_low = 0,
|
||||
},
|
||||
{
|
||||
.gpio = S3C2410_GPG7,
|
||||
.gpio = S3C2410_GPG(7),
|
||||
.code = KEY_ENTER,
|
||||
.desc = "Joystick Press",
|
||||
.active_low = 0,
|
||||
},
|
||||
{
|
||||
.gpio = S3C2410_GPF7,
|
||||
.gpio = S3C2410_GPF(7),
|
||||
.code = KEY_HOMEPAGE,
|
||||
.desc = "Home",
|
||||
.active_low = 0,
|
||||
},
|
||||
{
|
||||
.gpio = S3C2410_GPF6,
|
||||
.gpio = S3C2410_GPF(6),
|
||||
.code = KEY_CALENDAR,
|
||||
.desc = "Calendar",
|
||||
.active_low = 0,
|
||||
},
|
||||
{
|
||||
.gpio = S3C2410_GPF5,
|
||||
.gpio = S3C2410_GPF(5),
|
||||
.code = KEY_ADDRESSBOOK,
|
||||
.desc = "Contacts",
|
||||
.active_low = 0,
|
||||
},
|
||||
{
|
||||
.gpio = S3C2410_GPF4,
|
||||
.gpio = S3C2410_GPF(4),
|
||||
.code = KEY_MAIL,
|
||||
.desc = "Mail",
|
||||
.active_low = 0,
|
||||
},
|
||||
{
|
||||
.gpio = S3C2410_GPF3,
|
||||
.gpio = S3C2410_GPF(3),
|
||||
.code = SW_RADIO,
|
||||
.desc = "GPS Antenna",
|
||||
.active_low = 0,
|
||||
},
|
||||
{
|
||||
.gpio = S3C2410_GPG2,
|
||||
.gpio = S3C2410_GPG(2),
|
||||
.code = SW_HEADPHONE_INSERT,
|
||||
.desc = "Headphone",
|
||||
.active_low = 0,
|
||||
|
@ -259,7 +260,7 @@ static struct platform_device n35_button_device = {
|
|||
/* This is the bluetooth LED on the device. */
|
||||
static struct s3c24xx_led_platdata n30_blue_led_pdata = {
|
||||
.name = "blue_led",
|
||||
.gpio = S3C2410_GPG6,
|
||||
.gpio = S3C2410_GPG(6),
|
||||
.def_trigger = "",
|
||||
};
|
||||
|
||||
|
@ -270,7 +271,7 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = {
|
|||
static struct s3c24xx_led_platdata n30_warning_led_pdata = {
|
||||
.name = "warning_led",
|
||||
.flags = S3C24XX_LEDF_ACTLOW,
|
||||
.gpio = S3C2410_GPD9,
|
||||
.gpio = S3C2410_GPD(9),
|
||||
.def_trigger = "",
|
||||
};
|
||||
|
||||
|
|
|
@ -27,6 +27,7 @@
|
|||
#include <linux/list.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/serial_core.h>
|
||||
|
@ -198,7 +199,7 @@ static struct platform_device qt2410_cs89x0 = {
|
|||
/* LED */
|
||||
|
||||
static struct s3c24xx_led_platdata qt2410_pdata_led = {
|
||||
.gpio = S3C2410_GPB0,
|
||||
.gpio = S3C2410_GPB(0),
|
||||
.flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
|
||||
.name = "led",
|
||||
.def_trigger = "timer",
|
||||
|
@ -218,18 +219,18 @@ static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
|
|||
{
|
||||
switch (cs) {
|
||||
case BITBANG_CS_ACTIVE:
|
||||
s3c2410_gpio_setpin(S3C2410_GPB5, 0);
|
||||
s3c2410_gpio_setpin(S3C2410_GPB(5), 0);
|
||||
break;
|
||||
case BITBANG_CS_INACTIVE:
|
||||
s3c2410_gpio_setpin(S3C2410_GPB5, 1);
|
||||
s3c2410_gpio_setpin(S3C2410_GPB(5), 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static struct s3c2410_spigpio_info spi_gpio_cfg = {
|
||||
.pin_clk = S3C2410_GPG7,
|
||||
.pin_mosi = S3C2410_GPG6,
|
||||
.pin_miso = S3C2410_GPG5,
|
||||
.pin_clk = S3C2410_GPG(7),
|
||||
.pin_mosi = S3C2410_GPG(6),
|
||||
.pin_miso = S3C2410_GPG(5),
|
||||
.chip_select = &spi_gpio_cs,
|
||||
};
|
||||
|
||||
|
@ -346,13 +347,13 @@ static void __init qt2410_machine_init(void)
|
|||
}
|
||||
s3c24xx_fb_set_platdata(&qt2410_fb_info);
|
||||
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT);
|
||||
s3c2410_gpio_setpin(S3C2410_GPB0, 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
|
||||
s3c2410_gpio_setpin(S3C2410_GPB(0), 1);
|
||||
|
||||
s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
|
||||
s3c_i2c0_set_platdata(NULL);
|
||||
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPB(5), S3C2410_GPIO_OUTPUT);
|
||||
|
||||
platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
|
||||
s3c_pm_init();
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/list.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/dm9000.h>
|
||||
#include <linux/i2c.h>
|
||||
|
||||
|
@ -277,19 +278,19 @@ static struct platform_device vr1000_dm9k1 = {
|
|||
|
||||
static struct s3c24xx_led_platdata vr1000_led1_pdata = {
|
||||
.name = "led1",
|
||||
.gpio = S3C2410_GPB0,
|
||||
.gpio = S3C2410_GPB(0),
|
||||
.def_trigger = "",
|
||||
};
|
||||
|
||||
static struct s3c24xx_led_platdata vr1000_led2_pdata = {
|
||||
.name = "led2",
|
||||
.gpio = S3C2410_GPB1,
|
||||
.gpio = S3C2410_GPB(1),
|
||||
.def_trigger = "",
|
||||
};
|
||||
|
||||
static struct s3c24xx_led_platdata vr1000_led3_pdata = {
|
||||
.name = "led3",
|
||||
.gpio = S3C2410_GPB2,
|
||||
.gpio = S3C2410_GPB(2),
|
||||
.def_trigger = "",
|
||||
};
|
||||
|
||||
|
@ -355,8 +356,8 @@ static struct clk *vr1000_clocks[] __initdata = {
|
|||
|
||||
static void vr1000_power_off(void)
|
||||
{
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPB9, S3C2410_GPB9_OUTP);
|
||||
s3c2410_gpio_setpin(S3C2410_GPB9, 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPB(9), S3C2410_GPIO_OUTPUT);
|
||||
s3c2410_gpio_setpin(S3C2410_GPB(9), 1);
|
||||
}
|
||||
|
||||
static void __init vr1000_map_io(void)
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
#include <linux/errno.h>
|
||||
#include <linux/time.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
@ -76,7 +77,7 @@ static void s3c2410_pm_prepare(void)
|
|||
}
|
||||
|
||||
if ( machine_is_aml_m5900() )
|
||||
s3c2410_gpio_setpin(S3C2410_GPF2, 1);
|
||||
s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
|
||||
|
||||
}
|
||||
|
||||
|
@ -91,7 +92,7 @@ static int s3c2410_pm_resume(struct sys_device *dev)
|
|||
__raw_writel(tmp, S3C2410_GSTATUS2);
|
||||
|
||||
if ( machine_is_aml_m5900() )
|
||||
s3c2410_gpio_setpin(S3C2410_GPF2, 0);
|
||||
s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -18,9 +18,11 @@
|
|||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
|
@ -29,7 +31,6 @@
|
|||
|
||||
#include <mach/bast-map.h>
|
||||
#include <mach/bast-irq.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/irq.h>
|
||||
|
@ -53,9 +54,9 @@ usb_simtec_powercontrol(int port, int to)
|
|||
power_state[port] = to;
|
||||
|
||||
if (power_state[0] && power_state[1])
|
||||
s3c2410_gpio_setpin(S3C2410_GPB4, 0);
|
||||
gpio_set_value(S3C2410_GPB(4), 0);
|
||||
else
|
||||
s3c2410_gpio_setpin(S3C2410_GPB4, 1);
|
||||
gpio_set_value(S3C2410_GPB(4), 1);
|
||||
}
|
||||
|
||||
static irqreturn_t
|
||||
|
@ -63,7 +64,7 @@ usb_simtec_ocirq(int irq, void *pw)
|
|||
{
|
||||
struct s3c2410_hcd_info *info = pw;
|
||||
|
||||
if (s3c2410_gpio_getpin(S3C2410_GPG10) == 0) {
|
||||
if (gpio_get_value(S3C2410_GPG(10)) == 0) {
|
||||
pr_debug("usb_simtec: over-current irq (oc detected)\n");
|
||||
s3c2410_usb_report_oc(info, 3);
|
||||
} else {
|
||||
|
@ -106,10 +107,27 @@ static struct s3c2410_hcd_info usb_simtec_info = {
|
|||
|
||||
int usb_simtec_init(void)
|
||||
{
|
||||
printk("USB Power Control, (c) 2004 Simtec Electronics\n");
|
||||
s3c_device_usb.dev.platform_data = &usb_simtec_info;
|
||||
int ret;
|
||||
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPB4, S3C2410_GPB4_OUTP);
|
||||
s3c2410_gpio_setpin(S3C2410_GPB4, 1);
|
||||
printk("USB Power Control, (c) 2004 Simtec Electronics\n");
|
||||
|
||||
ret = gpio_request(S3C2410_GPB(4), "USB power control");
|
||||
if (ret < 0) {
|
||||
pr_err("%s: failed to get GPB4\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = gpio_request(S3C2410_GPG(10), "USB overcurrent");
|
||||
if (ret < 0) {
|
||||
pr_err("%s: failed to get GPG10\n", __func__);
|
||||
gpio_free(S3C2410_GPB(4));
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* turn power on */
|
||||
gpio_direction_output(S3C2410_GPB(4), 1);
|
||||
gpio_direction_input(S3C2410_GPG(10));
|
||||
|
||||
s3c_device_usb.dev.platform_data = &usb_simtec_info;
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -38,6 +38,7 @@ menu "S3C2412 Machines"
|
|||
config MACH_JIVE
|
||||
bool "Logitech Jive"
|
||||
select CPU_S3C2412
|
||||
select S3C_DEV_USB_HOST
|
||||
help
|
||||
Say Y here if you are using the Logitech Jive.
|
||||
|
||||
|
@ -50,6 +51,7 @@ config MACH_SMDK2413
|
|||
select CPU_S3C2412
|
||||
select MACH_S3C2413
|
||||
select MACH_SMDK
|
||||
select S3C_DEV_USB_HOST
|
||||
help
|
||||
Say Y here if you are using an SMDK2413
|
||||
|
||||
|
@ -72,6 +74,7 @@ config MACH_SMDK2412
|
|||
config MACH_VSTMS
|
||||
bool "VMSTMS"
|
||||
select CPU_S3C2412
|
||||
select S3C_DEV_USB_HOST
|
||||
help
|
||||
Say Y here if you are using an VSTMS board
|
||||
|
||||
|
|
|
@ -20,12 +20,13 @@
|
|||
|
||||
#include <mach/dma.h>
|
||||
|
||||
#include <plat/dma.h>
|
||||
#include <plat/dma-plat.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include <plat/regs-serial.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <plat/regs-ac97.h>
|
||||
#include <plat/regs-dma.h>
|
||||
#include <mach/regs-mem.h>
|
||||
#include <mach/regs-lcd.h>
|
||||
#include <mach/regs-sdi.h>
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
#include <linux/list.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
@ -356,8 +357,8 @@ static void jive_lcm_reset(unsigned int set)
|
|||
{
|
||||
printk(KERN_DEBUG "%s(%d)\n", __func__, set);
|
||||
|
||||
s3c2410_gpio_setpin(S3C2410_GPG13, set);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
|
||||
s3c2410_gpio_setpin(S3C2410_GPG(13), set);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT);
|
||||
}
|
||||
|
||||
#undef LCD_UPPER_MARGIN
|
||||
|
@ -390,13 +391,13 @@ static struct ili9320_platdata jive_lcm_config = {
|
|||
|
||||
static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs)
|
||||
{
|
||||
s3c2410_gpio_setpin(S3C2410_GPB7, cs ? 0 : 1);
|
||||
s3c2410_gpio_setpin(S3C2410_GPB(7), cs ? 0 : 1);
|
||||
}
|
||||
|
||||
static struct s3c2410_spigpio_info jive_lcd_spi = {
|
||||
.bus_num = 1,
|
||||
.pin_clk = S3C2410_GPG8,
|
||||
.pin_mosi = S3C2410_GPB8,
|
||||
.pin_clk = S3C2410_GPG(8),
|
||||
.pin_mosi = S3C2410_GPB(8),
|
||||
.num_chipselect = 1,
|
||||
.chip_select = jive_lcd_spi_chipselect,
|
||||
};
|
||||
|
@ -412,13 +413,13 @@ static struct platform_device jive_device_lcdspi = {
|
|||
|
||||
static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs)
|
||||
{
|
||||
s3c2410_gpio_setpin(S3C2410_GPH10, cs ? 0 : 1);
|
||||
s3c2410_gpio_setpin(S3C2410_GPH(10), cs ? 0 : 1);
|
||||
}
|
||||
|
||||
static struct s3c2410_spigpio_info jive_wm8750_spi = {
|
||||
.bus_num = 2,
|
||||
.pin_clk = S3C2410_GPB4,
|
||||
.pin_mosi = S3C2410_GPB9,
|
||||
.pin_clk = S3C2410_GPB(4),
|
||||
.pin_mosi = S3C2410_GPB(9),
|
||||
.num_chipselect = 1,
|
||||
.chip_select = jive_wm8750_chipselect,
|
||||
};
|
||||
|
@ -479,7 +480,7 @@ static struct platform_device *jive_devices[] __initdata = {
|
|||
};
|
||||
|
||||
static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
|
||||
.vbus_pin = S3C2410_GPG1, /* detect is on GPG1 */
|
||||
.vbus_pin = S3C2410_GPG(1), /* detect is on GPG1 */
|
||||
};
|
||||
|
||||
/* Jive power management device */
|
||||
|
@ -529,8 +530,8 @@ static void jive_power_off(void)
|
|||
{
|
||||
printk(KERN_INFO "powering system down...\n");
|
||||
|
||||
s3c2410_gpio_setpin(S3C2410_GPC5, 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPC5, S3C2410_GPIO_OUTPUT);
|
||||
s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
|
||||
}
|
||||
|
||||
static void __init jive_machine_init(void)
|
||||
|
@ -634,22 +635,22 @@ static void __init jive_machine_init(void)
|
|||
|
||||
/* initialise the spi */
|
||||
|
||||
s3c2410_gpio_setpin(S3C2410_GPG13, 0);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
|
||||
s3c2410_gpio_setpin(S3C2410_GPG(13), 0);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT);
|
||||
|
||||
s3c2410_gpio_setpin(S3C2410_GPB7, 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPB7, S3C2410_GPIO_OUTPUT);
|
||||
s3c2410_gpio_setpin(S3C2410_GPB(7), 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPB(7), S3C2410_GPIO_OUTPUT);
|
||||
|
||||
s3c2410_gpio_setpin(S3C2410_GPB6, 0);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPB6, S3C2410_GPIO_OUTPUT);
|
||||
s3c2410_gpio_setpin(S3C2410_GPB(6), 0);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT);
|
||||
|
||||
s3c2410_gpio_setpin(S3C2410_GPG8, 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPG8, S3C2410_GPIO_OUTPUT);
|
||||
s3c2410_gpio_setpin(S3C2410_GPG(8), 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT);
|
||||
|
||||
/* initialise the WM8750 spi */
|
||||
|
||||
s3c2410_gpio_setpin(S3C2410_GPH10, 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPH10, S3C2410_GPIO_OUTPUT);
|
||||
s3c2410_gpio_setpin(S3C2410_GPH(10), 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPH(10), S3C2410_GPIO_OUTPUT);
|
||||
|
||||
/* Turn off suspend on both USB ports, and switch the
|
||||
* selectable USB port to USB device mode. */
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/list.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
|
@ -84,10 +85,10 @@ static void smdk2413_udc_pullup(enum s3c2410_udc_cmd_e cmd)
|
|||
switch (cmd)
|
||||
{
|
||||
case S3C2410_UDC_P_ENABLE :
|
||||
s3c2410_gpio_setpin(S3C2410_GPF2, 1);
|
||||
s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
|
||||
break;
|
||||
case S3C2410_UDC_P_DISABLE :
|
||||
s3c2410_gpio_setpin(S3C2410_GPF2, 0);
|
||||
s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
|
||||
break;
|
||||
case S3C2410_UDC_P_RESET :
|
||||
break;
|
||||
|
@ -134,8 +135,8 @@ static void __init smdk2413_machine_init(void)
|
|||
{ /* Turn off suspend on both USB ports, and switch the
|
||||
* selectable USB port to USB device mode. */
|
||||
|
||||
s3c2410_gpio_setpin(S3C2410_GPF2, 0);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPIO_OUTPUT);
|
||||
s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
|
||||
|
||||
s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
|
||||
S3C2410_MISCCR_USBSUSPND0 |
|
||||
|
|
|
@ -33,6 +33,7 @@ config MACH_ANUBIS
|
|||
select PM_SIMTEC if PM
|
||||
select HAVE_PATA_PLATFORM
|
||||
select S3C24XX_GPIO_EXTRA64
|
||||
select S3C_DEV_USB_HOST
|
||||
help
|
||||
Say Y here if you are using the Simtec Electronics ANUBIS
|
||||
development system
|
||||
|
@ -43,6 +44,7 @@ config MACH_OSIRIS
|
|||
select S3C24XX_DCLK
|
||||
select PM_SIMTEC if PM
|
||||
select S3C24XX_GPIO_EXTRA128
|
||||
select S3C_DEV_USB_HOST
|
||||
help
|
||||
Say Y here if you are using the Simtec IM2440D20 module, also
|
||||
known as the Osiris.
|
||||
|
@ -58,12 +60,14 @@ config ARCH_S3C2440
|
|||
bool "SMDK2440"
|
||||
select CPU_S3C2440
|
||||
select MACH_SMDK
|
||||
select S3C_DEV_USB_HOST
|
||||
help
|
||||
Say Y here if you are using the SMDK2440.
|
||||
|
||||
config MACH_NEXCODER_2440
|
||||
bool "NexVision NEXCODER 2440 Light Board"
|
||||
select CPU_S3C2440
|
||||
select S3C_DEV_USB_HOST
|
||||
help
|
||||
Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board
|
||||
|
||||
|
@ -76,6 +80,7 @@ config SMDK2440_CPU2440
|
|||
config MACH_AT2440EVB
|
||||
bool "Avantech AT2440EVB development board"
|
||||
select CPU_S3C2440
|
||||
select S3C_DEV_USB_HOST
|
||||
help
|
||||
Say Y here if you are using the AT2440EVB development board
|
||||
|
||||
|
|
|
@ -17,14 +17,16 @@
|
|||
#include <linux/sysdev.h>
|
||||
#include <linux/serial_core.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/dma.h>
|
||||
|
||||
#include <plat/dma.h>
|
||||
#include <plat/dma-plat.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include <plat/regs-serial.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <plat/regs-ac97.h>
|
||||
#include <plat/regs-dma.h>
|
||||
#include <mach/regs-mem.h>
|
||||
#include <mach/regs-lcd.h>
|
||||
#include <mach/regs-sdi.h>
|
||||
|
|
|
@ -15,6 +15,7 @@
|
|||
#include <linux/list.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/ata_platform.h>
|
||||
|
@ -468,7 +469,7 @@ static void __init anubis_map_io(void)
|
|||
anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
|
||||
} else {
|
||||
/* ensure that the GPIO is setup */
|
||||
s3c2410_gpio_setpin(S3C2410_GPA0, 1);
|
||||
s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -166,7 +166,7 @@ static struct platform_device at2440evb_device_eth = {
|
|||
};
|
||||
|
||||
static struct s3c24xx_mci_pdata at2440evb_mci_pdata = {
|
||||
.gpio_detect = S3C2410_GPG10,
|
||||
.gpio_detect = S3C2410_GPG(10),
|
||||
};
|
||||
|
||||
/* 7" LCD panel */
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/list.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
@ -120,16 +121,16 @@ static struct platform_device *nexcoder_devices[] __initdata = {
|
|||
static void __init nexcoder_sensorboard_init(void)
|
||||
{
|
||||
// Initialize SCCB bus
|
||||
s3c2410_gpio_setpin(S3C2410_GPE14, 1); // IICSCL
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_OUTP);
|
||||
s3c2410_gpio_setpin(S3C2410_GPE15, 1); // IICSDA
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_OUTP);
|
||||
s3c2410_gpio_setpin(S3C2410_GPE(14), 1); // IICSCL
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT);
|
||||
s3c2410_gpio_setpin(S3C2410_GPE(15), 1); // IICSDA
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT);
|
||||
|
||||
// Power up the sensor board
|
||||
s3c2410_gpio_setpin(S3C2410_GPF1, 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPF1, S3C2410_GPF1_OUTP); // CAM_GPIO7 => nLDO_PWRDN
|
||||
s3c2410_gpio_setpin(S3C2410_GPF2, 0);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_OUTP); // CAM_GPIO6 => CAM_PWRDN
|
||||
s3c2410_gpio_setpin(S3C2410_GPF(1), 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN
|
||||
s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN
|
||||
}
|
||||
|
||||
static void __init nexcoder_map_io(void)
|
||||
|
|
|
@ -15,6 +15,7 @@
|
|||
#include <linux/list.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/serial_core.h>
|
||||
|
@ -291,8 +292,8 @@ static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
|
|||
__raw_writeb(tmp, OSIRIS_VA_CTRL0);
|
||||
|
||||
/* ensure that an nRESET is not generated on resume. */
|
||||
s3c2410_gpio_setpin(S3C2410_GPA21, 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);
|
||||
s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -304,7 +305,7 @@ static int osiris_pm_resume(struct sys_device *sd)
|
|||
|
||||
__raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
|
||||
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -384,7 +385,7 @@ static void __init osiris_map_io(void)
|
|||
osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
|
||||
} else {
|
||||
/* write-protect line to the NAND */
|
||||
s3c2410_gpio_setpin(S3C2410_GPA0, 1);
|
||||
s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
|
||||
}
|
||||
|
||||
/* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
|
||||
|
|
|
@ -20,12 +20,13 @@
|
|||
|
||||
#include <mach/dma.h>
|
||||
|
||||
#include <plat/dma.h>
|
||||
#include <plat/dma-plat.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include <plat/regs-serial.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <plat/regs-ac97.h>
|
||||
#include <plat/regs-dma.h>
|
||||
#include <mach/regs-mem.h>
|
||||
#include <mach/regs-lcd.h>
|
||||
#include <mach/regs-sdi.h>
|
||||
|
|
|
@ -5,4 +5,27 @@
|
|||
#
|
||||
# Licensed under GPLv2
|
||||
|
||||
# Currently nothing here, this will be added later
|
||||
# Configuration options for the S3C6410 CPU
|
||||
|
||||
config CPU_S3C6400
|
||||
bool
|
||||
select CPU_S3C6400_INIT
|
||||
select CPU_S3C6400_CLOCK
|
||||
help
|
||||
Enable S3C6400 CPU support
|
||||
|
||||
config S3C6400_SETUP_SDHCI
|
||||
bool
|
||||
help
|
||||
Internal configuration for default SDHCI
|
||||
setup for S3C6400.
|
||||
|
||||
# S36400 Macchine support
|
||||
|
||||
config MACH_SMDK6400
|
||||
bool "SMDK6400"
|
||||
select CPU_S3C6400
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C6400_SETUP_SDHCI
|
||||
help
|
||||
Machine support for the Samsung SMDK6400
|
||||
|
|
|
@ -12,4 +12,12 @@ obj- :=
|
|||
|
||||
# Core support for S3C6400 system
|
||||
|
||||
obj-n += blank.o
|
||||
obj-$(CONFIG_CPU_S3C6400) += s3c6400.o
|
||||
|
||||
# setup support
|
||||
|
||||
obj-$(CONFIG_S3C6400_SETUP_SDHCI) += setup-sdhci.o
|
||||
|
||||
# Machine support
|
||||
|
||||
obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
|
||||
|
|
|
@ -11,6 +11,63 @@
|
|||
#ifndef __ASM_ARCH_DMA_H
|
||||
#define __ASM_ARCH_DMA_H __FILE__
|
||||
|
||||
/* currently nothing here, placeholder */
|
||||
#define S3C_DMA_CHANNELS (16)
|
||||
|
||||
/* see mach-s3c2410/dma.h for notes on dma channel numbers */
|
||||
|
||||
/* Note, for the S3C64XX architecture we keep the DMACH_
|
||||
* defines in the order they are allocated to [S]DMA0/[S]DMA1
|
||||
* so that is easy to do DHACH_ -> DMA controller conversion
|
||||
*/
|
||||
enum dma_ch {
|
||||
/* DMA0/SDMA0 */
|
||||
DMACH_UART0 = 0,
|
||||
DMACH_UART0_SRC2,
|
||||
DMACH_UART1,
|
||||
DMACH_UART1_SRC2,
|
||||
DMACH_UART2,
|
||||
DMACH_UART2_SRC2,
|
||||
DMACH_UART3,
|
||||
DMACH_UART3_SRC2,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_I2S0_OUT,
|
||||
DMACH_I2S0_IN,
|
||||
DMACH_SPI0_TX,
|
||||
DMACH_SPI0_RX,
|
||||
DMACH_HSI_I2SV40_TX,
|
||||
DMACH_HSI_I2SV40_RX,
|
||||
|
||||
/* DMA1/SDMA1 */
|
||||
DMACH_PCM1_TX = 16,
|
||||
DMACH_PCM1_RX,
|
||||
DMACH_I2S1_OUT,
|
||||
DMACH_I2S1_IN,
|
||||
DMACH_SPI1_TX,
|
||||
DMACH_SPI1_RX,
|
||||
DMACH_AC97_PCMOUT,
|
||||
DMACH_AC97_PCMIN,
|
||||
DMACH_AC97_MICIN,
|
||||
DMACH_PWM,
|
||||
DMACH_IRDA,
|
||||
DMACH_EXTERNAL,
|
||||
DMACH_RES1,
|
||||
DMACH_RES2,
|
||||
DMACH_SECURITY_RX, /* SDMA1 only */
|
||||
DMACH_SECURITY_TX, /* SDMA1 only */
|
||||
DMACH_MAX /* the end */
|
||||
};
|
||||
|
||||
static __inline__ int s3c_dma_has_circular(void)
|
||||
{
|
||||
/* we will be supporting ciruclar buffers as soon as we have DMA
|
||||
* engine support.
|
||||
*/
|
||||
return 1;
|
||||
}
|
||||
|
||||
#define S3C2410_DMAF_CIRCULAR (1 << 0)
|
||||
|
||||
#include <plat/dma.h>
|
||||
|
||||
#endif /* __ASM_ARCH_IRQ_H */
|
||||
|
|
|
@ -39,6 +39,8 @@
|
|||
#define S3C_VA_UART3 S3C_VA_UARTx(3)
|
||||
|
||||
#define S3C64XX_PA_FB (0x77100000)
|
||||
#define S3C64XX_PA_USB_HSOTG (0x7C000000)
|
||||
#define S3C64XX_PA_WATCHDOG (0x7E004000)
|
||||
#define S3C64XX_PA_SYSCON (0x7E00F000)
|
||||
#define S3C64XX_PA_IIS0 (0x7F002000)
|
||||
#define S3C64XX_PA_IIS1 (0x7F003000)
|
||||
|
@ -57,6 +59,8 @@
|
|||
#define S3C64XX_PA_MODEM (0x74108000)
|
||||
#define S3C64XX_VA_MODEM S3C_ADDR(0x00600000)
|
||||
|
||||
#define S3C64XX_PA_USBHOST (0x74300000)
|
||||
|
||||
/* place VICs close together */
|
||||
#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00)
|
||||
#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000)
|
||||
|
@ -69,5 +73,7 @@
|
|||
#define S3C_PA_IIC S3C64XX_PA_IIC0
|
||||
#define S3C_PA_IIC1 S3C64XX_PA_IIC1
|
||||
#define S3C_PA_FB S3C64XX_PA_FB
|
||||
#define S3C_PA_USBHOST S3C64XX_PA_USBHOST
|
||||
#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
|
||||
|
||||
#endif /* __ASM_ARCH_6400_MAP_H */
|
||||
|
|
16
arch/arm/mach-s3c6400/include/mach/regs-clock.h
Normal file
16
arch/arm/mach-s3c6400/include/mach/regs-clock.h
Normal file
|
@ -0,0 +1,16 @@
|
|||
/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h
|
||||
*
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* http://armlinux.simtec.co.uk/
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* S3C64XX - clock register compatibility with s3c24xx
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <plat/regs-clock.h>
|
||||
|
|
@ -11,6 +11,8 @@
|
|||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H __FILE__
|
||||
|
||||
#include <plat/watchdog-reset.h>
|
||||
|
||||
static void arch_idle(void)
|
||||
{
|
||||
/* nothing here yet */
|
||||
|
@ -18,7 +20,11 @@ static void arch_idle(void)
|
|||
|
||||
static void arch_reset(char mode, const char *cmd)
|
||||
{
|
||||
/* nothing here yet */
|
||||
if (mode != 's')
|
||||
arch_wdt_reset();
|
||||
|
||||
/* if all else fails, or mode was for soft, jump to 0 */
|
||||
cpu_reset(0);
|
||||
}
|
||||
|
||||
#endif /* __ASM_ARCH_IRQ_H */
|
||||
|
|
96
arch/arm/mach-s3c6400/mach-smdk6400.c
Normal file
96
arch/arm/mach-s3c6400/mach-smdk6400.c
Normal file
|
@ -0,0 +1,96 @@
|
|||
/* linux/arch/arm/mach-s3c6400/mach-smdk6400.c
|
||||
*
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/regs-serial.h>
|
||||
|
||||
#include <plat/s3c6400.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/iic.h>
|
||||
|
||||
#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
|
||||
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
|
||||
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
|
||||
|
||||
static struct s3c2410_uartcfg smdk6400_uartcfgs[] __initdata = {
|
||||
[0] = {
|
||||
.hwport = 0,
|
||||
.flags = 0,
|
||||
.ucon = 0x3c5,
|
||||
.ulcon = 0x03,
|
||||
.ufcon = 0x51,
|
||||
},
|
||||
[1] = {
|
||||
.hwport = 1,
|
||||
.flags = 0,
|
||||
.ucon = 0x3c5,
|
||||
.ulcon = 0x03,
|
||||
.ufcon = 0x51,
|
||||
},
|
||||
};
|
||||
|
||||
static struct map_desc smdk6400_iodesc[] = {};
|
||||
|
||||
static void __init smdk6400_map_io(void)
|
||||
{
|
||||
s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc));
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs));
|
||||
}
|
||||
|
||||
static struct platform_device *smdk6400_devices[] __initdata = {
|
||||
&s3c_device_hsmmc1,
|
||||
&s3c_device_i2c0,
|
||||
};
|
||||
|
||||
static struct i2c_board_info i2c_devs[] __initdata = {
|
||||
{ I2C_BOARD_INFO("wm8753", 0x1A), },
|
||||
{ I2C_BOARD_INFO("24c08", 0x50), },
|
||||
};
|
||||
|
||||
static void __init smdk6400_machine_init(void)
|
||||
{
|
||||
i2c_register_board_info(0, i2c_devs, ARRAY_SIZE(i2c_devs));
|
||||
platform_add_devices(smdk6400_devices, ARRAY_SIZE(smdk6400_devices));
|
||||
}
|
||||
|
||||
MACHINE_START(SMDK6400, "SMDK6400")
|
||||
/* Maintainer: Ben Dooks <ben@fluff.org> */
|
||||
.phys_io = S3C_PA_UART & 0xfff00000,
|
||||
.io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
|
||||
.boot_params = S3C64XX_PA_SDRAM + 0x100,
|
||||
|
||||
.init_irq = s3c6400_init_irq,
|
||||
.map_io = smdk6400_map_io,
|
||||
.init_machine = smdk6400_machine_init,
|
||||
.timer = &s3c24xx_timer,
|
||||
MACHINE_END
|
89
arch/arm/mach-s3c6400/s3c6400.c
Normal file
89
arch/arm/mach-s3c6400/s3c6400.c
Normal file
|
@ -0,0 +1,89 @@
|
|||
/* linux/arch/arm/mach-s3c6410/cpu.c
|
||||
*
|
||||
* Copyright 2009 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/irq.h>
|
||||
|
||||
#include <plat/cpu-freq.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/regs-clock.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/sdhci.h>
|
||||
#include <plat/iic-core.h>
|
||||
#include <plat/s3c6400.h>
|
||||
|
||||
void __init s3c6400_map_io(void)
|
||||
{
|
||||
/* setup SDHCI */
|
||||
|
||||
s3c6400_default_sdhci0();
|
||||
s3c6400_default_sdhci1();
|
||||
|
||||
/* the i2c devices are directly compatible with s3c2440 */
|
||||
s3c_i2c0_setname("s3c2440-i2c");
|
||||
}
|
||||
|
||||
void __init s3c6400_init_clocks(int xtal)
|
||||
{
|
||||
printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
|
||||
s3c24xx_register_baseclocks(xtal);
|
||||
s3c64xx_register_clocks();
|
||||
s3c6400_register_clocks(S3C6400_CLKDIV0_ARM_MASK);
|
||||
s3c6400_setup_clocks();
|
||||
}
|
||||
|
||||
void __init s3c6400_init_irq(void)
|
||||
{
|
||||
/* VIC0 does not have IRQS 5..7,
|
||||
* VIC1 is fully populated. */
|
||||
s3c64xx_init_irq(~0 & ~(0xf << 5), ~0);
|
||||
}
|
||||
|
||||
struct sysdev_class s3c6400_sysclass = {
|
||||
.name = "s3c6400-core",
|
||||
};
|
||||
|
||||
static struct sys_device s3c6400_sysdev = {
|
||||
.cls = &s3c6400_sysclass,
|
||||
};
|
||||
|
||||
static int __init s3c6400_core_init(void)
|
||||
{
|
||||
return sysdev_class_register(&s3c6400_sysclass);
|
||||
}
|
||||
|
||||
core_initcall(s3c6400_core_init);
|
||||
|
||||
int __init s3c6400_init(void)
|
||||
{
|
||||
printk("S3C6400: Initialising architecture\n");
|
||||
|
||||
return sysdev_register(&s3c6400_sysdev);
|
||||
}
|
63
arch/arm/mach-s3c6400/setup-sdhci.c
Normal file
63
arch/arm/mach-s3c6400/setup-sdhci.c
Normal file
|
@ -0,0 +1,63 @@
|
|||
/* linux/arch/arm/mach-s3c6410/setup-sdhci.c
|
||||
*
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <linux/mmc/card.h>
|
||||
#include <linux/mmc/host.h>
|
||||
|
||||
#include <plat/regs-sdhci.h>
|
||||
#include <plat/sdhci.h>
|
||||
|
||||
/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
|
||||
|
||||
char *s3c6400_hsmmc_clksrcs[4] = {
|
||||
[0] = "hsmmc",
|
||||
[1] = "hsmmc",
|
||||
[2] = "mmc_bus",
|
||||
/* [3] = "48m", - note not succesfully used yet */
|
||||
};
|
||||
|
||||
void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
|
||||
void __iomem *r,
|
||||
struct mmc_ios *ios,
|
||||
struct mmc_card *card)
|
||||
{
|
||||
u32 ctrl2, ctrl3;
|
||||
|
||||
ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
|
||||
ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
|
||||
ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
|
||||
S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
|
||||
S3C_SDHCI_CTRL2_ENFBCLKRX |
|
||||
S3C_SDHCI_CTRL2_DFCNT_NONE |
|
||||
S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
|
||||
|
||||
if (ios->clock < 25 * 1000000)
|
||||
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
|
||||
S3C_SDHCI_CTRL3_FCSEL2 |
|
||||
S3C_SDHCI_CTRL3_FCSEL1 |
|
||||
S3C_SDHCI_CTRL3_FCSEL0);
|
||||
else
|
||||
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
|
||||
|
||||
printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
|
||||
writel(ctrl2, r + S3C_SDHCI_CONTROL2);
|
||||
writel(ctrl3, r + S3C_SDHCI_CONTROL3);
|
||||
}
|
||||
|
|
@ -16,9 +16,18 @@ config CPU_S3C6410
|
|||
|
||||
config S3C6410_SETUP_SDHCI
|
||||
bool
|
||||
select S3C64XX_SETUP_SDHCI_GPIO
|
||||
help
|
||||
Internal helper functions for S3C6410 based SDHCI systems
|
||||
|
||||
config MACH_ANW6410
|
||||
bool "A&W6410"
|
||||
select CPU_S3C6410
|
||||
select S3C_DEV_FB
|
||||
select S3C64XX_SETUP_FB_24BPP
|
||||
help
|
||||
Machine support for the A&W6410
|
||||
|
||||
config MACH_SMDK6410
|
||||
bool "SMDK6410"
|
||||
select CPU_S3C6410
|
||||
|
@ -26,6 +35,8 @@ config MACH_SMDK6410
|
|||
select S3C_DEV_HSMMC1
|
||||
select S3C_DEV_I2C1
|
||||
select S3C_DEV_FB
|
||||
select S3C_DEV_USB_HOST
|
||||
select S3C_DEV_USB_HSOTG
|
||||
select S3C6410_SETUP_SDHCI
|
||||
select S3C64XX_SETUP_I2C1
|
||||
select S3C64XX_SETUP_FB_24BPP
|
||||
|
@ -60,3 +71,29 @@ config SMDK6410_SD_CH1
|
|||
channels 0 and 1 are the same.
|
||||
|
||||
endchoice
|
||||
|
||||
config SMDK6410_WM1190_EV1
|
||||
bool "Support Wolfson Microelectronics 1190-EV1 PMIC card"
|
||||
depends on MACH_SMDK6410
|
||||
select REGULATOR
|
||||
select REGULATOR_WM8350
|
||||
select MFD_WM8350_I2C
|
||||
select MFD_WM8350_CONFIG_MODE_0
|
||||
select MFD_WM8350_CONFIG_MODE_3
|
||||
select MFD_WM8352_CONFIG_MODE_0
|
||||
help
|
||||
The Wolfson Microelectronics 1190-EV1 is a WM835x based PMIC
|
||||
and audio daughtercard for the Samsung SMDK6410 reference
|
||||
platform. Enabling this option will build support for this
|
||||
module into the kernel. The presence of the module will be
|
||||
detected at runtime so the the resulting kernel can be used
|
||||
with or without the 1190-EV1 fitted.
|
||||
|
||||
config MACH_NCP
|
||||
bool "NCP"
|
||||
select CPU_S3C6410
|
||||
select S3C_DEV_I2C1
|
||||
select S3C_DEV_HSMMC1
|
||||
select S3C64XX_SETUP_I2C1
|
||||
help
|
||||
Machine support for the Samsung NCP
|
||||
|
|
|
@ -20,4 +20,8 @@ obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci.o
|
|||
|
||||
# machine support
|
||||
|
||||
obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o
|
||||
obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
|
||||
obj-$(CONFIG_MACH_NCP) += mach-ncp.o
|
||||
|
||||
|
||||
|
|
|
@ -31,6 +31,7 @@
|
|||
|
||||
#include <plat/cpu-freq.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/regs-clock.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
|
@ -68,7 +69,7 @@ void __init s3c6410_init_clocks(int xtal)
|
|||
printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
|
||||
s3c24xx_register_baseclocks(xtal);
|
||||
s3c64xx_register_clocks();
|
||||
s3c6400_register_clocks();
|
||||
s3c6400_register_clocks(S3C6410_CLKDIV0_ARM_MASK);
|
||||
s3c6400_setup_clocks();
|
||||
}
|
||||
|
||||
|
|
245
arch/arm/mach-s3c6410/mach-anw6410.c
Normal file
245
arch/arm/mach-s3c6410/mach-anw6410.c
Normal file
|
@ -0,0 +1,245 @@
|
|||
/* linux/arch/arm/mach-s3c6410/mach-anw6410.c
|
||||
*
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
* Copyright 2009 Kwangwoo Lee
|
||||
* Kwangwoo Lee <kwangwoo.lee@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/fb.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/dm9000.h>
|
||||
|
||||
#include <video/platform_lcd.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/regs-fb.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/iic.h>
|
||||
#include <plat/fb.h>
|
||||
|
||||
#include <plat/s3c6410.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/regs-gpio.h>
|
||||
#include <plat/regs-modem.h>
|
||||
|
||||
/* DM9000 */
|
||||
#define ANW6410_PA_DM9000 (0x18000000)
|
||||
|
||||
/* A hardware buffer to control external devices is mapped at 0x30000000.
|
||||
* It can not be read. So current status must be kept in anw6410_extdev_status.
|
||||
*/
|
||||
#define ANW6410_VA_EXTDEV S3C_ADDR(0x02000000)
|
||||
#define ANW6410_PA_EXTDEV (0x30000000)
|
||||
|
||||
#define ANW6410_EN_DM9000 (1<<11)
|
||||
#define ANW6410_EN_LCD (1<<14)
|
||||
|
||||
static __u32 anw6410_extdev_status;
|
||||
|
||||
static struct s3c2410_uartcfg anw6410_uartcfgs[] __initdata = {
|
||||
[0] = {
|
||||
.hwport = 0,
|
||||
.flags = 0,
|
||||
.ucon = 0x3c5,
|
||||
.ulcon = 0x03,
|
||||
.ufcon = 0x51,
|
||||
},
|
||||
[1] = {
|
||||
.hwport = 1,
|
||||
.flags = 0,
|
||||
.ucon = 0x3c5,
|
||||
.ulcon = 0x03,
|
||||
.ufcon = 0x51,
|
||||
},
|
||||
};
|
||||
|
||||
/* framebuffer and LCD setup. */
|
||||
static void __init anw6410_lcd_mode_set(void)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
/* set the LCD type */
|
||||
tmp = __raw_readl(S3C64XX_SPCON);
|
||||
tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
|
||||
tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
|
||||
__raw_writel(tmp, S3C64XX_SPCON);
|
||||
|
||||
/* remove the LCD bypass */
|
||||
tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
|
||||
tmp &= ~MIFPCON_LCD_BYPASS;
|
||||
__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
|
||||
}
|
||||
|
||||
/* GPF1 = LCD panel power
|
||||
* GPF4 = LCD backlight control
|
||||
*/
|
||||
static void anw6410_lcd_power_set(struct plat_lcd_data *pd,
|
||||
unsigned int power)
|
||||
{
|
||||
if (power) {
|
||||
anw6410_extdev_status |= (ANW6410_EN_LCD << 16);
|
||||
__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
|
||||
|
||||
gpio_direction_output(S3C64XX_GPF(1), 1);
|
||||
gpio_direction_output(S3C64XX_GPF(4), 1);
|
||||
} else {
|
||||
anw6410_extdev_status &= ~(ANW6410_EN_LCD << 16);
|
||||
__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
|
||||
|
||||
gpio_direction_output(S3C64XX_GPF(1), 0);
|
||||
gpio_direction_output(S3C64XX_GPF(4), 0);
|
||||
}
|
||||
}
|
||||
|
||||
static struct plat_lcd_data anw6410_lcd_power_data = {
|
||||
.set_power = anw6410_lcd_power_set,
|
||||
};
|
||||
|
||||
static struct platform_device anw6410_lcd_powerdev = {
|
||||
.name = "platform-lcd",
|
||||
.dev.parent = &s3c_device_fb.dev,
|
||||
.dev.platform_data = &anw6410_lcd_power_data,
|
||||
};
|
||||
|
||||
static struct s3c_fb_pd_win anw6410_fb_win0 = {
|
||||
/* this is to ensure we use win0 */
|
||||
.win_mode = {
|
||||
.pixclock = 41094,
|
||||
.left_margin = 8,
|
||||
.right_margin = 13,
|
||||
.upper_margin = 7,
|
||||
.lower_margin = 5,
|
||||
.hsync_len = 3,
|
||||
.vsync_len = 1,
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
},
|
||||
.max_bpp = 32,
|
||||
.default_bpp = 16,
|
||||
};
|
||||
|
||||
/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
|
||||
static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = {
|
||||
.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
|
||||
.win[0] = &anw6410_fb_win0,
|
||||
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
|
||||
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
|
||||
};
|
||||
|
||||
/* DM9000AEP 10/100 ethernet controller */
|
||||
static void __init anw6410_dm9000_enable(void)
|
||||
{
|
||||
anw6410_extdev_status |= (ANW6410_EN_DM9000 << 16);
|
||||
__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
|
||||
}
|
||||
|
||||
static struct resource anw6410_dm9000_resource[] = {
|
||||
[0] = {
|
||||
.start = ANW6410_PA_DM9000,
|
||||
.end = ANW6410_PA_DM9000 + 3,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = ANW6410_PA_DM9000 + 4,
|
||||
.end = ANW6410_PA_DM9000 + 4 + 500,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[2] = {
|
||||
.start = IRQ_EINT(15),
|
||||
.end = IRQ_EINT(15),
|
||||
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
|
||||
},
|
||||
};
|
||||
|
||||
static struct dm9000_plat_data anw6410_dm9000_pdata = {
|
||||
.flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
|
||||
/* dev_addr can be set to provide hwaddr. */
|
||||
};
|
||||
|
||||
static struct platform_device anw6410_device_eth = {
|
||||
.name = "dm9000",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(anw6410_dm9000_resource),
|
||||
.resource = anw6410_dm9000_resource,
|
||||
.dev = {
|
||||
.platform_data = &anw6410_dm9000_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct map_desc anw6410_iodesc[] __initdata = {
|
||||
{
|
||||
.virtual = (unsigned long)ANW6410_VA_EXTDEV,
|
||||
.pfn = __phys_to_pfn(ANW6410_PA_EXTDEV),
|
||||
.length = SZ_64K,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *anw6410_devices[] __initdata = {
|
||||
&s3c_device_fb,
|
||||
&anw6410_lcd_powerdev,
|
||||
&anw6410_device_eth,
|
||||
};
|
||||
|
||||
static void __init anw6410_map_io(void)
|
||||
{
|
||||
s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
|
||||
|
||||
anw6410_lcd_mode_set();
|
||||
}
|
||||
|
||||
static void __init anw6410_machine_init(void)
|
||||
{
|
||||
s3c_fb_set_platdata(&anw6410_lcd_pdata);
|
||||
|
||||
gpio_request(S3C64XX_GPF(1), "panel power");
|
||||
gpio_request(S3C64XX_GPF(4), "LCD backlight");
|
||||
|
||||
anw6410_dm9000_enable();
|
||||
|
||||
platform_add_devices(anw6410_devices, ARRAY_SIZE(anw6410_devices));
|
||||
}
|
||||
|
||||
MACHINE_START(ANW6410, "A&W6410")
|
||||
/* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
|
||||
.phys_io = S3C_PA_UART & 0xfff00000,
|
||||
.io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
|
||||
.boot_params = S3C64XX_PA_SDRAM + 0x100,
|
||||
|
||||
.init_irq = s3c6410_init_irq,
|
||||
.map_io = anw6410_map_io,
|
||||
.init_machine = anw6410_machine_init,
|
||||
.timer = &s3c24xx_timer,
|
||||
MACHINE_END
|
107
arch/arm/mach-s3c6410/mach-ncp.c
Normal file
107
arch/arm/mach-s3c6410/mach-ncp.c
Normal file
|
@ -0,0 +1,107 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-s3c6410/mach-ncp.c
|
||||
*
|
||||
* Copyright (C) 2008-2009 Samsung Electronics
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/fb.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include <video/platform_lcd.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/regs-fb.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/iic.h>
|
||||
#include <plat/fb.h>
|
||||
|
||||
#include <plat/s3c6410.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#define UCON S3C2410_UCON_DEFAULT
|
||||
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
|
||||
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
|
||||
|
||||
static struct s3c2410_uartcfg ncp_uartcfgs[] __initdata = {
|
||||
/* REVISIT: NCP uses only serial 1, 2 */
|
||||
[0] = {
|
||||
.hwport = 0,
|
||||
.flags = 0,
|
||||
.ucon = UCON,
|
||||
.ulcon = ULCON,
|
||||
.ufcon = UFCON,
|
||||
},
|
||||
[1] = {
|
||||
.hwport = 1,
|
||||
.flags = 0,
|
||||
.ucon = UCON,
|
||||
.ulcon = ULCON,
|
||||
.ufcon = UFCON,
|
||||
},
|
||||
[2] = {
|
||||
.hwport = 2,
|
||||
.flags = 0,
|
||||
.ucon = UCON,
|
||||
.ulcon = ULCON,
|
||||
.ufcon = UFCON,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *ncp_devices[] __initdata = {
|
||||
&s3c_device_hsmmc1,
|
||||
&s3c_device_i2c0,
|
||||
};
|
||||
|
||||
struct map_desc ncp_iodesc[] = {};
|
||||
|
||||
static void __init ncp_map_io(void)
|
||||
{
|
||||
s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
|
||||
}
|
||||
|
||||
static void __init ncp_machine_init(void)
|
||||
{
|
||||
s3c_i2c0_set_platdata(NULL);
|
||||
|
||||
platform_add_devices(ncp_devices, ARRAY_SIZE(ncp_devices));
|
||||
}
|
||||
|
||||
MACHINE_START(NCP, "NCP")
|
||||
/* Maintainer: Samsung Electronics */
|
||||
.phys_io = S3C_PA_UART & 0xfff00000,
|
||||
.io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
|
||||
.boot_params = S3C64XX_PA_SDRAM + 0x100,
|
||||
.init_irq = s3c6410_init_irq,
|
||||
.map_io = ncp_map_io,
|
||||
.init_machine = ncp_machine_init,
|
||||
.timer = &s3c24xx_timer,
|
||||
MACHINE_END
|
|
@ -24,6 +24,12 @@
|
|||
#include <linux/fb.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/smsc911x.h>
|
||||
|
||||
#ifdef CONFIG_SMDK6410_WM1190_EV1
|
||||
#include <linux/mfd/wm8350/core.h>
|
||||
#include <linux/mfd/wm8350/pmic.h>
|
||||
#endif
|
||||
|
||||
#include <video/platform_lcd.h>
|
||||
|
||||
|
@ -39,8 +45,12 @@
|
|||
#include <asm/mach-types.h>
|
||||
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/regs-modem.h>
|
||||
#include <plat/regs-gpio.h>
|
||||
#include <plat/regs-sys.h>
|
||||
#include <plat/iic.h>
|
||||
#include <plat/fb.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
|
||||
#include <plat/s3c6410.h>
|
||||
#include <plat/clock.h>
|
||||
|
@ -129,6 +139,37 @@ static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
|
|||
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
|
||||
};
|
||||
|
||||
static struct resource smdk6410_smsc911x_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x18000000,
|
||||
.end = 0x18000000 + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = S3C_EINT(10),
|
||||
.end = S3C_EINT(10),
|
||||
.flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW,
|
||||
},
|
||||
};
|
||||
|
||||
static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
|
||||
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
|
||||
.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
|
||||
.flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
|
||||
.phy_interface = PHY_INTERFACE_MODE_MII,
|
||||
};
|
||||
|
||||
|
||||
static struct platform_device smdk6410_smsc911x = {
|
||||
.name = "smsc911x",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
|
||||
.resource = &smdk6410_smsc911x_resources[0],
|
||||
.dev = {
|
||||
.platform_data = &smdk6410_smsc911x_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct map_desc smdk6410_iodesc[] = {};
|
||||
|
||||
static struct platform_device *smdk6410_devices[] __initdata = {
|
||||
|
@ -141,12 +182,155 @@ static struct platform_device *smdk6410_devices[] __initdata = {
|
|||
&s3c_device_i2c0,
|
||||
&s3c_device_i2c1,
|
||||
&s3c_device_fb,
|
||||
&s3c_device_usb,
|
||||
&s3c_device_usb_hsotg,
|
||||
&smdk6410_lcd_powerdev,
|
||||
|
||||
&smdk6410_smsc911x,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_SMDK6410_WM1190_EV1
|
||||
/* S3C64xx internal logic & PLL */
|
||||
static struct regulator_init_data wm8350_dcdc1_data = {
|
||||
.constraints = {
|
||||
.name = "PVDD_INT/PVDD_PLL",
|
||||
.min_uV = 1200000,
|
||||
.max_uV = 1200000,
|
||||
.always_on = 1,
|
||||
.apply_uV = 1,
|
||||
},
|
||||
};
|
||||
|
||||
/* Memory */
|
||||
static struct regulator_init_data wm8350_dcdc3_data = {
|
||||
.constraints = {
|
||||
.name = "PVDD_MEM",
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.always_on = 1,
|
||||
.state_mem = {
|
||||
.uV = 1800000,
|
||||
.mode = REGULATOR_MODE_NORMAL,
|
||||
.enabled = 1,
|
||||
},
|
||||
.initial_state = PM_SUSPEND_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
/* USB, EXT, PCM, ADC/DAC, USB, MMC */
|
||||
static struct regulator_init_data wm8350_dcdc4_data = {
|
||||
.constraints = {
|
||||
.name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
|
||||
.min_uV = 3000000,
|
||||
.max_uV = 3000000,
|
||||
.always_on = 1,
|
||||
},
|
||||
};
|
||||
|
||||
/* ARM core */
|
||||
static struct regulator_consumer_supply dcdc6_consumers[] = {
|
||||
{
|
||||
.supply = "vddarm",
|
||||
}
|
||||
};
|
||||
|
||||
static struct regulator_init_data wm8350_dcdc6_data = {
|
||||
.constraints = {
|
||||
.name = "PVDD_ARM",
|
||||
.min_uV = 1000000,
|
||||
.max_uV = 1300000,
|
||||
.always_on = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(dcdc6_consumers),
|
||||
.consumer_supplies = dcdc6_consumers,
|
||||
};
|
||||
|
||||
/* Alive */
|
||||
static struct regulator_init_data wm8350_ldo1_data = {
|
||||
.constraints = {
|
||||
.name = "PVDD_ALIVE",
|
||||
.min_uV = 1200000,
|
||||
.max_uV = 1200000,
|
||||
.always_on = 1,
|
||||
.apply_uV = 1,
|
||||
},
|
||||
};
|
||||
|
||||
/* OTG */
|
||||
static struct regulator_init_data wm8350_ldo2_data = {
|
||||
.constraints = {
|
||||
.name = "PVDD_OTG",
|
||||
.min_uV = 3300000,
|
||||
.max_uV = 3300000,
|
||||
.always_on = 1,
|
||||
},
|
||||
};
|
||||
|
||||
/* LCD */
|
||||
static struct regulator_init_data wm8350_ldo3_data = {
|
||||
.constraints = {
|
||||
.name = "PVDD_LCD",
|
||||
.min_uV = 3000000,
|
||||
.max_uV = 3000000,
|
||||
.always_on = 1,
|
||||
},
|
||||
};
|
||||
|
||||
/* OTGi/1190-EV1 HPVDD & AVDD */
|
||||
static struct regulator_init_data wm8350_ldo4_data = {
|
||||
.constraints = {
|
||||
.name = "PVDD_OTGI/HPVDD/AVDD",
|
||||
.min_uV = 1200000,
|
||||
.max_uV = 1200000,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct {
|
||||
int regulator;
|
||||
struct regulator_init_data *initdata;
|
||||
} wm1190_regulators[] = {
|
||||
{ WM8350_DCDC_1, &wm8350_dcdc1_data },
|
||||
{ WM8350_DCDC_3, &wm8350_dcdc3_data },
|
||||
{ WM8350_DCDC_4, &wm8350_dcdc4_data },
|
||||
{ WM8350_DCDC_6, &wm8350_dcdc6_data },
|
||||
{ WM8350_LDO_1, &wm8350_ldo1_data },
|
||||
{ WM8350_LDO_2, &wm8350_ldo2_data },
|
||||
{ WM8350_LDO_3, &wm8350_ldo3_data },
|
||||
{ WM8350_LDO_4, &wm8350_ldo4_data },
|
||||
};
|
||||
|
||||
static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Instantiate the regulators */
|
||||
for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
|
||||
wm8350_register_regulator(wm8350,
|
||||
wm1190_regulators[i].regulator,
|
||||
wm1190_regulators[i].initdata);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
|
||||
.init = smdk6410_wm8350_init,
|
||||
.irq_high = 1,
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct i2c_board_info i2c_devs0[] __initdata = {
|
||||
{ I2C_BOARD_INFO("24c08", 0x50), },
|
||||
{ I2C_BOARD_INFO("wm8580", 0x1b), },
|
||||
|
||||
#ifdef CONFIG_SMDK6410_WM1190_EV1
|
||||
{ I2C_BOARD_INFO("wm8350", 0x1a),
|
||||
.platform_data = &smdk6410_wm8350_pdata,
|
||||
.irq = S3C_EINT(12),
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct i2c_board_info i2c_devs1[] __initdata = {
|
||||
|
@ -155,9 +339,23 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
|
|||
|
||||
static void __init smdk6410_map_io(void)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
|
||||
|
||||
/* set the LCD type */
|
||||
|
||||
tmp = __raw_readl(S3C64XX_SPCON);
|
||||
tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
|
||||
tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
|
||||
__raw_writel(tmp, S3C64XX_SPCON);
|
||||
|
||||
/* remove the lcd bypass */
|
||||
tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
|
||||
tmp &= ~MIFPCON_LCD_BYPASS;
|
||||
__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
|
||||
}
|
||||
|
||||
static void __init smdk6410_machine_init(void)
|
||||
|
|
|
@ -21,8 +21,6 @@
|
|||
#include <linux/mmc/card.h>
|
||||
#include <linux/mmc/host.h>
|
||||
|
||||
#include <mach/gpio.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/regs-sdhci.h>
|
||||
#include <plat/sdhci.h>
|
||||
|
||||
|
@ -35,22 +33,6 @@ char *s3c6410_hsmmc_clksrcs[4] = {
|
|||
/* [3] = "48m", - note not succesfully used yet */
|
||||
};
|
||||
|
||||
void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
|
||||
{
|
||||
unsigned int gpio;
|
||||
unsigned int end;
|
||||
|
||||
end = S3C64XX_GPG(2 + width);
|
||||
|
||||
/* Set all the necessary GPG pins to special-function 0 */
|
||||
for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
|
||||
s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
|
||||
}
|
||||
|
||||
void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
|
||||
void __iomem *r,
|
||||
|
@ -84,19 +66,3 @@ void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
|
|||
writel(ctrl3, r + S3C_SDHCI_CONTROL3);
|
||||
}
|
||||
|
||||
void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
|
||||
{
|
||||
unsigned int gpio;
|
||||
unsigned int end;
|
||||
|
||||
end = S3C64XX_GPH(2 + width);
|
||||
|
||||
/* Set all the necessary GPG pins to special-function 0 */
|
||||
for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
|
||||
s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
|
||||
}
|
||||
|
|
|
@ -116,7 +116,7 @@ void __init versatile_init_irq(void)
|
|||
{
|
||||
unsigned int i;
|
||||
|
||||
vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0);
|
||||
vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
|
||||
|
||||
set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
|
||||
|
||||
|
|
|
@ -71,6 +71,15 @@ config S3C2410_PM_DEBUG
|
|||
Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
|
||||
for more information.
|
||||
|
||||
config S3C_PM_DEBUG_LED_SMDK
|
||||
bool "SMDK LED suspend/resume debugging"
|
||||
depends on PM && (MACH_SMDK6410)
|
||||
help
|
||||
Say Y here to enable the use of the SMDK LEDs on the baseboard
|
||||
for debugging of the state of the suspend and resume process.
|
||||
|
||||
Note, this currently only works for S3C64XX based SMDK boards.
|
||||
|
||||
config S3C2410_PM_CHECK
|
||||
bool "S3C2410 PM Suspend Memory CRC"
|
||||
depends on PM && CRC32
|
||||
|
@ -150,6 +159,13 @@ config S3C_GPIO_CFG_S3C64XX
|
|||
Internal configuration to enable S3C64XX style GPIO configuration
|
||||
functions.
|
||||
|
||||
# DMA
|
||||
|
||||
config S3C_DMA
|
||||
bool
|
||||
help
|
||||
Internal configuration for S3C DMA core
|
||||
|
||||
# device definitions to compile in
|
||||
|
||||
config S3C_DEV_HSMMC
|
||||
|
@ -172,4 +188,14 @@ config S3C_DEV_FB
|
|||
help
|
||||
Compile in platform device definition for framebuffer
|
||||
|
||||
config S3C_DEV_USB_HOST
|
||||
bool
|
||||
help
|
||||
Compile in platform device definition for USB host.
|
||||
|
||||
config S3C_DEV_USB_HSOTG
|
||||
bool
|
||||
help
|
||||
Compile in platform device definition for USB high-speed OtG
|
||||
|
||||
endif
|
||||
|
|
|
@ -18,9 +18,14 @@ obj-y += pwm-clock.o
|
|||
obj-y += gpio.o
|
||||
obj-y += gpio-config.o
|
||||
|
||||
# DMA support
|
||||
|
||||
obj-$(CONFIG_S3C_DMA) += dma.o
|
||||
|
||||
# PM support
|
||||
|
||||
obj-$(CONFIG_PM) += pm.o
|
||||
obj-$(CONFIG_PM) += pm-gpio.o
|
||||
obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o
|
||||
|
||||
# devices
|
||||
|
@ -30,3 +35,5 @@ obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o
|
|||
obj-y += dev-i2c0.o
|
||||
obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o
|
||||
obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o
|
||||
obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o
|
||||
obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o
|
||||
|
|
41
arch/arm/plat-s3c/dev-usb-hsotg.c
Normal file
41
arch/arm/plat-s3c/dev-usb-hsotg.c
Normal file
|
@ -0,0 +1,41 @@
|
|||
/* linux/arch/arm/plat-s3c/dev-usb-hsotg.c
|
||||
*
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* S3C series device definition for USB high-speed UDC/OtG block
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/devs.h>
|
||||
|
||||
static struct resource s3c_usb_hsotg_resources[] = {
|
||||
[0] = {
|
||||
.start = S3C_PA_USB_HSOTG,
|
||||
.end = S3C_PA_USB_HSOTG + 0x10000 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_OTG,
|
||||
.end = IRQ_OTG,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device s3c_device_usb_hsotg = {
|
||||
.name = "s3c-hsotg",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources),
|
||||
.resource = s3c_usb_hsotg_resources,
|
||||
};
|
50
arch/arm/plat-s3c/dev-usb.c
Normal file
50
arch/arm/plat-s3c/dev-usb.c
Normal file
|
@ -0,0 +1,50 @@
|
|||
/* linux/arch/arm/plat-s3c/dev-usb.c
|
||||
*
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* S3C series device definition for USB host
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/devs.h>
|
||||
|
||||
|
||||
static struct resource s3c_usb_resource[] = {
|
||||
[0] = {
|
||||
.start = S3C_PA_USBHOST,
|
||||
.end = S3C_PA_USBHOST + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_USBH,
|
||||
.end = IRQ_USBH,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
static u64 s3c_device_usb_dmamask = 0xffffffffUL;
|
||||
|
||||
struct platform_device s3c_device_usb = {
|
||||
.name = "s3c2410-ohci",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(s3c_usb_resource),
|
||||
.resource = s3c_usb_resource,
|
||||
.dev = {
|
||||
.dma_mask = &s3c_device_usb_dmamask,
|
||||
.coherent_dma_mask = 0xffffffffUL
|
||||
}
|
||||
};
|
||||
|
||||
EXPORT_SYMBOL(s3c_device_usb);
|
86
arch/arm/plat-s3c/dma.c
Normal file
86
arch/arm/plat-s3c/dma.c
Normal file
|
@ -0,0 +1,86 @@
|
|||
/* linux/arch/arm/plat-s3c/dma.c
|
||||
*
|
||||
* Copyright (c) 2003-2005,2006,2009 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* S3C DMA core
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
struct s3c2410_dma_buf;
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/errno.h>
|
||||
|
||||
#include <mach/dma.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include <plat/dma-plat.h>
|
||||
|
||||
/* dma channel state information */
|
||||
struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
|
||||
struct s3c2410_dma_chan *s3c_dma_chan_map[DMACH_MAX];
|
||||
|
||||
/* s3c_dma_lookup_channel
|
||||
*
|
||||
* change the dma channel number given into a real dma channel id
|
||||
*/
|
||||
|
||||
struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel)
|
||||
{
|
||||
if (channel & DMACH_LOW_LEVEL)
|
||||
return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
|
||||
else
|
||||
return s3c_dma_chan_map[channel];
|
||||
}
|
||||
|
||||
/* do we need to protect the settings of the fields from
|
||||
* irq?
|
||||
*/
|
||||
|
||||
int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
|
||||
if (chan == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
|
||||
|
||||
chan->op_fn = rtn;
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(s3c2410_dma_set_opfn);
|
||||
|
||||
int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
|
||||
if (chan == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
|
||||
|
||||
chan->callback_fn = rtn;
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
|
||||
|
||||
int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
|
||||
if (chan == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
chan->flags = flags;
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(s3c2410_dma_setflags);
|
|
@ -16,7 +16,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <plat/gpio-core.h>
|
||||
#include <mach/gpio-core.h>
|
||||
|
||||
#ifdef CONFIG_S3C_GPIO_TRACK
|
||||
struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
|
||||
|
@ -140,6 +140,15 @@ __init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)
|
|||
if (!gc->get)
|
||||
gc->get = s3c_gpiolib_get;
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
if (chip->pm != NULL) {
|
||||
if (!chip->pm->save || !chip->pm->resume)
|
||||
printk(KERN_ERR "gpio: %s has missing PM functions\n",
|
||||
gc->label);
|
||||
} else
|
||||
printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);
|
||||
#endif
|
||||
|
||||
/* gpiochip_add() prints own failure message on error. */
|
||||
ret = gpiochip_add(gc);
|
||||
if (ret >= 0)
|
||||
|
|
|
@ -19,10 +19,12 @@ struct s3c_adc_client;
|
|||
extern int s3c_adc_start(struct s3c_adc_client *client,
|
||||
unsigned int channel, unsigned int nr_samples);
|
||||
|
||||
extern struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
|
||||
void (*select)(unsigned selected),
|
||||
void (*conv)(unsigned d0, unsigned d1),
|
||||
unsigned int is_ts);
|
||||
extern struct s3c_adc_client *
|
||||
s3c_adc_register(struct platform_device *pdev,
|
||||
void (*select)(unsigned selected),
|
||||
void (*conv)(unsigned d0, unsigned d1,
|
||||
unsigned *samples_left),
|
||||
unsigned int is_ts);
|
||||
|
||||
extern void s3c_adc_release(struct s3c_adc_client *client);
|
||||
|
||||
|
|
|
@ -50,6 +50,7 @@ extern struct clk clk_xtal;
|
|||
extern struct clk clk_ext;
|
||||
|
||||
/* S3C64XX specific clocks */
|
||||
extern struct clk clk_h2;
|
||||
extern struct clk clk_27m;
|
||||
extern struct clk clk_48m;
|
||||
|
||||
|
|
|
@ -69,3 +69,6 @@ extern struct sysdev_class s3c2412_sysclass;
|
|||
extern struct sysdev_class s3c2440_sysclass;
|
||||
extern struct sysdev_class s3c2442_sysclass;
|
||||
extern struct sysdev_class s3c2443_sysclass;
|
||||
extern struct sysdev_class s3c6410_sysclass;
|
||||
extern struct sysdev_class s3c64xx_sysclass;
|
||||
|
||||
|
|
|
@ -45,6 +45,7 @@ extern struct platform_device s3c_device_spi1;
|
|||
extern struct platform_device s3c_device_nand;
|
||||
|
||||
extern struct platform_device s3c_device_usbgadget;
|
||||
extern struct platform_device s3c_device_usb_hsotg;
|
||||
|
||||
/* s3c2440 specific devices */
|
||||
|
||||
|
|
22
arch/arm/plat-s3c/include/plat/dma-core.h
Normal file
22
arch/arm/plat-s3c/include/plat/dma-core.h
Normal file
|
@ -0,0 +1,22 @@
|
|||
/* arch/arm/plat-s3c/include/plat/dma.h
|
||||
*
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* Samsung S3C DMA core support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
extern struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel);
|
||||
|
||||
extern struct s3c2410_dma_chan *s3c_dma_chan_map[];
|
||||
|
||||
/* the currently allocated channel information */
|
||||
extern struct s3c2410_dma_chan s3c2410_chans[];
|
||||
|
||||
|
127
arch/arm/plat-s3c/include/plat/dma.h
Normal file
127
arch/arm/plat-s3c/include/plat/dma.h
Normal file
|
@ -0,0 +1,127 @@
|
|||
/* arch/arm/plat-s3c/include/plat/dma.h
|
||||
*
|
||||
* Copyright (C) 2003,2004,2006 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* Samsung S3C DMA support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
enum s3c2410_dma_buffresult {
|
||||
S3C2410_RES_OK,
|
||||
S3C2410_RES_ERR,
|
||||
S3C2410_RES_ABORT
|
||||
};
|
||||
|
||||
enum s3c2410_dmasrc {
|
||||
S3C2410_DMASRC_HW, /* source is memory */
|
||||
S3C2410_DMASRC_MEM /* source is hardware */
|
||||
};
|
||||
|
||||
/* enum s3c2410_chan_op
|
||||
*
|
||||
* operation codes passed to the DMA code by the user, and also used
|
||||
* to inform the current channel owner of any changes to the system state
|
||||
*/
|
||||
|
||||
enum s3c2410_chan_op {
|
||||
S3C2410_DMAOP_START,
|
||||
S3C2410_DMAOP_STOP,
|
||||
S3C2410_DMAOP_PAUSE,
|
||||
S3C2410_DMAOP_RESUME,
|
||||
S3C2410_DMAOP_FLUSH,
|
||||
S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
|
||||
S3C2410_DMAOP_STARTED, /* indicate channel started */
|
||||
};
|
||||
|
||||
struct s3c2410_dma_client {
|
||||
char *name;
|
||||
};
|
||||
|
||||
struct s3c2410_dma_chan;
|
||||
|
||||
/* s3c2410_dma_cbfn_t
|
||||
*
|
||||
* buffer callback routine type
|
||||
*/
|
||||
|
||||
typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
|
||||
void *buf, int size,
|
||||
enum s3c2410_dma_buffresult result);
|
||||
|
||||
typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
|
||||
enum s3c2410_chan_op );
|
||||
|
||||
|
||||
|
||||
/* s3c2410_dma_request
|
||||
*
|
||||
* request a dma channel exclusivley
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_request(unsigned int channel,
|
||||
struct s3c2410_dma_client *, void *dev);
|
||||
|
||||
|
||||
/* s3c2410_dma_ctrl
|
||||
*
|
||||
* change the state of the dma channel
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
|
||||
|
||||
/* s3c2410_dma_setflags
|
||||
*
|
||||
* set the channel's flags to a given state
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_setflags(unsigned int channel,
|
||||
unsigned int flags);
|
||||
|
||||
/* s3c2410_dma_free
|
||||
*
|
||||
* free the dma channel (will also abort any outstanding operations)
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
|
||||
|
||||
/* s3c2410_dma_enqueue
|
||||
*
|
||||
* place the given buffer onto the queue of operations for the channel.
|
||||
* The buffer must be allocated from dma coherent memory, or the Dcache/WB
|
||||
* drained before the buffer is given to the DMA system.
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
|
||||
dma_addr_t data, int size);
|
||||
|
||||
/* s3c2410_dma_config
|
||||
*
|
||||
* configure the dma channel
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_config(unsigned int channel, int xferunit);
|
||||
|
||||
/* s3c2410_dma_devconfig
|
||||
*
|
||||
* configure the device we're talking to
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
|
||||
unsigned long devaddr);
|
||||
|
||||
/* s3c2410_dma_getposition
|
||||
*
|
||||
* get the position that the dma transfer is currently at
|
||||
*/
|
||||
|
||||
extern int s3c2410_dma_getposition(unsigned int channel,
|
||||
dma_addr_t *src, dma_addr_t *dest);
|
||||
|
||||
extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
|
||||
extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
|
||||
|
||||
|
|
@ -20,6 +20,18 @@
|
|||
* specific code.
|
||||
*/
|
||||
|
||||
struct s3c_gpio_chip;
|
||||
|
||||
/**
|
||||
* struct s3c_gpio_pm - power management (suspend/resume) information
|
||||
* @save: Routine to save the state of the GPIO block
|
||||
* @resume: Routine to resume the GPIO block.
|
||||
*/
|
||||
struct s3c_gpio_pm {
|
||||
void (*save)(struct s3c_gpio_chip *chip);
|
||||
void (*resume)(struct s3c_gpio_chip *chip);
|
||||
};
|
||||
|
||||
struct s3c_gpio_cfg;
|
||||
|
||||
/**
|
||||
|
@ -27,6 +39,7 @@ struct s3c_gpio_cfg;
|
|||
* @chip: The chip structure to be exported via gpiolib.
|
||||
* @base: The base pointer to the gpio configuration registers.
|
||||
* @config: special function and pull-resistor control information.
|
||||
* @pm_save: Save information for suspend/resume support.
|
||||
*
|
||||
* This wrapper provides the necessary information for the Samsung
|
||||
* specific gpios being registered with gpiolib.
|
||||
|
@ -34,7 +47,11 @@ struct s3c_gpio_cfg;
|
|||
struct s3c_gpio_chip {
|
||||
struct gpio_chip chip;
|
||||
struct s3c_gpio_cfg *config;
|
||||
struct s3c_gpio_pm *pm;
|
||||
void __iomem *base;
|
||||
#ifdef CONFIG_PM
|
||||
u32 pm_save[4];
|
||||
#endif
|
||||
};
|
||||
|
||||
static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc)
|
||||
|
@ -75,3 +92,16 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip)
|
|||
|
||||
static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { }
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
extern struct s3c_gpio_pm s3c_gpio_pm_1bit;
|
||||
extern struct s3c_gpio_pm s3c_gpio_pm_2bit;
|
||||
extern struct s3c_gpio_pm s3c_gpio_pm_4bit;
|
||||
#define __gpio_pm(x) x
|
||||
#else
|
||||
#define s3c_gpio_pm_1bit NULL
|
||||
#define s3c_gpio_pm_2bit NULL
|
||||
#define s3c_gpio_pm_4bit NULL
|
||||
#define __gpio_pm(x) NULL
|
||||
|
||||
#endif /* CONFIG_PM */
|
||||
|
|
|
@ -44,6 +44,8 @@ extern void (*pm_cpu_sleep)(void);
|
|||
|
||||
extern unsigned long s3c_pm_flags;
|
||||
|
||||
extern unsigned char pm_uart_udivslot; /* true to save UART UDIVSLOT */
|
||||
|
||||
/* from sleep.S */
|
||||
|
||||
extern int s3c_cpu_save(unsigned long *saveblk);
|
||||
|
@ -88,6 +90,7 @@ struct pm_uart_save {
|
|||
u32 ufcon;
|
||||
u32 umcon;
|
||||
u32 ubrdiv;
|
||||
u32 udivslot;
|
||||
};
|
||||
|
||||
/* helper functions to save/restore lists of registers. */
|
||||
|
@ -124,6 +127,18 @@ extern void s3c_pm_dbg(const char *msg, ...);
|
|||
#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
|
||||
/**
|
||||
* s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs
|
||||
* @set: set bits for the state of the LEDs
|
||||
* @clear: clear bits for the state of the LEDs.
|
||||
*/
|
||||
extern void s3c_pm_debug_smdkled(u32 set, u32 clear);
|
||||
|
||||
#else
|
||||
static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { }
|
||||
#endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */
|
||||
|
||||
/* suspend memory checking */
|
||||
|
||||
#ifdef CONFIG_S3C2410_PM_CHECK
|
||||
|
|
|
@ -189,6 +189,11 @@
|
|||
|
||||
#define S3C2443_DIVSLOT (0x2C)
|
||||
|
||||
/* S3C64XX interrupt registers. */
|
||||
#define S3C64XX_UINTP 0x30
|
||||
#define S3C64XX_UINTSP 0x34
|
||||
#define S3C64XX_UINTM 0x38
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* struct s3c24xx_uart_clksrc
|
||||
|
|
|
@ -67,12 +67,52 @@ extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
|
|||
|
||||
/* Helper function availablity */
|
||||
|
||||
extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
|
||||
extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
|
||||
|
||||
/* S3C6400 SDHCI setup */
|
||||
|
||||
#ifdef CONFIG_S3C6400_SETUP_SDHCI
|
||||
extern char *s3c6400_hsmmc_clksrcs[4];
|
||||
|
||||
#ifdef CONFIG_S3C_DEV_HSMMC
|
||||
extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
|
||||
void __iomem *r,
|
||||
struct mmc_ios *ios,
|
||||
struct mmc_card *card);
|
||||
|
||||
static inline void s3c6400_default_sdhci0(void)
|
||||
{
|
||||
s3c_hsmmc0_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
|
||||
s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
|
||||
s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
|
||||
}
|
||||
|
||||
#else
|
||||
static inline void s3c6400_default_sdhci0(void) { }
|
||||
#endif /* CONFIG_S3C_DEV_HSMMC */
|
||||
|
||||
#ifdef CONFIG_S3C_DEV_HSMMC1
|
||||
static inline void s3c6400_default_sdhci1(void)
|
||||
{
|
||||
s3c_hsmmc1_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
|
||||
s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
|
||||
s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
|
||||
}
|
||||
#else
|
||||
static inline void s3c6400_default_sdhci1(void) { }
|
||||
#endif /* CONFIG_S3C_DEV_HSMMC1 */
|
||||
|
||||
#else
|
||||
static inline void s3c6400_default_sdhci0(void) { }
|
||||
static inline void s3c6400_default_sdhci1(void) { }
|
||||
#endif /* CONFIG_S3C6400_SETUP_SDHCI */
|
||||
|
||||
/* S3C6410 SDHCI setup */
|
||||
|
||||
#ifdef CONFIG_S3C6410_SETUP_SDHCI
|
||||
extern char *s3c6410_hsmmc_clksrcs[4];
|
||||
|
||||
extern void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
|
||||
extern void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
|
||||
|
||||
extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
|
||||
void __iomem *r,
|
||||
struct mmc_ios *ios,
|
||||
|
@ -82,7 +122,7 @@ extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
|
|||
static inline void s3c6410_default_sdhci0(void)
|
||||
{
|
||||
s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
|
||||
s3c_hsmmc0_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio;
|
||||
s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
|
||||
s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
|
||||
}
|
||||
#else
|
||||
|
@ -93,7 +133,7 @@ static inline void s3c6410_default_sdhci0(void) { }
|
|||
static inline void s3c6410_default_sdhci1(void)
|
||||
{
|
||||
s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
|
||||
s3c_hsmmc1_def_platdata.cfg_gpio = s3c6410_setup_sdhci1_cfg_gpio;
|
||||
s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
|
||||
s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
|
||||
}
|
||||
#else
|
||||
|
|
29
arch/arm/plat-s3c/include/plat/udc-hs.h
Normal file
29
arch/arm/plat-s3c/include/plat/udc-hs.h
Normal file
|
@ -0,0 +1,29 @@
|
|||
/* arch/arm/plat-s3c/include/plat/udc-hs.h
|
||||
*
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* S3C USB2.0 High-speed / OtG platform information
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
enum s3c_hostg_dmamode {
|
||||
S3C_HSOTG_DMA_NONE, /* do not use DMA at-all */
|
||||
S3C_HSOTG_DMA_ONLY, /* always use DMA */
|
||||
S3C_HSOTG_DMA_DRV, /* DMA is chosen by driver */
|
||||
};
|
||||
|
||||
/**
|
||||
* struct s3c_hsotg_plat - platform data for high-speed otg/udc
|
||||
* @dma: Whether to use DMA or not.
|
||||
* @is_osc: The clock source is an oscillator, not a crystal
|
||||
*/
|
||||
struct s3c_hsotg_plat {
|
||||
enum s3c_hostg_dmamode dma;
|
||||
unsigned int is_osc : 1;
|
||||
};
|
49
arch/arm/plat-s3c/include/plat/watchdog-reset.h
Normal file
49
arch/arm/plat-s3c/include/plat/watchdog-reset.h
Normal file
|
@ -0,0 +1,49 @@
|
|||
/* arch/arm/plat-s3c/include/plat/watchdog-reset.h
|
||||
*
|
||||
* Copyright (c) 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* S3C2410 - System define for arch_reset() function
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <plat/regs-watchdog.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
static inline void arch_wdt_reset(void)
|
||||
{
|
||||
struct clk *wdtclk;
|
||||
|
||||
printk("arch_reset: attempting watchdog reset\n");
|
||||
|
||||
__raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
|
||||
|
||||
wdtclk = clk_get(NULL, "watchdog");
|
||||
if (!IS_ERR(wdtclk)) {
|
||||
clk_enable(wdtclk);
|
||||
} else
|
||||
printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
|
||||
|
||||
/* put initial values into count and data */
|
||||
__raw_writel(0x80, S3C2410_WTCNT);
|
||||
__raw_writel(0x80, S3C2410_WTDAT);
|
||||
|
||||
/* set the watchdog to go and reset... */
|
||||
__raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
|
||||
S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
|
||||
|
||||
/* wait for reset to assert... */
|
||||
mdelay(500);
|
||||
|
||||
printk(KERN_ERR "Watchdog reset failed to assert reset\n");
|
||||
|
||||
/* delay to allow the serial port to show the message */
|
||||
mdelay(50);
|
||||
}
|
380
arch/arm/plat-s3c/pm-gpio.c
Normal file
380
arch/arm/plat-s3c/pm-gpio.c
Normal file
|
@ -0,0 +1,380 @@
|
|||
|
||||
/* linux/arch/arm/plat-s3c/pm-gpio.c
|
||||
*
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* S3C series GPIO PM code
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <mach/gpio-core.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
/* PM GPIO helpers */
|
||||
|
||||
#define OFFS_CON (0x00)
|
||||
#define OFFS_DAT (0x04)
|
||||
#define OFFS_UP (0x08)
|
||||
|
||||
static void s3c_gpio_pm_1bit_save(struct s3c_gpio_chip *chip)
|
||||
{
|
||||
chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
|
||||
chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
|
||||
}
|
||||
|
||||
static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip)
|
||||
{
|
||||
void __iomem *base = chip->base;
|
||||
u32 old_gpcon = __raw_readl(base + OFFS_CON);
|
||||
u32 old_gpdat = __raw_readl(base + OFFS_DAT);
|
||||
u32 gps_gpcon = chip->pm_save[0];
|
||||
u32 gps_gpdat = chip->pm_save[1];
|
||||
u32 gpcon;
|
||||
|
||||
/* GPACON only has one bit per control / data and no PULLUPs.
|
||||
* GPACON[x] = 0 => Output, 1 => SFN */
|
||||
|
||||
/* first set all SFN bits to SFN */
|
||||
|
||||
gpcon = old_gpcon | gps_gpcon;
|
||||
__raw_writel(gpcon, base + OFFS_CON);
|
||||
|
||||
/* now set all the other bits */
|
||||
|
||||
__raw_writel(gps_gpdat, base + OFFS_DAT);
|
||||
__raw_writel(gps_gpcon, base + OFFS_CON);
|
||||
|
||||
S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
|
||||
chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
|
||||
}
|
||||
|
||||
struct s3c_gpio_pm s3c_gpio_pm_1bit = {
|
||||
.save = s3c_gpio_pm_1bit_save,
|
||||
.resume = s3c_gpio_pm_1bit_resume,
|
||||
};
|
||||
|
||||
static void s3c_gpio_pm_2bit_save(struct s3c_gpio_chip *chip)
|
||||
{
|
||||
chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
|
||||
chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
|
||||
chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP);
|
||||
}
|
||||
|
||||
/* Test whether the given masked+shifted bits of an GPIO configuration
|
||||
* are one of the SFN (special function) modes. */
|
||||
|
||||
static inline int is_sfn(unsigned long con)
|
||||
{
|
||||
return con >= 2;
|
||||
}
|
||||
|
||||
/* Test if the given masked+shifted GPIO configuration is an input */
|
||||
|
||||
static inline int is_in(unsigned long con)
|
||||
{
|
||||
return con == 0;
|
||||
}
|
||||
|
||||
/* Test if the given masked+shifted GPIO configuration is an output */
|
||||
|
||||
static inline int is_out(unsigned long con)
|
||||
{
|
||||
return con == 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* s3c_gpio_pm_2bit_resume() - restore the given GPIO bank
|
||||
* @chip: The chip information to resume.
|
||||
*
|
||||
* Restore one of the GPIO banks that was saved during suspend. This is
|
||||
* not as simple as once thought, due to the possibility of glitches
|
||||
* from the order that the CON and DAT registers are set in.
|
||||
*
|
||||
* The three states the pin can be are {IN,OUT,SFN} which gives us 9
|
||||
* combinations of changes to check. Three of these, if the pin stays
|
||||
* in the same configuration can be discounted. This leaves us with
|
||||
* the following:
|
||||
*
|
||||
* { IN => OUT } Change DAT first
|
||||
* { IN => SFN } Change CON first
|
||||
* { OUT => SFN } Change CON first, so new data will not glitch
|
||||
* { OUT => IN } Change CON first, so new data will not glitch
|
||||
* { SFN => IN } Change CON first
|
||||
* { SFN => OUT } Change DAT first, so new data will not glitch [1]
|
||||
*
|
||||
* We do not currently deal with the UP registers as these control
|
||||
* weak resistors, so a small delay in change should not need to bring
|
||||
* these into the calculations.
|
||||
*
|
||||
* [1] this assumes that writing to a pin DAT whilst in SFN will set the
|
||||
* state for when it is next output.
|
||||
*/
|
||||
static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip)
|
||||
{
|
||||
void __iomem *base = chip->base;
|
||||
u32 old_gpcon = __raw_readl(base + OFFS_CON);
|
||||
u32 old_gpdat = __raw_readl(base + OFFS_DAT);
|
||||
u32 gps_gpcon = chip->pm_save[0];
|
||||
u32 gps_gpdat = chip->pm_save[1];
|
||||
u32 gpcon, old, new, mask;
|
||||
u32 change_mask = 0x0;
|
||||
int nr;
|
||||
|
||||
/* restore GPIO pull-up settings */
|
||||
__raw_writel(chip->pm_save[2], base + OFFS_UP);
|
||||
|
||||
/* Create a change_mask of all the items that need to have
|
||||
* their CON value changed before their DAT value, so that
|
||||
* we minimise the work between the two settings.
|
||||
*/
|
||||
|
||||
for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
|
||||
old = (old_gpcon & mask) >> nr;
|
||||
new = (gps_gpcon & mask) >> nr;
|
||||
|
||||
/* If there is no change, then skip */
|
||||
|
||||
if (old == new)
|
||||
continue;
|
||||
|
||||
/* If both are special function, then skip */
|
||||
|
||||
if (is_sfn(old) && is_sfn(new))
|
||||
continue;
|
||||
|
||||
/* Change is IN => OUT, do not change now */
|
||||
|
||||
if (is_in(old) && is_out(new))
|
||||
continue;
|
||||
|
||||
/* Change is SFN => OUT, do not change now */
|
||||
|
||||
if (is_sfn(old) && is_out(new))
|
||||
continue;
|
||||
|
||||
/* We should now be at the case of IN=>SFN,
|
||||
* OUT=>SFN, OUT=>IN, SFN=>IN. */
|
||||
|
||||
change_mask |= mask;
|
||||
}
|
||||
|
||||
|
||||
/* Write the new CON settings */
|
||||
|
||||
gpcon = old_gpcon & ~change_mask;
|
||||
gpcon |= gps_gpcon & change_mask;
|
||||
|
||||
__raw_writel(gpcon, base + OFFS_CON);
|
||||
|
||||
/* Now change any items that require DAT,CON */
|
||||
|
||||
__raw_writel(gps_gpdat, base + OFFS_DAT);
|
||||
__raw_writel(gps_gpcon, base + OFFS_CON);
|
||||
|
||||
S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
|
||||
chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
|
||||
}
|
||||
|
||||
struct s3c_gpio_pm s3c_gpio_pm_2bit = {
|
||||
.save = s3c_gpio_pm_2bit_save,
|
||||
.resume = s3c_gpio_pm_2bit_resume,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ARCH_S3C64XX
|
||||
static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
|
||||
{
|
||||
chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
|
||||
chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT);
|
||||
chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP);
|
||||
|
||||
if (chip->chip.ngpio > 8)
|
||||
chip->pm_save[0] = __raw_readl(chip->base - 4);
|
||||
}
|
||||
|
||||
static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon)
|
||||
{
|
||||
u32 old, new, mask;
|
||||
u32 change_mask = 0x0;
|
||||
int nr;
|
||||
|
||||
for (nr = 0, mask = 0x0f; nr < 16; nr += 4, mask <<= 4) {
|
||||
old = (old_gpcon & mask) >> nr;
|
||||
new = (gps_gpcon & mask) >> nr;
|
||||
|
||||
/* If there is no change, then skip */
|
||||
|
||||
if (old == new)
|
||||
continue;
|
||||
|
||||
/* If both are special function, then skip */
|
||||
|
||||
if (is_sfn(old) && is_sfn(new))
|
||||
continue;
|
||||
|
||||
/* Change is IN => OUT, do not change now */
|
||||
|
||||
if (is_in(old) && is_out(new))
|
||||
continue;
|
||||
|
||||
/* Change is SFN => OUT, do not change now */
|
||||
|
||||
if (is_sfn(old) && is_out(new))
|
||||
continue;
|
||||
|
||||
/* We should now be at the case of IN=>SFN,
|
||||
* OUT=>SFN, OUT=>IN, SFN=>IN. */
|
||||
|
||||
change_mask |= mask;
|
||||
}
|
||||
|
||||
return change_mask;
|
||||
}
|
||||
|
||||
static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index)
|
||||
{
|
||||
void __iomem *con = chip->base + (index * 4);
|
||||
u32 old_gpcon = __raw_readl(con);
|
||||
u32 gps_gpcon = chip->pm_save[index + 1];
|
||||
u32 gpcon, mask;
|
||||
|
||||
mask = s3c_gpio_pm_4bit_mask(old_gpcon, gps_gpcon);
|
||||
|
||||
gpcon = old_gpcon & ~mask;
|
||||
gpcon |= gps_gpcon & mask;
|
||||
|
||||
__raw_writel(gpcon, con);
|
||||
}
|
||||
|
||||
static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip)
|
||||
{
|
||||
void __iomem *base = chip->base;
|
||||
u32 old_gpcon[2];
|
||||
u32 old_gpdat = __raw_readl(base + OFFS_DAT);
|
||||
u32 gps_gpdat = chip->pm_save[2];
|
||||
|
||||
/* First, modify the CON settings */
|
||||
|
||||
old_gpcon[0] = 0;
|
||||
old_gpcon[1] = __raw_readl(base + OFFS_CON);
|
||||
|
||||
s3c_gpio_pm_4bit_con(chip, 0);
|
||||
if (chip->chip.ngpio > 8) {
|
||||
old_gpcon[0] = __raw_readl(base - 4);
|
||||
s3c_gpio_pm_4bit_con(chip, -1);
|
||||
}
|
||||
|
||||
/* Now change the configurations that require DAT,CON */
|
||||
|
||||
__raw_writel(chip->pm_save[2], base + OFFS_DAT);
|
||||
__raw_writel(chip->pm_save[1], base + OFFS_CON);
|
||||
if (chip->chip.ngpio > 8)
|
||||
__raw_writel(chip->pm_save[0], base - 4);
|
||||
|
||||
__raw_writel(chip->pm_save[2], base + OFFS_DAT);
|
||||
__raw_writel(chip->pm_save[3], base + OFFS_UP);
|
||||
|
||||
if (chip->chip.ngpio > 8) {
|
||||
S3C_PMDBG("%s: CON4 %08x,%08x => %08x,%08x, DAT %08x => %08x\n",
|
||||
chip->chip.label, old_gpcon[0], old_gpcon[1],
|
||||
__raw_readl(base - 4),
|
||||
__raw_readl(base + OFFS_CON),
|
||||
old_gpdat, gps_gpdat);
|
||||
} else
|
||||
S3C_PMDBG("%s: CON4 %08x => %08x, DAT %08x => %08x\n",
|
||||
chip->chip.label, old_gpcon[1],
|
||||
__raw_readl(base + OFFS_CON),
|
||||
old_gpdat, gps_gpdat);
|
||||
}
|
||||
|
||||
struct s3c_gpio_pm s3c_gpio_pm_4bit = {
|
||||
.save = s3c_gpio_pm_4bit_save,
|
||||
.resume = s3c_gpio_pm_4bit_resume,
|
||||
};
|
||||
#endif /* CONFIG_ARCH_S3C64XX */
|
||||
|
||||
/**
|
||||
* s3c_pm_save_gpio() - save gpio chip data for suspend
|
||||
* @ourchip: The chip for suspend.
|
||||
*/
|
||||
static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip)
|
||||
{
|
||||
struct s3c_gpio_pm *pm = ourchip->pm;
|
||||
|
||||
if (pm == NULL || pm->save == NULL)
|
||||
S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
|
||||
else
|
||||
pm->save(ourchip);
|
||||
}
|
||||
|
||||
/**
|
||||
* s3c_pm_save_gpios() - Save the state of the GPIO banks.
|
||||
*
|
||||
* For all the GPIO banks, save the state of each one ready for going
|
||||
* into a suspend mode.
|
||||
*/
|
||||
void s3c_pm_save_gpios(void)
|
||||
{
|
||||
struct s3c_gpio_chip *ourchip;
|
||||
unsigned int gpio_nr;
|
||||
|
||||
for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
|
||||
ourchip = s3c_gpiolib_getchip(gpio_nr);
|
||||
if (!ourchip)
|
||||
continue;
|
||||
|
||||
s3c_pm_save_gpio(ourchip);
|
||||
|
||||
S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n",
|
||||
ourchip->chip.label,
|
||||
ourchip->pm_save[0],
|
||||
ourchip->pm_save[1],
|
||||
ourchip->pm_save[2],
|
||||
ourchip->pm_save[3]);
|
||||
|
||||
gpio_nr += ourchip->chip.ngpio;
|
||||
gpio_nr += CONFIG_S3C_GPIO_SPACE;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* s3c_pm_resume_gpio() - restore gpio chip data after suspend
|
||||
* @ourchip: The suspended chip.
|
||||
*/
|
||||
static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip)
|
||||
{
|
||||
struct s3c_gpio_pm *pm = ourchip->pm;
|
||||
|
||||
if (pm == NULL || pm->resume == NULL)
|
||||
S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
|
||||
else
|
||||
pm->resume(ourchip);
|
||||
}
|
||||
|
||||
void s3c_pm_restore_gpios(void)
|
||||
{
|
||||
struct s3c_gpio_chip *ourchip;
|
||||
unsigned int gpio_nr;
|
||||
|
||||
for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
|
||||
ourchip = s3c_gpiolib_getchip(gpio_nr);
|
||||
if (!ourchip)
|
||||
continue;
|
||||
|
||||
s3c_pm_resume_gpio(ourchip);
|
||||
|
||||
gpio_nr += ourchip->chip.ngpio;
|
||||
gpio_nr += CONFIG_S3C_GPIO_SPACE;
|
||||
}
|
||||
}
|
|
@ -21,11 +21,10 @@
|
|||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/regs-serial.h>
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <mach/regs-mem.h>
|
||||
#include <mach/regs-irq.h>
|
||||
#include <asm/irq.h>
|
||||
|
||||
|
@ -70,6 +69,8 @@ static inline void s3c_pm_debug_init(void)
|
|||
|
||||
/* Save the UART configurations if we are configured for debug. */
|
||||
|
||||
unsigned char pm_uart_udivslot;
|
||||
|
||||
#ifdef CONFIG_S3C2410_PM_DEBUG
|
||||
|
||||
struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS];
|
||||
|
@ -83,6 +84,12 @@ static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
|
|||
save->ufcon = __raw_readl(regs + S3C2410_UFCON);
|
||||
save->umcon = __raw_readl(regs + S3C2410_UMCON);
|
||||
save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
|
||||
|
||||
if (pm_uart_udivslot)
|
||||
save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
|
||||
|
||||
S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
|
||||
uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
|
||||
}
|
||||
|
||||
static void s3c_pm_save_uarts(void)
|
||||
|
@ -98,11 +105,16 @@ static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
|
|||
{
|
||||
void __iomem *regs = S3C_VA_UARTx(uart);
|
||||
|
||||
s3c_pm_arch_update_uart(regs, save);
|
||||
|
||||
__raw_writel(save->ulcon, regs + S3C2410_ULCON);
|
||||
__raw_writel(save->ucon, regs + S3C2410_UCON);
|
||||
__raw_writel(save->ufcon, regs + S3C2410_UFCON);
|
||||
__raw_writel(save->umcon, regs + S3C2410_UMCON);
|
||||
__raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
|
||||
|
||||
if (pm_uart_udivslot)
|
||||
__raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
|
||||
}
|
||||
|
||||
static void s3c_pm_restore_uarts(void)
|
||||
|
@ -313,6 +325,9 @@ static int s3c_pm_enter(suspend_state_t state)
|
|||
|
||||
S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
|
||||
|
||||
/* LEDs should now be 1110 */
|
||||
s3c_pm_debug_smdkled(1 << 1, 0);
|
||||
|
||||
s3c_pm_check_restore();
|
||||
|
||||
/* ok, let's return from sleep */
|
||||
|
|
|
@ -71,6 +71,7 @@ config PM_SIMTEC
|
|||
config S3C2410_DMA
|
||||
bool "S3C2410 DMA support"
|
||||
depends on ARCH_S3C2410
|
||||
select S3C_DMA
|
||||
help
|
||||
S3C2410 DMA support. This is needed for drivers like sound which
|
||||
use the S3C2410's DMA system to move data to and from the
|
||||
|
|
|
@ -45,7 +45,8 @@ struct s3c_adc_client {
|
|||
unsigned char channel;
|
||||
|
||||
void (*select_cb)(unsigned selected);
|
||||
void (*convert_cb)(unsigned val1, unsigned val2);
|
||||
void (*convert_cb)(unsigned val1, unsigned val2,
|
||||
unsigned *samples_left);
|
||||
};
|
||||
|
||||
struct adc_device {
|
||||
|
@ -158,7 +159,8 @@ static void s3c_adc_default_select(unsigned select)
|
|||
|
||||
struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
|
||||
void (*select)(unsigned int selected),
|
||||
void (*conv)(unsigned d0, unsigned d1),
|
||||
void (*conv)(unsigned d0, unsigned d1,
|
||||
unsigned *samples_left),
|
||||
unsigned int is_ts)
|
||||
{
|
||||
struct s3c_adc_client *client;
|
||||
|
@ -227,9 +229,10 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
|
|||
data1 = readl(adc->regs + S3C2410_ADCDAT1);
|
||||
adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1);
|
||||
|
||||
(client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff);
|
||||
client->nr_samples--;
|
||||
(client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff, &client->nr_samples);
|
||||
|
||||
if (--client->nr_samples > 0) {
|
||||
if (client->nr_samples > 0) {
|
||||
/* fire another conversion for this */
|
||||
|
||||
client->select_cb(1);
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/list.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
|
@ -47,27 +48,27 @@
|
|||
/* LED devices */
|
||||
|
||||
static struct s3c24xx_led_platdata smdk_pdata_led4 = {
|
||||
.gpio = S3C2410_GPF4,
|
||||
.gpio = S3C2410_GPF(4),
|
||||
.flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
|
||||
.name = "led4",
|
||||
.def_trigger = "timer",
|
||||
};
|
||||
|
||||
static struct s3c24xx_led_platdata smdk_pdata_led5 = {
|
||||
.gpio = S3C2410_GPF5,
|
||||
.gpio = S3C2410_GPF(5),
|
||||
.flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
|
||||
.name = "led5",
|
||||
.def_trigger = "nand-disk",
|
||||
};
|
||||
|
||||
static struct s3c24xx_led_platdata smdk_pdata_led6 = {
|
||||
.gpio = S3C2410_GPF6,
|
||||
.gpio = S3C2410_GPF(6),
|
||||
.flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
|
||||
.name = "led6",
|
||||
};
|
||||
|
||||
static struct s3c24xx_led_platdata smdk_pdata_led7 = {
|
||||
.gpio = S3C2410_GPF7,
|
||||
.gpio = S3C2410_GPF(7),
|
||||
.flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
|
||||
.name = "led7",
|
||||
};
|
||||
|
@ -184,15 +185,15 @@ void __init smdk_machine_init(void)
|
|||
{
|
||||
/* Configure the LEDs (even if we have no LED support)*/
|
||||
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPF4, S3C2410_GPF4_OUTP);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPF5, S3C2410_GPF5_OUTP);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPF6, S3C2410_GPF6_OUTP);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPF7, S3C2410_GPF7_OUTP);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT);
|
||||
|
||||
s3c2410_gpio_setpin(S3C2410_GPF4, 1);
|
||||
s3c2410_gpio_setpin(S3C2410_GPF5, 1);
|
||||
s3c2410_gpio_setpin(S3C2410_GPF6, 1);
|
||||
s3c2410_gpio_setpin(S3C2410_GPF7, 1);
|
||||
s3c2410_gpio_setpin(S3C2410_GPF(4), 1);
|
||||
s3c2410_gpio_setpin(S3C2410_GPF(5), 1);
|
||||
s3c2410_gpio_setpin(S3C2410_GPF(6), 1);
|
||||
s3c2410_gpio_setpin(S3C2410_GPF(7), 1);
|
||||
|
||||
if (machine_is_smdk2443())
|
||||
smdk_nand_info.twrph0 = 50;
|
||||
|
|
|
@ -136,36 +136,6 @@ struct platform_device *s3c24xx_uart_src[4] = {
|
|||
struct platform_device *s3c24xx_uart_devs[4] = {
|
||||
};
|
||||
|
||||
/* USB Host Controller */
|
||||
|
||||
static struct resource s3c_usb_resource[] = {
|
||||
[0] = {
|
||||
.start = S3C24XX_PA_USBHOST,
|
||||
.end = S3C24XX_PA_USBHOST + S3C24XX_SZ_USBHOST - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_USBH,
|
||||
.end = IRQ_USBH,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
static u64 s3c_device_usb_dmamask = 0xffffffffUL;
|
||||
|
||||
struct platform_device s3c_device_usb = {
|
||||
.name = "s3c2410-ohci",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(s3c_usb_resource),
|
||||
.resource = s3c_usb_resource,
|
||||
.dev = {
|
||||
.dma_mask = &s3c_device_usb_dmamask,
|
||||
.coherent_dma_mask = 0xffffffffUL
|
||||
}
|
||||
};
|
||||
|
||||
EXPORT_SYMBOL(s3c_device_usb);
|
||||
|
||||
/* LCD Controller */
|
||||
|
||||
static struct resource s3c_lcd_resource[] = {
|
||||
|
|
|
@ -31,10 +31,10 @@
|
|||
#include <asm/irq.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/dma.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/dma.h>
|
||||
#include <plat/dma-plat.h>
|
||||
#include <plat/regs-dma.h>
|
||||
|
||||
/* io map for dma */
|
||||
static void __iomem *dma_base;
|
||||
|
@ -44,8 +44,6 @@ static int dma_channels;
|
|||
|
||||
static struct s3c24xx_dma_selection dma_sel;
|
||||
|
||||
/* dma channel state information */
|
||||
struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
|
||||
|
||||
/* debugging functions */
|
||||
|
||||
|
@ -135,21 +133,6 @@ dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
|
|||
#define dbg_showchan(chan) do { } while(0)
|
||||
#endif /* CONFIG_S3C2410_DMA_DEBUG */
|
||||
|
||||
static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX];
|
||||
|
||||
/* lookup_dma_channel
|
||||
*
|
||||
* change the dma channel number given into a real dma channel id
|
||||
*/
|
||||
|
||||
static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel)
|
||||
{
|
||||
if (channel & DMACH_LOW_LEVEL)
|
||||
return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
|
||||
else
|
||||
return dma_chan_map[channel];
|
||||
}
|
||||
|
||||
/* s3c2410_dma_stats_timeout
|
||||
*
|
||||
* Update DMA stats from timeout info
|
||||
|
@ -214,8 +197,6 @@ s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
|
|||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* s3c2410_dma_loadbuffer
|
||||
*
|
||||
* load a buffer, and update the channel state
|
||||
|
@ -453,7 +434,7 @@ s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
|
|||
int s3c2410_dma_enqueue(unsigned int channel, void *id,
|
||||
dma_addr_t data, int size)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
|
||||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
struct s3c2410_dma_buf *buf;
|
||||
unsigned long flags;
|
||||
|
||||
|
@ -804,7 +785,7 @@ EXPORT_SYMBOL(s3c2410_dma_request);
|
|||
|
||||
int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
|
||||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
unsigned long flags;
|
||||
|
||||
if (chan == NULL)
|
||||
|
@ -836,7 +817,7 @@ int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
|
|||
chan->irq_claimed = 0;
|
||||
|
||||
if (!(channel & DMACH_LOW_LEVEL))
|
||||
dma_chan_map[channel] = NULL;
|
||||
s3c_dma_chan_map[channel] = NULL;
|
||||
|
||||
local_irq_restore(flags);
|
||||
|
||||
|
@ -995,7 +976,7 @@ static int s3c2410_dma_started(struct s3c2410_dma_chan *chan)
|
|||
int
|
||||
s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
|
||||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
|
||||
if (chan == NULL)
|
||||
return -EINVAL;
|
||||
|
@ -1038,14 +1019,13 @@ EXPORT_SYMBOL(s3c2410_dma_ctrl);
|
|||
/* s3c2410_dma_config
|
||||
*
|
||||
* xfersize: size of unit in bytes (1,2,4)
|
||||
* dcon: base value of the DCONx register
|
||||
*/
|
||||
|
||||
int s3c2410_dma_config(unsigned int channel,
|
||||
int xferunit,
|
||||
int dcon)
|
||||
int xferunit)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
|
||||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
unsigned int dcon;
|
||||
|
||||
pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
|
||||
__func__, channel, xferunit, dcon);
|
||||
|
@ -1055,10 +1035,33 @@ int s3c2410_dma_config(unsigned int channel,
|
|||
|
||||
pr_debug("%s: Initial dcon is %08x\n", __func__, dcon);
|
||||
|
||||
dcon |= chan->dcon & dma_sel.dcon_mask;
|
||||
dcon = chan->dcon & dma_sel.dcon_mask;
|
||||
|
||||
pr_debug("%s: New dcon is %08x\n", __func__, dcon);
|
||||
|
||||
switch (chan->req_ch) {
|
||||
case DMACH_I2S_IN:
|
||||
case DMACH_I2S_OUT:
|
||||
case DMACH_PCM_IN:
|
||||
case DMACH_PCM_OUT:
|
||||
case DMACH_MIC_IN:
|
||||
default:
|
||||
dcon |= S3C2410_DCON_HANDSHAKE;
|
||||
dcon |= S3C2410_DCON_SYNC_PCLK;
|
||||
break;
|
||||
|
||||
case DMACH_SDI:
|
||||
/* note, ensure if need HANDSHAKE or not */
|
||||
dcon |= S3C2410_DCON_SYNC_PCLK;
|
||||
break;
|
||||
|
||||
case DMACH_XD0:
|
||||
case DMACH_XD1:
|
||||
dcon |= S3C2410_DCON_HANDSHAKE;
|
||||
dcon |= S3C2410_DCON_SYNC_HCLK;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (xferunit) {
|
||||
case 1:
|
||||
dcon |= S3C2410_DCON_BYTE;
|
||||
|
@ -1090,58 +1093,6 @@ int s3c2410_dma_config(unsigned int channel,
|
|||
|
||||
EXPORT_SYMBOL(s3c2410_dma_config);
|
||||
|
||||
int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
|
||||
|
||||
if (chan == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
pr_debug("%s: chan=%p, flags=%08x\n", __func__, chan, flags);
|
||||
|
||||
chan->flags = flags;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(s3c2410_dma_setflags);
|
||||
|
||||
|
||||
/* do we need to protect the settings of the fields from
|
||||
* irq?
|
||||
*/
|
||||
|
||||
int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
|
||||
|
||||
if (chan == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
|
||||
|
||||
chan->op_fn = rtn;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(s3c2410_dma_set_opfn);
|
||||
|
||||
int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
|
||||
|
||||
if (chan == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
|
||||
|
||||
chan->callback_fn = rtn;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
|
||||
|
||||
/* s3c2410_dma_devconfig
|
||||
*
|
||||
|
@ -1150,29 +1101,38 @@ EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
|
|||
* source: S3C2410_DMASRC_HW: source is hardware
|
||||
* S3C2410_DMASRC_MEM: source is memory
|
||||
*
|
||||
* hwcfg: the value for xxxSTCn register,
|
||||
* bit 0: 0=increment pointer, 1=leave pointer
|
||||
* bit 1: 0=source is AHB, 1=source is APB
|
||||
*
|
||||
* devaddr: physical address of the source
|
||||
*/
|
||||
|
||||
int s3c2410_dma_devconfig(int channel,
|
||||
enum s3c2410_dmasrc source,
|
||||
int hwcfg,
|
||||
unsigned long devaddr)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
|
||||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
unsigned int hwcfg;
|
||||
|
||||
if (chan == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
|
||||
__func__, (int)source, hwcfg, devaddr);
|
||||
pr_debug("%s: source=%d, devaddr=%08lx\n",
|
||||
__func__, (int)source, devaddr);
|
||||
|
||||
chan->source = source;
|
||||
chan->dev_addr = devaddr;
|
||||
chan->hw_cfg = hwcfg;
|
||||
|
||||
switch (chan->req_ch) {
|
||||
case DMACH_XD0:
|
||||
case DMACH_XD1:
|
||||
hwcfg = 0; /* AHB */
|
||||
break;
|
||||
|
||||
default:
|
||||
hwcfg = S3C2410_DISRCC_APB;
|
||||
}
|
||||
|
||||
/* always assume our peripheral desintation is a fixed
|
||||
* address in memory. */
|
||||
hwcfg |= S3C2410_DISRCC_INC;
|
||||
|
||||
switch (source) {
|
||||
case S3C2410_DMASRC_HW:
|
||||
|
@ -1219,7 +1179,7 @@ EXPORT_SYMBOL(s3c2410_dma_devconfig);
|
|||
|
||||
int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *dst)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
|
||||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
|
||||
if (chan == NULL)
|
||||
return -EINVAL;
|
||||
|
@ -1278,8 +1238,8 @@ static int s3c2410_dma_resume(struct sys_device *dev)
|
|||
|
||||
printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
|
||||
|
||||
s3c2410_dma_config(no, cp->xfer_unit, cp->dcon);
|
||||
s3c2410_dma_devconfig(no, cp->source, cp->hw_cfg, cp->dev_addr);
|
||||
s3c2410_dma_config(no, cp->xfer_unit);
|
||||
s3c2410_dma_devconfig(no, cp->source, cp->dev_addr);
|
||||
|
||||
/* re-select the dma source for this channel */
|
||||
|
||||
|
@ -1476,7 +1436,8 @@ static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
|
|||
found:
|
||||
dmach = &s3c2410_chans[ch];
|
||||
dmach->map = ch_map;
|
||||
dma_chan_map[channel] = dmach;
|
||||
dmach->req_ch = channel;
|
||||
s3c_dma_chan_map[channel] = dmach;
|
||||
|
||||
/* select the channel */
|
||||
|
||||
|
|
|
@ -183,35 +183,19 @@ EXPORT_SYMBOL(s3c2410_modify_misccr);
|
|||
|
||||
int s3c2410_gpio_getirq(unsigned int pin)
|
||||
{
|
||||
if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15)
|
||||
return -1; /* not valid interrupts */
|
||||
if (pin < S3C2410_GPF(0) || pin > S3C2410_GPG(15))
|
||||
return -EINVAL; /* not valid interrupts */
|
||||
|
||||
if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7)
|
||||
return -1; /* not valid pin */
|
||||
if (pin < S3C2410_GPG(0) && pin > S3C2410_GPF(7))
|
||||
return -EINVAL; /* not valid pin */
|
||||
|
||||
if (pin < S3C2410_GPF4)
|
||||
return (pin - S3C2410_GPF0) + IRQ_EINT0;
|
||||
if (pin < S3C2410_GPF(4))
|
||||
return (pin - S3C2410_GPF(0)) + IRQ_EINT0;
|
||||
|
||||
if (pin < S3C2410_GPG0)
|
||||
return (pin - S3C2410_GPF4) + IRQ_EINT4;
|
||||
if (pin < S3C2410_GPG(0))
|
||||
return (pin - S3C2410_GPF(4)) + IRQ_EINT4;
|
||||
|
||||
return (pin - S3C2410_GPG0) + IRQ_EINT8;
|
||||
return (pin - S3C2410_GPG(0)) + IRQ_EINT8;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(s3c2410_gpio_getirq);
|
||||
|
||||
int s3c2410_gpio_irq2pin(unsigned int irq)
|
||||
{
|
||||
if (irq >= IRQ_EINT0 && irq <= IRQ_EINT3)
|
||||
return S3C2410_GPF0 + (irq - IRQ_EINT0);
|
||||
|
||||
if (irq >= IRQ_EINT4 && irq <= IRQ_EINT7)
|
||||
return S3C2410_GPF4 + (irq - IRQ_EINT4);
|
||||
|
||||
if (irq >= IRQ_EINT8 && irq <= IRQ_EINT23)
|
||||
return S3C2410_GPG0 + (irq - IRQ_EINT8);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(s3c2410_gpio_irq2pin);
|
||||
|
|
|
@ -15,6 +15,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
|
@ -22,6 +23,7 @@
|
|||
#include <mach/gpio-core.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/irq.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include <mach/regs-gpio.h>
|
||||
|
||||
|
@ -77,9 +79,10 @@ static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
|
|||
|
||||
struct s3c_gpio_chip s3c24xx_gpios[] = {
|
||||
[0] = {
|
||||
.base = S3C24XX_GPIO_BASE(S3C2410_GPA0),
|
||||
.base = S3C2410_GPACON,
|
||||
.pm = __gpio_pm(&s3c_gpio_pm_1bit),
|
||||
.chip = {
|
||||
.base = S3C2410_GPA0,
|
||||
.base = S3C2410_GPA(0),
|
||||
.owner = THIS_MODULE,
|
||||
.label = "GPIOA",
|
||||
.ngpio = 24,
|
||||
|
@ -88,45 +91,50 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
|
|||
},
|
||||
},
|
||||
[1] = {
|
||||
.base = S3C24XX_GPIO_BASE(S3C2410_GPB0),
|
||||
.base = S3C2410_GPBCON,
|
||||
.pm = __gpio_pm(&s3c_gpio_pm_2bit),
|
||||
.chip = {
|
||||
.base = S3C2410_GPB0,
|
||||
.base = S3C2410_GPB(0),
|
||||
.owner = THIS_MODULE,
|
||||
.label = "GPIOB",
|
||||
.ngpio = 16,
|
||||
},
|
||||
},
|
||||
[2] = {
|
||||
.base = S3C24XX_GPIO_BASE(S3C2410_GPC0),
|
||||
.base = S3C2410_GPCCON,
|
||||
.pm = __gpio_pm(&s3c_gpio_pm_2bit),
|
||||
.chip = {
|
||||
.base = S3C2410_GPC0,
|
||||
.base = S3C2410_GPC(0),
|
||||
.owner = THIS_MODULE,
|
||||
.label = "GPIOC",
|
||||
.ngpio = 16,
|
||||
},
|
||||
},
|
||||
[3] = {
|
||||
.base = S3C24XX_GPIO_BASE(S3C2410_GPD0),
|
||||
.base = S3C2410_GPDCON,
|
||||
.pm = __gpio_pm(&s3c_gpio_pm_2bit),
|
||||
.chip = {
|
||||
.base = S3C2410_GPD0,
|
||||
.base = S3C2410_GPD(0),
|
||||
.owner = THIS_MODULE,
|
||||
.label = "GPIOD",
|
||||
.ngpio = 16,
|
||||
},
|
||||
},
|
||||
[4] = {
|
||||
.base = S3C24XX_GPIO_BASE(S3C2410_GPE0),
|
||||
.base = S3C2410_GPECON,
|
||||
.pm = __gpio_pm(&s3c_gpio_pm_2bit),
|
||||
.chip = {
|
||||
.base = S3C2410_GPE0,
|
||||
.base = S3C2410_GPE(0),
|
||||
.label = "GPIOE",
|
||||
.owner = THIS_MODULE,
|
||||
.ngpio = 16,
|
||||
},
|
||||
},
|
||||
[5] = {
|
||||
.base = S3C24XX_GPIO_BASE(S3C2410_GPF0),
|
||||
.base = S3C2410_GPFCON,
|
||||
.pm = __gpio_pm(&s3c_gpio_pm_2bit),
|
||||
.chip = {
|
||||
.base = S3C2410_GPF0,
|
||||
.base = S3C2410_GPF(0),
|
||||
.owner = THIS_MODULE,
|
||||
.label = "GPIOF",
|
||||
.ngpio = 8,
|
||||
|
@ -134,14 +142,24 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
|
|||
},
|
||||
},
|
||||
[6] = {
|
||||
.base = S3C24XX_GPIO_BASE(S3C2410_GPG0),
|
||||
.base = S3C2410_GPGCON,
|
||||
.pm = __gpio_pm(&s3c_gpio_pm_2bit),
|
||||
.chip = {
|
||||
.base = S3C2410_GPG0,
|
||||
.base = S3C2410_GPG(0),
|
||||
.owner = THIS_MODULE,
|
||||
.label = "GPIOG",
|
||||
.ngpio = 10,
|
||||
.ngpio = 16,
|
||||
.to_irq = s3c24xx_gpiolib_bankg_toirq,
|
||||
},
|
||||
}, {
|
||||
.base = S3C2410_GPHCON,
|
||||
.pm = __gpio_pm(&s3c_gpio_pm_2bit),
|
||||
.chip = {
|
||||
.base = S3C2410_GPH(0),
|
||||
.owner = THIS_MODULE,
|
||||
.label = "GPIOH",
|
||||
.ngpio = 11,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -156,4 +174,4 @@ static __init int s3c24xx_gpiolib_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(s3c24xx_gpiolib_init);
|
||||
core_initcall(s3c24xx_gpiolib_init);
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
/* linux/include/asm-arm/plat-s3c24xx/dma.h
|
||||
/* linux/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
|
||||
*
|
||||
* Copyright (C) 2006 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
|
@ -10,8 +10,10 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <plat/dma-core.h>
|
||||
|
||||
extern struct sysdev_class dma_sysclass;
|
||||
extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
|
||||
extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
|
||||
|
||||
#define DMA_CH_VALID (1<<31)
|
||||
#define DMA_CH_NEVER (1<<30)
|
||||
|
@ -31,8 +33,8 @@ struct s3c24xx_dma_map {
|
|||
const char *name;
|
||||
struct s3c24xx_dma_addr hw_addr;
|
||||
|
||||
unsigned long channels[S3C2410_DMA_CHANNELS];
|
||||
unsigned long channels_rx[S3C2410_DMA_CHANNELS];
|
||||
unsigned long channels[S3C_DMA_CHANNELS];
|
||||
unsigned long channels_rx[S3C_DMA_CHANNELS];
|
||||
};
|
||||
|
||||
struct s3c24xx_dma_selection {
|
||||
|
@ -58,7 +60,7 @@ extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
|
|||
*/
|
||||
|
||||
struct s3c24xx_dma_order_ch {
|
||||
unsigned int list[S3C2410_DMA_CHANNELS]; /* list of channels */
|
||||
unsigned int list[S3C_DMA_CHANNELS]; /* list of channels */
|
||||
unsigned int flags; /* flags */
|
||||
};
|
||||
|
|
@ -58,7 +58,6 @@
|
|||
#define S3C24XX_SZ_SPI SZ_1M
|
||||
#define S3C24XX_SZ_SDI SZ_1M
|
||||
#define S3C24XX_SZ_NAND SZ_1M
|
||||
#define S3C24XX_SZ_USBHOST SZ_1M
|
||||
|
||||
/* GPIO ports */
|
||||
|
||||
|
|
|
@ -57,3 +57,8 @@ static inline void s3c_pm_arch_show_resume_irqs(void)
|
|||
s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
|
||||
s3c_irqwake_eintmask);
|
||||
}
|
||||
|
||||
static inline void s3c_pm_arch_update_uart(void __iomem *regs,
|
||||
struct pm_uart_save *save)
|
||||
{
|
||||
}
|
||||
|
|
145
arch/arm/plat-s3c24xx/include/plat/regs-dma.h
Normal file
145
arch/arm/plat-s3c24xx/include/plat/regs-dma.h
Normal file
|
@ -0,0 +1,145 @@
|
|||
/* arch/arm/mach-s3c2410/include/mach/dma.h
|
||||
*
|
||||
* Copyright (C) 2003,2004,2006 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* Samsung S3C24XX DMA support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/* DMA Register definitions */
|
||||
|
||||
#define S3C2410_DMA_DISRC (0x00)
|
||||
#define S3C2410_DMA_DISRCC (0x04)
|
||||
#define S3C2410_DMA_DIDST (0x08)
|
||||
#define S3C2410_DMA_DIDSTC (0x0C)
|
||||
#define S3C2410_DMA_DCON (0x10)
|
||||
#define S3C2410_DMA_DSTAT (0x14)
|
||||
#define S3C2410_DMA_DCSRC (0x18)
|
||||
#define S3C2410_DMA_DCDST (0x1C)
|
||||
#define S3C2410_DMA_DMASKTRIG (0x20)
|
||||
#define S3C2412_DMA_DMAREQSEL (0x24)
|
||||
#define S3C2443_DMA_DMAREQSEL (0x24)
|
||||
|
||||
#define S3C2410_DISRCC_INC (1<<0)
|
||||
#define S3C2410_DISRCC_APB (1<<1)
|
||||
|
||||
#define S3C2410_DMASKTRIG_STOP (1<<2)
|
||||
#define S3C2410_DMASKTRIG_ON (1<<1)
|
||||
#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
|
||||
|
||||
#define S3C2410_DCON_DEMAND (0<<31)
|
||||
#define S3C2410_DCON_HANDSHAKE (1<<31)
|
||||
#define S3C2410_DCON_SYNC_PCLK (0<<30)
|
||||
#define S3C2410_DCON_SYNC_HCLK (1<<30)
|
||||
|
||||
#define S3C2410_DCON_INTREQ (1<<29)
|
||||
|
||||
#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
|
||||
#define S3C2410_DCON_CH0_UART0 (1<<24)
|
||||
#define S3C2410_DCON_CH0_SDI (2<<24)
|
||||
#define S3C2410_DCON_CH0_TIMER (3<<24)
|
||||
#define S3C2410_DCON_CH0_USBEP1 (4<<24)
|
||||
|
||||
#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
|
||||
#define S3C2410_DCON_CH1_UART1 (1<<24)
|
||||
#define S3C2410_DCON_CH1_I2SSDI (2<<24)
|
||||
#define S3C2410_DCON_CH1_SPI (3<<24)
|
||||
#define S3C2410_DCON_CH1_USBEP2 (4<<24)
|
||||
|
||||
#define S3C2410_DCON_CH2_I2SSDO (0<<24)
|
||||
#define S3C2410_DCON_CH2_I2SSDI (1<<24)
|
||||
#define S3C2410_DCON_CH2_SDI (2<<24)
|
||||
#define S3C2410_DCON_CH2_TIMER (3<<24)
|
||||
#define S3C2410_DCON_CH2_USBEP3 (4<<24)
|
||||
|
||||
#define S3C2410_DCON_CH3_UART2 (0<<24)
|
||||
#define S3C2410_DCON_CH3_SDI (1<<24)
|
||||
#define S3C2410_DCON_CH3_SPI (2<<24)
|
||||
#define S3C2410_DCON_CH3_TIMER (3<<24)
|
||||
#define S3C2410_DCON_CH3_USBEP4 (4<<24)
|
||||
|
||||
#define S3C2410_DCON_SRCSHIFT (24)
|
||||
#define S3C2410_DCON_SRCMASK (7<<24)
|
||||
|
||||
#define S3C2410_DCON_BYTE (0<<20)
|
||||
#define S3C2410_DCON_HALFWORD (1<<20)
|
||||
#define S3C2410_DCON_WORD (2<<20)
|
||||
|
||||
#define S3C2410_DCON_AUTORELOAD (0<<22)
|
||||
#define S3C2410_DCON_NORELOAD (1<<22)
|
||||
#define S3C2410_DCON_HWTRIG (1<<23)
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2440
|
||||
#define S3C2440_DIDSTC_CHKINT (1<<2)
|
||||
|
||||
#define S3C2440_DCON_CH0_I2SSDO (5<<24)
|
||||
#define S3C2440_DCON_CH0_PCMIN (6<<24)
|
||||
|
||||
#define S3C2440_DCON_CH1_PCMOUT (5<<24)
|
||||
#define S3C2440_DCON_CH1_SDI (6<<24)
|
||||
|
||||
#define S3C2440_DCON_CH2_PCMIN (5<<24)
|
||||
#define S3C2440_DCON_CH2_MICIN (6<<24)
|
||||
|
||||
#define S3C2440_DCON_CH3_MICIN (5<<24)
|
||||
#define S3C2440_DCON_CH3_PCMOUT (6<<24)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2412
|
||||
|
||||
#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
|
||||
|
||||
#define S3C2412_DMAREQSEL_HW (1)
|
||||
|
||||
#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
|
||||
#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
|
||||
#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
|
||||
#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
|
||||
#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
|
||||
#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
|
||||
#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
|
||||
#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
|
||||
#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
|
||||
#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
|
||||
#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
|
||||
#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
|
||||
#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
|
||||
#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
|
||||
#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
|
||||
#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
|
||||
#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
|
||||
#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
|
||||
#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
|
||||
#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
|
||||
|
||||
#endif
|
||||
|
||||
#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1)
|
||||
|
||||
#define S3C2443_DMAREQSEL_HW (1)
|
||||
|
||||
#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
|
||||
#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
|
||||
#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
|
||||
#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
|
||||
#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
|
||||
#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
|
||||
#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
|
||||
#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
|
||||
#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
|
||||
#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
|
||||
#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
|
||||
#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
|
||||
#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
|
||||
#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
|
||||
#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
|
||||
#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
|
||||
#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
|
||||
#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
|
||||
#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
|
||||
#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
|
||||
#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
|
|
@ -30,6 +30,7 @@
|
|||
#include <linux/suspend.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/time.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/io.h>
|
||||
|
@ -75,43 +76,10 @@ static struct sleep_save core_save[] = {
|
|||
SAVE_ITEM(S3C2410_CLKSLOW),
|
||||
};
|
||||
|
||||
static struct gpio_sleep {
|
||||
void __iomem *base;
|
||||
unsigned int gpcon;
|
||||
unsigned int gpdat;
|
||||
unsigned int gpup;
|
||||
} gpio_save[] = {
|
||||
[0] = {
|
||||
.base = S3C2410_GPACON,
|
||||
},
|
||||
[1] = {
|
||||
.base = S3C2410_GPBCON,
|
||||
},
|
||||
[2] = {
|
||||
.base = S3C2410_GPCCON,
|
||||
},
|
||||
[3] = {
|
||||
.base = S3C2410_GPDCON,
|
||||
},
|
||||
[4] = {
|
||||
.base = S3C2410_GPECON,
|
||||
},
|
||||
[5] = {
|
||||
.base = S3C2410_GPFCON,
|
||||
},
|
||||
[6] = {
|
||||
.base = S3C2410_GPGCON,
|
||||
},
|
||||
[7] = {
|
||||
.base = S3C2410_GPHCON,
|
||||
},
|
||||
};
|
||||
|
||||
static struct sleep_save misc_save[] = {
|
||||
SAVE_ITEM(S3C2410_DCLKCON),
|
||||
};
|
||||
|
||||
|
||||
/* s3c_pm_check_resume_pin
|
||||
*
|
||||
* check to see if the pin is configured correctly for sleep mode, and
|
||||
|
@ -156,195 +124,15 @@ void s3c_pm_configure_extint(void)
|
|||
* and then configure it as an input if it is not
|
||||
*/
|
||||
|
||||
for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
|
||||
s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
|
||||
for (pin = S3C2410_GPF(0); pin <= S3C2410_GPF(7); pin++) {
|
||||
s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF(0));
|
||||
}
|
||||
|
||||
for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
|
||||
s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
|
||||
for (pin = S3C2410_GPG(0); pin <= S3C2410_GPG(7); pin++) {
|
||||
s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG(0))+8);
|
||||
}
|
||||
}
|
||||
|
||||
/* offsets for CON/DAT/UP registers */
|
||||
|
||||
#define OFFS_CON (S3C2410_GPACON - S3C2410_GPACON)
|
||||
#define OFFS_DAT (S3C2410_GPADAT - S3C2410_GPACON)
|
||||
#define OFFS_UP (S3C2410_GPBUP - S3C2410_GPBCON)
|
||||
|
||||
/* s3c_pm_save_gpios()
|
||||
*
|
||||
* Save the state of the GPIOs
|
||||
*/
|
||||
|
||||
void s3c_pm_save_gpios(void)
|
||||
{
|
||||
struct gpio_sleep *gps = gpio_save;
|
||||
unsigned int gpio;
|
||||
|
||||
for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
|
||||
void __iomem *base = gps->base;
|
||||
|
||||
gps->gpcon = __raw_readl(base + OFFS_CON);
|
||||
gps->gpdat = __raw_readl(base + OFFS_DAT);
|
||||
|
||||
if (gpio > 0)
|
||||
gps->gpup = __raw_readl(base + OFFS_UP);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/* Test whether the given masked+shifted bits of an GPIO configuration
|
||||
* are one of the SFN (special function) modes. */
|
||||
|
||||
static inline int is_sfn(unsigned long con)
|
||||
{
|
||||
return (con == 2 || con == 3);
|
||||
}
|
||||
|
||||
/* Test if the given masked+shifted GPIO configuration is an input */
|
||||
|
||||
static inline int is_in(unsigned long con)
|
||||
{
|
||||
return con == 0;
|
||||
}
|
||||
|
||||
/* Test if the given masked+shifted GPIO configuration is an output */
|
||||
|
||||
static inline int is_out(unsigned long con)
|
||||
{
|
||||
return con == 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* s3c2410_pm_restore_gpio() - restore the given GPIO bank
|
||||
* @index: The number of the GPIO bank being resumed.
|
||||
* @gps: The sleep confgiuration for the bank.
|
||||
*
|
||||
* Restore one of the GPIO banks that was saved during suspend. This is
|
||||
* not as simple as once thought, due to the possibility of glitches
|
||||
* from the order that the CON and DAT registers are set in.
|
||||
*
|
||||
* The three states the pin can be are {IN,OUT,SFN} which gives us 9
|
||||
* combinations of changes to check. Three of these, if the pin stays
|
||||
* in the same configuration can be discounted. This leaves us with
|
||||
* the following:
|
||||
*
|
||||
* { IN => OUT } Change DAT first
|
||||
* { IN => SFN } Change CON first
|
||||
* { OUT => SFN } Change CON first, so new data will not glitch
|
||||
* { OUT => IN } Change CON first, so new data will not glitch
|
||||
* { SFN => IN } Change CON first
|
||||
* { SFN => OUT } Change DAT first, so new data will not glitch [1]
|
||||
*
|
||||
* We do not currently deal with the UP registers as these control
|
||||
* weak resistors, so a small delay in change should not need to bring
|
||||
* these into the calculations.
|
||||
*
|
||||
* [1] this assumes that writing to a pin DAT whilst in SFN will set the
|
||||
* state for when it is next output.
|
||||
*/
|
||||
|
||||
static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps)
|
||||
{
|
||||
void __iomem *base = gps->base;
|
||||
unsigned long gps_gpcon = gps->gpcon;
|
||||
unsigned long gps_gpdat = gps->gpdat;
|
||||
unsigned long old_gpcon;
|
||||
unsigned long old_gpdat;
|
||||
unsigned long old_gpup = 0x0;
|
||||
unsigned long gpcon;
|
||||
int nr;
|
||||
|
||||
old_gpcon = __raw_readl(base + OFFS_CON);
|
||||
old_gpdat = __raw_readl(base + OFFS_DAT);
|
||||
|
||||
if (base == S3C2410_GPACON) {
|
||||
/* GPACON only has one bit per control / data and no PULLUPs.
|
||||
* GPACON[x] = 0 => Output, 1 => SFN */
|
||||
|
||||
/* first set all SFN bits to SFN */
|
||||
|
||||
gpcon = old_gpcon | gps->gpcon;
|
||||
__raw_writel(gpcon, base + OFFS_CON);
|
||||
|
||||
/* now set all the other bits */
|
||||
|
||||
__raw_writel(gps_gpdat, base + OFFS_DAT);
|
||||
__raw_writel(gps_gpcon, base + OFFS_CON);
|
||||
} else {
|
||||
unsigned long old, new, mask;
|
||||
unsigned long change_mask = 0x0;
|
||||
|
||||
old_gpup = __raw_readl(base + OFFS_UP);
|
||||
|
||||
/* Create a change_mask of all the items that need to have
|
||||
* their CON value changed before their DAT value, so that
|
||||
* we minimise the work between the two settings.
|
||||
*/
|
||||
|
||||
for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
|
||||
old = (old_gpcon & mask) >> nr;
|
||||
new = (gps_gpcon & mask) >> nr;
|
||||
|
||||
/* If there is no change, then skip */
|
||||
|
||||
if (old == new)
|
||||
continue;
|
||||
|
||||
/* If both are special function, then skip */
|
||||
|
||||
if (is_sfn(old) && is_sfn(new))
|
||||
continue;
|
||||
|
||||
/* Change is IN => OUT, do not change now */
|
||||
|
||||
if (is_in(old) && is_out(new))
|
||||
continue;
|
||||
|
||||
/* Change is SFN => OUT, do not change now */
|
||||
|
||||
if (is_sfn(old) && is_out(new))
|
||||
continue;
|
||||
|
||||
/* We should now be at the case of IN=>SFN,
|
||||
* OUT=>SFN, OUT=>IN, SFN=>IN. */
|
||||
|
||||
change_mask |= mask;
|
||||
}
|
||||
|
||||
/* Write the new CON settings */
|
||||
|
||||
gpcon = old_gpcon & ~change_mask;
|
||||
gpcon |= gps_gpcon & change_mask;
|
||||
|
||||
__raw_writel(gpcon, base + OFFS_CON);
|
||||
|
||||
/* Now change any items that require DAT,CON */
|
||||
|
||||
__raw_writel(gps_gpdat, base + OFFS_DAT);
|
||||
__raw_writel(gps_gpcon, base + OFFS_CON);
|
||||
__raw_writel(gps->gpup, base + OFFS_UP);
|
||||
}
|
||||
|
||||
S3C_PMDBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n",
|
||||
index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
|
||||
}
|
||||
|
||||
|
||||
/** s3c2410_pm_restore_gpios()
|
||||
*
|
||||
* Restore the state of the GPIOs
|
||||
*/
|
||||
|
||||
void s3c_pm_restore_gpios(void)
|
||||
{
|
||||
struct gpio_sleep *gps = gpio_save;
|
||||
int gpio;
|
||||
|
||||
for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
|
||||
s3c2410_pm_restore_gpio(gpio, gps);
|
||||
}
|
||||
}
|
||||
|
||||
void s3c_pm_restore_core(void)
|
||||
{
|
||||
|
|
|
@ -11,6 +11,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
struct platform_device;
|
||||
|
||||
|
@ -20,6 +21,6 @@ struct platform_device;
|
|||
|
||||
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
|
||||
{
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPE15_IICSDA);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPE14_IICSCL);
|
||||
}
|
||||
|
|
|
@ -22,16 +22,16 @@ void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
|
|||
int enable)
|
||||
{
|
||||
if (enable) {
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPE13_SPICLK0);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE12, S3C2410_GPE12_SPIMOSI0);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPE11_SPIMISO0);
|
||||
s3c2410_gpio_pullup(S3C2410_GPE11, 0);
|
||||
s3c2410_gpio_pullup(S3C2410_GPE13, 0);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0);
|
||||
s3c2410_gpio_pullup(S3C2410_GPE(11), 0);
|
||||
s3c2410_gpio_pullup(S3C2410_GPE(13), 0);
|
||||
} else {
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPIO_INPUT);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPIO_INPUT);
|
||||
s3c2410_gpio_pullup(S3C2410_GPE11, 1);
|
||||
s3c2410_gpio_pullup(S3C2410_GPE12, 1);
|
||||
s3c2410_gpio_pullup(S3C2410_GPE13, 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT);
|
||||
s3c2410_gpio_pullup(S3C2410_GPE(11), 1);
|
||||
s3c2410_gpio_pullup(S3C2410_GPE(12), 1);
|
||||
s3c2410_gpio_pullup(S3C2410_GPE(13), 1);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -22,16 +22,16 @@ void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
|
|||
int enable)
|
||||
{
|
||||
if (enable) {
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPG7_SPICLK1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPG6, S3C2410_GPG6_SPIMOSI1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPG5_SPIMISO1);
|
||||
s3c2410_gpio_pullup(S3C2410_GPG5, 0);
|
||||
s3c2410_gpio_pullup(S3C2410_GPG6, 0);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1);
|
||||
s3c2410_gpio_pullup(S3C2410_GPG(5), 0);
|
||||
s3c2410_gpio_pullup(S3C2410_GPG(6), 0);
|
||||
} else {
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPIO_INPUT);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPIO_INPUT);
|
||||
s3c2410_gpio_pullup(S3C2410_GPG5, 1);
|
||||
s3c2410_gpio_pullup(S3C2410_GPG6, 1);
|
||||
s3c2410_gpio_pullup(S3C2410_GPG7, 1);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT);
|
||||
s3c2410_gpio_pullup(S3C2410_GPG(5), 1);
|
||||
s3c2410_gpio_pullup(S3C2410_GPG(6), 1);
|
||||
s3c2410_gpio_pullup(S3C2410_GPG(7), 1);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -19,6 +19,7 @@ config PLAT_S3C64XX
|
|||
select S3C_GPIO_PULL_UPDOWN
|
||||
select S3C_GPIO_CFG_S3C24XX
|
||||
select S3C_GPIO_CFG_S3C64XX
|
||||
select USB_ARCH_HAS_OHCI
|
||||
help
|
||||
Base platform code for any Samsung S3C64XX device
|
||||
|
||||
|
@ -38,6 +39,10 @@ config CPU_S3C6400_CLOCK
|
|||
Common clock support code for the S3C6400 that is shared
|
||||
by other CPUs in the series, such as the S3C6410.
|
||||
|
||||
config S3C64XX_DMA
|
||||
bool "S3C64XX DMA"
|
||||
select S3C_DMA
|
||||
|
||||
# platform specific device setup
|
||||
|
||||
config S3C64XX_SETUP_I2C0
|
||||
|
@ -59,4 +64,9 @@ config S3C64XX_SETUP_FB_24BPP
|
|||
help
|
||||
Common setup code for S3C64XX with an 24bpp RGB display helper.
|
||||
|
||||
config S3C64XX_SETUP_SDHCI_GPIO
|
||||
bool
|
||||
help
|
||||
Common setup code for S3C64XX SDHCI GPIO configurations
|
||||
|
||||
endif
|
||||
|
|
|
@ -24,8 +24,19 @@ obj-y += gpiolib.o
|
|||
obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o
|
||||
obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o
|
||||
|
||||
# PM support
|
||||
|
||||
obj-$(CONFIG_PM) += pm.o
|
||||
obj-$(CONFIG_PM) += sleep.o
|
||||
obj-$(CONFIG_PM) += irq-pm.o
|
||||
|
||||
# DMA support
|
||||
|
||||
obj-$(CONFIG_S3C64XX_DMA) += dma.o
|
||||
|
||||
# Device setup
|
||||
|
||||
obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
|
||||
obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
|
||||
obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
|
||||
obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
|
|
@ -27,6 +27,12 @@
|
|||
#include <plat/devs.h>
|
||||
#include <plat/clock.h>
|
||||
|
||||
struct clk clk_h2 = {
|
||||
.name = "hclk2",
|
||||
.id = -1,
|
||||
.rate = 0,
|
||||
};
|
||||
|
||||
struct clk clk_27m = {
|
||||
.name = "clk_27m",
|
||||
.id = -1,
|
||||
|
@ -152,6 +158,18 @@ static struct clk init_clocks_disable[] = {
|
|||
.parent = &clk_48m,
|
||||
.enable = s3c64xx_sclk_ctrl,
|
||||
.ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
|
||||
}, {
|
||||
.name = "dma0",
|
||||
.id = -1,
|
||||
.parent = &clk_h,
|
||||
.enable = s3c64xx_hclk_ctrl,
|
||||
.ctrlbit = S3C_CLKCON_HCLK_DMA0,
|
||||
}, {
|
||||
.name = "dma1",
|
||||
.id = -1,
|
||||
.parent = &clk_h,
|
||||
.enable = s3c64xx_hclk_ctrl,
|
||||
.ctrlbit = S3C_CLKCON_HCLK_DMA1,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -246,6 +264,7 @@ static struct clk *clks[] __initdata = {
|
|||
&clk_epll,
|
||||
&clk_27m,
|
||||
&clk_48m,
|
||||
&clk_h2,
|
||||
};
|
||||
|
||||
void __init s3c64xx_register_clocks(void)
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
|
@ -101,9 +102,24 @@ static struct map_desc s3c_iodesc[] __initdata = {
|
|||
.pfn = __phys_to_pfn(S3C64XX_PA_MODEM),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S3C_VA_WATCHDOG,
|
||||
.pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
struct sysdev_class s3c64xx_sysclass = {
|
||||
.name = "s3c64xx-core",
|
||||
};
|
||||
|
||||
static struct sys_device s3c64xx_sysdev = {
|
||||
.cls = &s3c64xx_sysclass,
|
||||
};
|
||||
|
||||
|
||||
/* read cpu identification code */
|
||||
|
||||
void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
|
||||
|
@ -115,5 +131,21 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
|
|||
iotable_init(mach_desc, size);
|
||||
|
||||
idcode = __raw_readl(S3C_VA_SYS + 0x118);
|
||||
if (!idcode) {
|
||||
/* S3C6400 has the ID register in a different place,
|
||||
* and needs a write before it can be read. */
|
||||
|
||||
__raw_writel(0x0, S3C_VA_SYS + 0xA1C);
|
||||
idcode = __raw_readl(S3C_VA_SYS + 0xA1C);
|
||||
}
|
||||
|
||||
s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
|
||||
}
|
||||
|
||||
static __init int s3c64xx_sysdev_init(void)
|
||||
{
|
||||
sysdev_class_register(&s3c64xx_sysclass);
|
||||
return sysdev_register(&s3c64xx_sysdev);
|
||||
}
|
||||
|
||||
core_initcall(s3c64xx_sysdev_init);
|
||||
|
|
722
arch/arm/plat-s3c64xx/dma.c
Normal file
722
arch/arm/plat-s3c64xx/dma.c
Normal file
|
@ -0,0 +1,722 @@
|
|||
/* linux/arch/arm/plat-s3c64xx/dma.c
|
||||
*
|
||||
* Copyright 2009 Openmoko, Inc.
|
||||
* Copyright 2009 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* S3C64XX DMA core
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/dmapool.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <mach/dma.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include <plat/dma-plat.h>
|
||||
#include <plat/regs-sys.h>
|
||||
|
||||
#include <asm/hardware/pl080.h>
|
||||
|
||||
/* dma channel state information */
|
||||
|
||||
struct s3c64xx_dmac {
|
||||
struct sys_device sysdev;
|
||||
struct clk *clk;
|
||||
void __iomem *regs;
|
||||
struct s3c2410_dma_chan *channels;
|
||||
enum dma_ch chanbase;
|
||||
};
|
||||
|
||||
/* pool to provide LLI buffers */
|
||||
static struct dma_pool *dma_pool;
|
||||
|
||||
/* Debug configuration and code */
|
||||
|
||||
static unsigned char debug_show_buffs = 0;
|
||||
|
||||
static void dbg_showchan(struct s3c2410_dma_chan *chan)
|
||||
{
|
||||
pr_debug("DMA%d: %08x->%08x L %08x C %08x,%08x S %08x\n",
|
||||
chan->number,
|
||||
readl(chan->regs + PL080_CH_SRC_ADDR),
|
||||
readl(chan->regs + PL080_CH_DST_ADDR),
|
||||
readl(chan->regs + PL080_CH_LLI),
|
||||
readl(chan->regs + PL080_CH_CONTROL),
|
||||
readl(chan->regs + PL080S_CH_CONTROL2),
|
||||
readl(chan->regs + PL080S_CH_CONFIG));
|
||||
}
|
||||
|
||||
static void show_lli(struct pl080s_lli *lli)
|
||||
{
|
||||
pr_debug("LLI[%p] %08x->%08x, NL %08x C %08x,%08x\n",
|
||||
lli, lli->src_addr, lli->dst_addr, lli->next_lli,
|
||||
lli->control0, lli->control1);
|
||||
}
|
||||
|
||||
static void dbg_showbuffs(struct s3c2410_dma_chan *chan)
|
||||
{
|
||||
struct s3c64xx_dma_buff *ptr;
|
||||
struct s3c64xx_dma_buff *end;
|
||||
|
||||
pr_debug("DMA%d: buffs next %p, curr %p, end %p\n",
|
||||
chan->number, chan->next, chan->curr, chan->end);
|
||||
|
||||
ptr = chan->next;
|
||||
end = chan->end;
|
||||
|
||||
if (debug_show_buffs) {
|
||||
for (; ptr != NULL; ptr = ptr->next) {
|
||||
pr_debug("DMA%d: %08x ",
|
||||
chan->number, ptr->lli_dma);
|
||||
show_lli(ptr->lli);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* End of Debug */
|
||||
|
||||
static struct s3c2410_dma_chan *s3c64xx_dma_map_channel(unsigned int channel)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan;
|
||||
unsigned int start, offs;
|
||||
|
||||
start = 0;
|
||||
|
||||
if (channel >= DMACH_PCM1_TX)
|
||||
start = 8;
|
||||
|
||||
for (offs = 0; offs < 8; offs++) {
|
||||
chan = &s3c2410_chans[start + offs];
|
||||
if (!chan->in_use)
|
||||
goto found;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
|
||||
found:
|
||||
s3c_dma_chan_map[channel] = chan;
|
||||
return chan;
|
||||
}
|
||||
|
||||
int s3c2410_dma_config(unsigned int channel, int xferunit)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
|
||||
if (chan == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
switch (xferunit) {
|
||||
case 1:
|
||||
chan->hw_width = 0;
|
||||
break;
|
||||
case 2:
|
||||
chan->hw_width = 1;
|
||||
break;
|
||||
case 4:
|
||||
chan->hw_width = 2;
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "%s: illegal width %d\n", __func__, xferunit);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(s3c2410_dma_config);
|
||||
|
||||
static void s3c64xx_dma_fill_lli(struct s3c2410_dma_chan *chan,
|
||||
struct pl080s_lli *lli,
|
||||
dma_addr_t data, int size)
|
||||
{
|
||||
dma_addr_t src, dst;
|
||||
u32 control0, control1;
|
||||
|
||||
switch (chan->source) {
|
||||
case S3C2410_DMASRC_HW:
|
||||
src = chan->dev_addr;
|
||||
dst = data;
|
||||
control0 = PL080_CONTROL_SRC_AHB2;
|
||||
control0 |= (u32)chan->hw_width << PL080_CONTROL_SWIDTH_SHIFT;
|
||||
control0 |= 2 << PL080_CONTROL_DWIDTH_SHIFT;
|
||||
control0 |= PL080_CONTROL_DST_INCR;
|
||||
break;
|
||||
|
||||
case S3C2410_DMASRC_MEM:
|
||||
src = data;
|
||||
dst = chan->dev_addr;
|
||||
control0 = PL080_CONTROL_DST_AHB2;
|
||||
control0 |= (u32)chan->hw_width << PL080_CONTROL_DWIDTH_SHIFT;
|
||||
control0 |= 2 << PL080_CONTROL_SWIDTH_SHIFT;
|
||||
control0 |= PL080_CONTROL_SRC_INCR;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
|
||||
/* note, we do not currently setup any of the burst controls */
|
||||
|
||||
control1 = size >> chan->hw_width; /* size in no of xfers */
|
||||
control0 |= PL080_CONTROL_PROT_SYS; /* always in priv. mode */
|
||||
control0 |= PL080_CONTROL_TC_IRQ_EN; /* always fire IRQ */
|
||||
|
||||
lli->src_addr = src;
|
||||
lli->dst_addr = dst;
|
||||
lli->next_lli = 0;
|
||||
lli->control0 = control0;
|
||||
lli->control1 = control1;
|
||||
}
|
||||
|
||||
static void s3c64xx_lli_to_regs(struct s3c2410_dma_chan *chan,
|
||||
struct pl080s_lli *lli)
|
||||
{
|
||||
void __iomem *regs = chan->regs;
|
||||
|
||||
pr_debug("%s: LLI %p => regs\n", __func__, lli);
|
||||
show_lli(lli);
|
||||
|
||||
writel(lli->src_addr, regs + PL080_CH_SRC_ADDR);
|
||||
writel(lli->dst_addr, regs + PL080_CH_DST_ADDR);
|
||||
writel(lli->next_lli, regs + PL080_CH_LLI);
|
||||
writel(lli->control0, regs + PL080_CH_CONTROL);
|
||||
writel(lli->control1, regs + PL080S_CH_CONTROL2);
|
||||
}
|
||||
|
||||
static int s3c64xx_dma_start(struct s3c2410_dma_chan *chan)
|
||||
{
|
||||
struct s3c64xx_dmac *dmac = chan->dmac;
|
||||
u32 config;
|
||||
u32 bit = chan->bit;
|
||||
|
||||
dbg_showchan(chan);
|
||||
|
||||
pr_debug("%s: clearing interrupts\n", __func__);
|
||||
|
||||
/* clear interrupts */
|
||||
writel(bit, dmac->regs + PL080_TC_CLEAR);
|
||||
writel(bit, dmac->regs + PL080_ERR_CLEAR);
|
||||
|
||||
pr_debug("%s: starting channel\n", __func__);
|
||||
|
||||
config = readl(chan->regs + PL080S_CH_CONFIG);
|
||||
config |= PL080_CONFIG_ENABLE;
|
||||
|
||||
pr_debug("%s: writing config %08x\n", __func__, config);
|
||||
writel(config, chan->regs + PL080S_CH_CONFIG);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int s3c64xx_dma_stop(struct s3c2410_dma_chan *chan)
|
||||
{
|
||||
u32 config;
|
||||
int timeout;
|
||||
|
||||
pr_debug("%s: stopping channel\n", __func__);
|
||||
|
||||
dbg_showchan(chan);
|
||||
|
||||
config = readl(chan->regs + PL080S_CH_CONFIG);
|
||||
config |= PL080_CONFIG_HALT;
|
||||
writel(config, chan->regs + PL080S_CH_CONFIG);
|
||||
|
||||
timeout = 1000;
|
||||
do {
|
||||
config = readl(chan->regs + PL080S_CH_CONFIG);
|
||||
pr_debug("%s: %d - config %08x\n", __func__, timeout, config);
|
||||
if (config & PL080_CONFIG_ACTIVE)
|
||||
udelay(10);
|
||||
else
|
||||
break;
|
||||
} while (--timeout > 0);
|
||||
|
||||
if (config & PL080_CONFIG_ACTIVE) {
|
||||
printk(KERN_ERR "%s: channel still active\n", __func__);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
config = readl(chan->regs + PL080S_CH_CONFIG);
|
||||
config &= ~PL080_CONFIG_ENABLE;
|
||||
writel(config, chan->regs + PL080S_CH_CONFIG);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void s3c64xx_dma_bufffdone(struct s3c2410_dma_chan *chan,
|
||||
struct s3c64xx_dma_buff *buf,
|
||||
enum s3c2410_dma_buffresult result)
|
||||
{
|
||||
if (chan->callback_fn != NULL)
|
||||
(chan->callback_fn)(chan, buf->pw, 0, result);
|
||||
}
|
||||
|
||||
static void s3c64xx_dma_freebuff(struct s3c64xx_dma_buff *buff)
|
||||
{
|
||||
dma_pool_free(dma_pool, buff->lli, buff->lli_dma);
|
||||
kfree(buff);
|
||||
}
|
||||
|
||||
static int s3c64xx_dma_flush(struct s3c2410_dma_chan *chan)
|
||||
{
|
||||
struct s3c64xx_dma_buff *buff, *next;
|
||||
u32 config;
|
||||
|
||||
dbg_showchan(chan);
|
||||
|
||||
pr_debug("%s: flushing channel\n", __func__);
|
||||
|
||||
config = readl(chan->regs + PL080S_CH_CONFIG);
|
||||
config &= ~PL080_CONFIG_ENABLE;
|
||||
writel(config, chan->regs + PL080S_CH_CONFIG);
|
||||
|
||||
/* dump all the buffers associated with this channel */
|
||||
|
||||
for (buff = chan->curr; buff != NULL; buff = next) {
|
||||
next = buff->next;
|
||||
pr_debug("%s: buff %p (next %p)\n", __func__, buff, buff->next);
|
||||
|
||||
s3c64xx_dma_bufffdone(chan, buff, S3C2410_RES_ABORT);
|
||||
s3c64xx_dma_freebuff(buff);
|
||||
}
|
||||
|
||||
chan->curr = chan->next = chan->end = NULL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
|
||||
WARN_ON(!chan);
|
||||
if (!chan)
|
||||
return -EINVAL;
|
||||
|
||||
switch (op) {
|
||||
case S3C2410_DMAOP_START:
|
||||
return s3c64xx_dma_start(chan);
|
||||
|
||||
case S3C2410_DMAOP_STOP:
|
||||
return s3c64xx_dma_stop(chan);
|
||||
|
||||
case S3C2410_DMAOP_FLUSH:
|
||||
return s3c64xx_dma_flush(chan);
|
||||
|
||||
/* belive PAUSE/RESUME are no-ops */
|
||||
case S3C2410_DMAOP_PAUSE:
|
||||
case S3C2410_DMAOP_RESUME:
|
||||
case S3C2410_DMAOP_STARTED:
|
||||
case S3C2410_DMAOP_TIMEOUT:
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -ENOENT;
|
||||
}
|
||||
EXPORT_SYMBOL(s3c2410_dma_ctrl);
|
||||
|
||||
/* s3c2410_dma_enque
|
||||
*
|
||||
*/
|
||||
|
||||
int s3c2410_dma_enqueue(unsigned int channel, void *id,
|
||||
dma_addr_t data, int size)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
struct s3c64xx_dma_buff *next;
|
||||
struct s3c64xx_dma_buff *buff;
|
||||
struct pl080s_lli *lli;
|
||||
int ret;
|
||||
|
||||
WARN_ON(!chan);
|
||||
if (!chan)
|
||||
return -EINVAL;
|
||||
|
||||
buff = kzalloc(sizeof(struct s3c64xx_dma_buff), GFP_KERNEL);
|
||||
if (!buff) {
|
||||
printk(KERN_ERR "%s: no memory for buffer\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
lli = dma_pool_alloc(dma_pool, GFP_KERNEL, &buff->lli_dma);
|
||||
if (!lli) {
|
||||
printk(KERN_ERR "%s: no memory for lli\n", __func__);
|
||||
ret = -ENOMEM;
|
||||
goto err_buff;
|
||||
}
|
||||
|
||||
pr_debug("%s: buff %p, dp %08x lli (%p, %08x) %d\n",
|
||||
__func__, buff, data, lli, (u32)buff->lli_dma, size);
|
||||
|
||||
buff->lli = lli;
|
||||
buff->pw = id;
|
||||
|
||||
s3c64xx_dma_fill_lli(chan, lli, data, size);
|
||||
|
||||
if ((next = chan->next) != NULL) {
|
||||
struct s3c64xx_dma_buff *end = chan->end;
|
||||
struct pl080s_lli *endlli = end->lli;
|
||||
|
||||
pr_debug("enquing onto channel\n");
|
||||
|
||||
end->next = buff;
|
||||
endlli->next_lli = buff->lli_dma;
|
||||
|
||||
if (chan->flags & S3C2410_DMAF_CIRCULAR) {
|
||||
struct s3c64xx_dma_buff *curr = chan->curr;
|
||||
lli->next_lli = curr->lli_dma;
|
||||
}
|
||||
|
||||
if (next == chan->curr) {
|
||||
writel(buff->lli_dma, chan->regs + PL080_CH_LLI);
|
||||
chan->next = buff;
|
||||
}
|
||||
|
||||
show_lli(endlli);
|
||||
chan->end = buff;
|
||||
} else {
|
||||
pr_debug("enquing onto empty channel\n");
|
||||
|
||||
chan->curr = buff;
|
||||
chan->next = buff;
|
||||
chan->end = buff;
|
||||
|
||||
s3c64xx_lli_to_regs(chan, lli);
|
||||
}
|
||||
|
||||
show_lli(lli);
|
||||
|
||||
dbg_showchan(chan);
|
||||
dbg_showbuffs(chan);
|
||||
return 0;
|
||||
|
||||
err_buff:
|
||||
kfree(buff);
|
||||
return ret;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(s3c2410_dma_enqueue);
|
||||
|
||||
|
||||
int s3c2410_dma_devconfig(int channel,
|
||||
enum s3c2410_dmasrc source,
|
||||
unsigned long devaddr)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
u32 peripheral;
|
||||
u32 config = 0;
|
||||
|
||||
pr_debug("%s: channel %d, source %d, dev %08lx, chan %p\n",
|
||||
__func__, channel, source, devaddr, chan);
|
||||
|
||||
WARN_ON(!chan);
|
||||
if (!chan)
|
||||
return -EINVAL;
|
||||
|
||||
peripheral = (chan->peripheral & 0xf);
|
||||
chan->source = source;
|
||||
chan->dev_addr = devaddr;
|
||||
|
||||
pr_debug("%s: peripheral %d\n", __func__, peripheral);
|
||||
|
||||
switch (source) {
|
||||
case S3C2410_DMASRC_HW:
|
||||
config = 2 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
|
||||
config |= peripheral << PL080_CONFIG_SRC_SEL_SHIFT;
|
||||
break;
|
||||
case S3C2410_DMASRC_MEM:
|
||||
config = 1 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
|
||||
config |= peripheral << PL080_CONFIG_DST_SEL_SHIFT;
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "%s: bad source\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* allow TC and ERR interrupts */
|
||||
config |= PL080_CONFIG_TC_IRQ_MASK;
|
||||
config |= PL080_CONFIG_ERR_IRQ_MASK;
|
||||
|
||||
pr_debug("%s: config %08x\n", __func__, config);
|
||||
|
||||
writel(config, chan->regs + PL080S_CH_CONFIG);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(s3c2410_dma_devconfig);
|
||||
|
||||
|
||||
int s3c2410_dma_getposition(unsigned int channel,
|
||||
dma_addr_t *src, dma_addr_t *dst)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
|
||||
WARN_ON(!chan);
|
||||
if (!chan)
|
||||
return -EINVAL;
|
||||
|
||||
if (src != NULL)
|
||||
*src = readl(chan->regs + PL080_CH_SRC_ADDR);
|
||||
|
||||
if (dst != NULL)
|
||||
*dst = readl(chan->regs + PL080_CH_DST_ADDR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(s3c2410_dma_getposition);
|
||||
|
||||
/* s3c2410_request_dma
|
||||
*
|
||||
* get control of an dma channel
|
||||
*/
|
||||
|
||||
int s3c2410_dma_request(unsigned int channel,
|
||||
struct s3c2410_dma_client *client,
|
||||
void *dev)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan;
|
||||
unsigned long flags;
|
||||
|
||||
pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
|
||||
channel, client->name, dev);
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
chan = s3c64xx_dma_map_channel(channel);
|
||||
if (chan == NULL) {
|
||||
local_irq_restore(flags);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
dbg_showchan(chan);
|
||||
|
||||
chan->client = client;
|
||||
chan->in_use = 1;
|
||||
chan->peripheral = channel;
|
||||
|
||||
local_irq_restore(flags);
|
||||
|
||||
/* need to setup */
|
||||
|
||||
pr_debug("%s: channel initialised, %p\n", __func__, chan);
|
||||
|
||||
return chan->number | DMACH_LOW_LEVEL;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(s3c2410_dma_request);
|
||||
|
||||
/* s3c2410_dma_free
|
||||
*
|
||||
* release the given channel back to the system, will stop and flush
|
||||
* any outstanding transfers, and ensure the channel is ready for the
|
||||
* next claimant.
|
||||
*
|
||||
* Note, although a warning is currently printed if the freeing client
|
||||
* info is not the same as the registrant's client info, the free is still
|
||||
* allowed to go through.
|
||||
*/
|
||||
|
||||
int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
unsigned long flags;
|
||||
|
||||
if (chan == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
if (chan->client != client) {
|
||||
printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
|
||||
channel, chan->client, client);
|
||||
}
|
||||
|
||||
/* sort out stopping and freeing the channel */
|
||||
|
||||
|
||||
chan->client = NULL;
|
||||
chan->in_use = 0;
|
||||
|
||||
if (!(channel & DMACH_LOW_LEVEL))
|
||||
s3c_dma_chan_map[channel] = NULL;
|
||||
|
||||
local_irq_restore(flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(s3c2410_dma_free);
|
||||
|
||||
|
||||
static void s3c64xx_dma_tcirq(struct s3c64xx_dmac *dmac, int offs)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = dmac->channels + offs;
|
||||
|
||||
/* note, we currently do not bother to work out which buffer
|
||||
* or buffers have been completed since the last tc-irq. */
|
||||
|
||||
if (chan->callback_fn)
|
||||
(chan->callback_fn)(chan, chan->curr->pw, 0, S3C2410_RES_OK);
|
||||
}
|
||||
|
||||
static void s3c64xx_dma_errirq(struct s3c64xx_dmac *dmac, int offs)
|
||||
{
|
||||
printk(KERN_DEBUG "%s: offs %d\n", __func__, offs);
|
||||
}
|
||||
|
||||
static irqreturn_t s3c64xx_dma_irq(int irq, void *pw)
|
||||
{
|
||||
struct s3c64xx_dmac *dmac = pw;
|
||||
u32 tcstat, errstat;
|
||||
u32 bit;
|
||||
int offs;
|
||||
|
||||
tcstat = readl(dmac->regs + PL080_TC_STATUS);
|
||||
errstat = readl(dmac->regs + PL080_ERR_STATUS);
|
||||
|
||||
for (offs = 0, bit = 1; offs < 8; offs++, bit <<= 1) {
|
||||
if (tcstat & bit) {
|
||||
writel(bit, dmac->regs + PL080_TC_CLEAR);
|
||||
s3c64xx_dma_tcirq(dmac, offs);
|
||||
}
|
||||
|
||||
if (errstat & bit) {
|
||||
s3c64xx_dma_errirq(dmac, offs);
|
||||
writel(bit, dmac->regs + PL080_ERR_CLEAR);
|
||||
}
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct sysdev_class dma_sysclass = {
|
||||
.name = "s3c64xx-dma",
|
||||
};
|
||||
|
||||
static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
|
||||
int irq, unsigned int base)
|
||||
{
|
||||
struct s3c2410_dma_chan *chptr = &s3c2410_chans[chno];
|
||||
struct s3c64xx_dmac *dmac;
|
||||
char clkname[16];
|
||||
void __iomem *regs;
|
||||
void __iomem *regptr;
|
||||
int err, ch;
|
||||
|
||||
dmac = kzalloc(sizeof(struct s3c64xx_dmac), GFP_KERNEL);
|
||||
if (!dmac) {
|
||||
printk(KERN_ERR "%s: failed to alloc mem\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dmac->sysdev.id = chno / 8;
|
||||
dmac->sysdev.cls = &dma_sysclass;
|
||||
|
||||
err = sysdev_register(&dmac->sysdev);
|
||||
if (err) {
|
||||
printk(KERN_ERR "%s: failed to register sysdevice\n", __func__);
|
||||
goto err_alloc;
|
||||
}
|
||||
|
||||
regs = ioremap(base, 0x200);
|
||||
if (!regs) {
|
||||
printk(KERN_ERR "%s: failed to ioremap()\n", __func__);
|
||||
err = -ENXIO;
|
||||
goto err_dev;
|
||||
}
|
||||
|
||||
snprintf(clkname, sizeof(clkname), "dma%d", dmac->sysdev.id);
|
||||
|
||||
dmac->clk = clk_get(NULL, clkname);
|
||||
if (IS_ERR(dmac->clk)) {
|
||||
printk(KERN_ERR "%s: failed to get clock %s\n", __func__, clkname);
|
||||
err = PTR_ERR(dmac->clk);
|
||||
goto err_map;
|
||||
}
|
||||
|
||||
clk_enable(dmac->clk);
|
||||
|
||||
dmac->regs = regs;
|
||||
dmac->chanbase = chbase;
|
||||
dmac->channels = chptr;
|
||||
|
||||
err = request_irq(irq, s3c64xx_dma_irq, 0, "DMA", dmac);
|
||||
if (err < 0) {
|
||||
printk(KERN_ERR "%s: failed to get irq\n", __func__);
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
regptr = regs + PL080_Cx_BASE(0);
|
||||
|
||||
for (ch = 0; ch < 8; ch++, chno++, chptr++) {
|
||||
printk(KERN_INFO "%s: registering DMA %d (%p)\n",
|
||||
__func__, chno, regptr);
|
||||
|
||||
chptr->bit = 1 << ch;
|
||||
chptr->number = chno;
|
||||
chptr->dmac = dmac;
|
||||
chptr->regs = regptr;
|
||||
regptr += PL008_Cx_STRIDE;
|
||||
}
|
||||
|
||||
/* for the moment, permanently enable the controller */
|
||||
writel(PL080_CONFIG_ENABLE, regs + PL080_CONFIG);
|
||||
|
||||
printk(KERN_INFO "PL080: IRQ %d, at %p\n", irq, regs);
|
||||
|
||||
return 0;
|
||||
|
||||
err_clk:
|
||||
clk_disable(dmac->clk);
|
||||
clk_put(dmac->clk);
|
||||
err_map:
|
||||
iounmap(regs);
|
||||
err_dev:
|
||||
sysdev_unregister(&dmac->sysdev);
|
||||
err_alloc:
|
||||
kfree(dmac);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int __init s3c64xx_dma_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
printk(KERN_INFO "%s: Registering DMA channels\n", __func__);
|
||||
|
||||
dma_pool = dma_pool_create("DMA-LLI", NULL, 32, 16, 0);
|
||||
if (!dma_pool) {
|
||||
printk(KERN_ERR "%s: failed to create pool\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ret = sysdev_class_register(&dma_sysclass);
|
||||
if (ret) {
|
||||
printk(KERN_ERR "%s: failed to create sysclass\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* Set all DMA configuration to be DMA, not SDMA */
|
||||
writel(0xffffff, S3C_SYSREG(0x110));
|
||||
|
||||
/* Register standard DMA controlers */
|
||||
s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000);
|
||||
s3c64xx_dma_init1(8, DMACH_PCM1_TX, IRQ_DMA1, 0x75100000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(s3c64xx_dma_init);
|
|
@ -385,12 +385,19 @@ static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip)
|
|||
{
|
||||
chip->chip.direction_input = s3c64xx_gpiolib_4bit_input;
|
||||
chip->chip.direction_output = s3c64xx_gpiolib_4bit_output;
|
||||
chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
|
||||
}
|
||||
|
||||
static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
|
||||
{
|
||||
chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input;
|
||||
chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output;
|
||||
chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
|
||||
}
|
||||
|
||||
static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
|
||||
{
|
||||
chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
|
||||
}
|
||||
|
||||
static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
|
||||
|
@ -412,7 +419,8 @@ static __init int s3c64xx_gpiolib_init(void)
|
|||
s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
|
||||
s3c64xx_gpiolib_add_4bit2);
|
||||
|
||||
s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), NULL);
|
||||
s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
|
||||
s3c64xx_gpiolib_add_2bit);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
70
arch/arm/plat-s3c64xx/include/plat/dma-plat.h
Normal file
70
arch/arm/plat-s3c64xx/include/plat/dma-plat.h
Normal file
|
@ -0,0 +1,70 @@
|
|||
/* linux/arch/arm/plat-s3c64xx/include/plat/dma-plat.h
|
||||
*
|
||||
* Copyright 2009 Openmoko, Inc.
|
||||
* Copyright 2009 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* S3C64XX DMA core
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
|
||||
|
||||
struct s3c64xx_dma_buff;
|
||||
|
||||
/** s3c64xx_dma_buff - S3C64XX DMA buffer descriptor
|
||||
* @next: Pointer to next buffer in queue or ring.
|
||||
* @pw: Client provided identifier
|
||||
* @lli: Pointer to hardware descriptor this buffer is associated with.
|
||||
* @lli_dma: Hardare address of the descriptor.
|
||||
*/
|
||||
struct s3c64xx_dma_buff {
|
||||
struct s3c64xx_dma_buff *next;
|
||||
|
||||
void *pw;
|
||||
struct pl080_lli *lli;
|
||||
dma_addr_t lli_dma;
|
||||
};
|
||||
|
||||
struct s3c64xx_dmac;
|
||||
|
||||
struct s3c2410_dma_chan {
|
||||
unsigned char number; /* number of this dma channel */
|
||||
unsigned char in_use; /* channel allocated */
|
||||
unsigned char bit; /* bit for enable/disable/etc */
|
||||
unsigned char hw_width;
|
||||
unsigned char peripheral;
|
||||
|
||||
unsigned int flags;
|
||||
enum s3c2410_dmasrc source;
|
||||
|
||||
|
||||
dma_addr_t dev_addr;
|
||||
|
||||
struct s3c2410_dma_client *client;
|
||||
struct s3c64xx_dmac *dmac; /* pointer to controller */
|
||||
|
||||
void __iomem *regs;
|
||||
|
||||
/* cdriver callbacks */
|
||||
s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
|
||||
s3c2410_dma_opfn_t op_fn; /* channel op callback */
|
||||
|
||||
/* buffer list and information */
|
||||
struct s3c64xx_dma_buff *curr; /* current dma buffer */
|
||||
struct s3c64xx_dma_buff *next; /* next buffer to load */
|
||||
struct s3c64xx_dma_buff *end; /* end of queue */
|
||||
|
||||
/* note, when channel is running in circular mode, curr is the
|
||||
* first buffer enqueued, end is the last and curr is where the
|
||||
* last buffer-done event is set-at. The buffers are not freed
|
||||
* and the last buffer hardware descriptor points back to the
|
||||
* first.
|
||||
*/
|
||||
};
|
||||
|
||||
#include <plat/dma-core.h>
|
|
@ -157,6 +157,7 @@
|
|||
|
||||
#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE)
|
||||
#define IRQ_EINT(x) S3C_EINT(x)
|
||||
#define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0))
|
||||
|
||||
/* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
|
||||
* that they are sourced from the GPIO pins but with a different scheme for
|
||||
|
|
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